1 /**
2 * @file xmc_eth_phy_ksz8081rnb.c
3 * @date 2018-08-06
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-06-20:
40 * - Initial
41 *
42 * 2015-12-15:
43 * - Added Reset and exit power down
44 * - Reset function called in Init function
45 *
46 * 2018-08-06:
47 * - Fixed XMC_ETH_PHY_Init waiting for PHY MDIO being ready
48 *
49 * @endcond
50 */
51
52 /*******************************************************************************
53 * HEADER FILES
54 *******************************************************************************/
55 #if defined(XMC_ETH_PHY_KSZ8081RNB)
56 #include <xmc_eth_phy.h>
57
58 /*******************************************************************************
59 * MACROS
60 *******************************************************************************/
61
62 /* Basic Registers */
63 #define REG_BMCR (0x00U) /* Basic Mode Control Register */
64 #define REG_BMSR (0x01U) /* Basic Mode Status Register */
65 #define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */
66 #define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */
67 #define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */
68 #define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */
69 #define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */
70 #define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */
71
72 /* Extended Registers */
73 #define REG_PHYCTRL1 (0x1eU) /* PHY control 1 Register */
74
75 /* Basic Mode Control Register */
76 #define BMCR_RESET (0x8000U) /* Software Reset */
77 #define BMCR_LOOPBACK (0x4000U) /* Loopback mode */
78 #define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */
79 #define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */
80 #define BMCR_POWER_DOWN (0x0800U) /* Power Down */
81 #define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */
82 #define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */
83 #define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */
84 #define BMCR_COL_TEST (0x0080U) /* Collision Test */
85
86 /* Basic Mode Status Register */
87 #define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */
88 #define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */
89 #define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */
90 #define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */
91 #define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */
92 #define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */
93 #define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */
94 #define BMSR_REM_FAULT (0x0010U) /* Remote Fault */
95 #define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */
96 #define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */
97 #define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */
98 #define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */
99
100 /* PHY control 1 Register */
101 #define PHYCTRL1_OPMODE_SPEED (0x0003U)
102 #define PHYCTRL1_OPMODE_DUPLEX (0x0004U)
103
104 /* PHY Identifier Registers */
105 #define PHY_ID1 (0x0022U) /* KSZ8031 Device Identifier MSB */
106 #define PHY_ID2 (0x1560U) /* KSZ8031 Device Identifier LSB */
107
108 /*******************************************************************************
109 * API IMPLEMENTATION
110 *******************************************************************************/
111
112 /* Check if the device identifier is valid */
XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr)113 static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
114 {
115 uint16_t phy_id1;
116 uint16_t phy_id2;
117 XMC_ETH_PHY_STATUS_t status;
118
119 /* Check Device Identification. */
120 if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) &&
121 (XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK))
122 {
123 if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2))
124 {
125 status = XMC_ETH_PHY_STATUS_OK;
126 }
127 else
128 {
129 status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID;
130 }
131 }
132 else
133 {
134 status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT;
135 }
136
137 return (int32_t)status;
138 }
139
140 /* PHY initialize */
XMC_ETH_PHY_Init(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr,const XMC_ETH_PHY_CONFIG_t * const config)141 int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config)
142 {
143 uint32_t retries = 0xffffffffUL;
144 int32_t status;
145 uint16_t reg_bmcr;
146
147 while (((status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr)) != XMC_ETH_PHY_STATUS_OK) && --retries);
148
149 if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
150 {
151 status = XMC_ETH_PHY_Reset(eth_mac, phy_addr);
152
153 if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
154 {
155 reg_bmcr = 0U;
156 if (config->speed == XMC_ETH_LINK_SPEED_100M)
157 {
158 reg_bmcr |= BMCR_SPEED_SEL;
159 }
160
161 if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL)
162 {
163 reg_bmcr |= BMCR_DUPLEX;
164 }
165
166 if (config->enable_auto_negotiate == true)
167 {
168 reg_bmcr |= BMCR_ANEG_EN;
169 }
170
171 if (config->enable_loop_back == true)
172 {
173 reg_bmcr |= BMCR_LOOPBACK;
174 }
175
176 status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
177 }
178 }
179
180 return status;
181 }
182
183 /* Reset */
XMC_ETH_PHY_Reset(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr)184 int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
185 {
186 int32_t status;
187 uint16_t reg_bmcr;
188
189 /* Reset PHY*/
190 status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET);
191 if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
192 {
193 /* Wait for the reset to complete */
194 do
195 {
196 status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr);
197 } while ((reg_bmcr & BMCR_RESET) != 0);
198 }
199
200 return status;
201 }
202
203 /* Initiate power down */
XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr)204 int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
205 {
206 int32_t status;
207 uint16_t reg_bmcr;
208
209 status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr);
210 if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
211 {
212 reg_bmcr |= BMCR_POWER_DOWN;
213 status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
214 }
215 return status;
216 }
217
218 /* Exit power down */
XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr)219 int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
220 {
221 int32_t status;
222 uint16_t reg_bmcr;
223
224 status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr);
225 if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
226 {
227 reg_bmcr &= ~BMCR_POWER_DOWN;
228 status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
229 }
230 return status;
231 }
232
233 /* Get link status */
XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr)234 XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
235 {
236 uint16_t val;
237
238 XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
239
240 return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN);
241 }
242
243 /* Get link speed */
XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr)244 XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
245 {
246 uint16_t val;
247
248 XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val);
249
250 return (XMC_ETH_LINK_SPEED_t)(((val & PHYCTRL1_OPMODE_SPEED) - 1U) ? XMC_ETH_LINK_SPEED_100M : XMC_ETH_LINK_SPEED_10M);
251 }
252
253 /* Get link duplex settings */
XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr)254 XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
255 {
256 uint16_t val;
257
258 XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val);
259
260 return (XMC_ETH_LINK_DUPLEX_t)((val & PHYCTRL1_OPMODE_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF);
261 }
262
XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t * const eth_mac,uint8_t phy_addr)263 bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
264 {
265 uint16_t val;
266
267 XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
268 return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL);
269 }
270 #endif // XMC_ETH_PHY_KSZ8081RNB
271
