1 /**
2  * @file xmc4_flash.h
3  * @date 2019-05-06
4  *
5  * @cond
6  *********************************************************************************************************************
7  * XMClib v2.1.24 - XMC Peripheral Driver Library
8  *
9  * Copyright (c) 2015-2019, Infineon Technologies AG
10  * All rights reserved.
11  *
12  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13  * following conditions are met:
14  *
15  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16  * disclaimer.
17  *
18  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19  * disclaimer in the documentation and/or other materials provided with the distribution.
20  *
21  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22  * products derived from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33  * Infineon Technologies AG dave@infineon.com).
34  *********************************************************************************************************************
35  *
36  * Change History
37  * --------------
38  *
39  * 2014-12-10:
40  *     - Initial <br>
41  * 2015-02-20:
42  *     - Updated for Documentation related changes<br>
43  * 2015-06-20:
44  *     - Removed version macros and declaration of GetDriverVersion API
45  * 2015-08-17:
46  *     - Added the below API's to the public interface.
47  *       1. XMC_FLASH_Reset
48  *       2. XMC_FLASH_ErasePhysicalSector
49  *       3. XMC_FLASH_EraseUCB
50  *       4. XMC_FLASH_ResumeProtection
51  *       5. XMC_FLASH_RepairPhysicalSector
52  *     - Added support for XMC4800/4700 devices
53  * 2015-12-07:
54  *     - Fix XMC_FLASH_READ_ACCESS_TIME for XMC43, 47 and 48 devices
55  * 2016-03-18:
56  *     - Fix implementation of XMC_PREFETCH_EnableInstructionBuffer and XMC_PREFETCH_DisableInstructionBuffer
57  * 2016-03-22:
58  *     - Fix implementation of XMC_PREFETCH_InvalidateInstructionBuffer
59  *
60  * 2018-02-08:
61  *     - Added XMC_FLASH_InstallBMI()
62  *
63  * 2019-03-30:
64  *     - Fix compilation warnings
65  *
66  * 2019-05-06:
67  *     - Moved definitions of XMC_FLASH_ProgramPage() and XMC_FLASH_EraseSector() from xmc_flash.h
68  *
69  * @endcond
70  *
71  */
72 
73 #ifndef XMC4_FLASH_H
74 #define XMC4_FLASH_H
75 
76 /*********************************************************************************************************************
77  * HEADER FILES
78  ********************************************************************************************************************/
79 
80 #include "xmc_common.h"
81 
82 #if UC_FAMILY == XMC4
83 
84 /**
85  * @addtogroup XMClib XMC Peripheral Library
86  * @{
87  */
88 
89 /**
90  * @addtogroup FLASH
91  * @{
92  */
93 
94 /*********************************************************************************************************************
95  * MACROS
96  ********************************************************************************************************************/
97 #define XMC_FLASH_UNCACHED_BASE    (0x0C000000U) /**< Non cached flash starting address of for
98                                                       XMC4 family of microcontrollers */
99 #define XMC_FLASH_WORDS_PER_PAGE   (64UL)        /**< Number of words in a page (256 bytes / 4 bytes = 64 words)*/
100 #define XMC_FLASH_BYTES_PER_PAGE   (256UL)       /**< Number of bytes in a  page*/
101 
102 #define XMC_FLASH_UCB0             (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0000UL) /**< Starting address of User
103                                                                                          Configurable Block 0*/
104 #define XMC_FLASH_UCB1             (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0400UL) /**< Starting address of User
105                                                                                          Configurable Block 1*/
106 #define XMC_FLASH_UCB2             (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0800UL) /**< Starting address of User
107                                                                                          Configurable Block 2*/
108 #define XMC_FLASH_BYTES_PER_UCB    (1024UL) /**< Number of bytes in a user configurable block*/
109 
110 /**< Note : Total number of Sectors depends on the flash size of the controller. So while using these macros for flash
111  *          operations ensure that sector is available, other may lead to flash error.
112  */
113 #define XMC_FLASH_SECTOR_0         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x00000UL) /**<Starting address of sector0 */
114 #define XMC_FLASH_SECTOR_1         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x04000UL) /**<Starting address of sector1 */
115 #define XMC_FLASH_SECTOR_2         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x08000UL) /**<Starting address of sector2 */
116 #define XMC_FLASH_SECTOR_3         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0C000UL) /**<Starting address of sector3 */
117 #define XMC_FLASH_SECTOR_4         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x10000UL) /**<Starting address of sector4 */
118 #define XMC_FLASH_SECTOR_5         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x14000UL) /**<Starting address of sector5 */
119 #define XMC_FLASH_SECTOR_6         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x18000UL) /**<Starting address of sector6 */
120 #define XMC_FLASH_SECTOR_7         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x1C000UL) /**<Starting address of sector7 */
121 #define XMC_FLASH_SECTOR_8         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x20000UL) /**<Starting address of sector8 */
122 #define XMC_FLASH_SECTOR_9         (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x40000UL) /**<Starting address of sector9 */
123 #define XMC_FLASH_SECTOR_10        (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x80000UL) /**<Starting address of sector10*/
124 #define XMC_FLASH_SECTOR_11        (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xC0000UL) /**<Starting address of sector11*/
125 
126 #define XMC_FLASH_SECTOR_12        (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x100000UL) /**<Starting address of sector12*/
127 #define XMC_FLASH_SECTOR_13        (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x140000UL) /**<Starting address of sector13*/
128 #define XMC_FLASH_SECTOR_14        (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x180000UL) /**<Starting address of sector14*/
129 #define XMC_FLASH_SECTOR_15        (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x1C0000UL) /**<Starting address of sector15*/
130 
131 #define XMC_FLASH_PHY_SECTOR_0     (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x00000UL) /**<Starting address of non cached
132                                                                                          physical sector0 */
133 #define XMC_FLASH_PHY_SECTOR_4     (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x10000UL) /**<Starting address of non cached
134                                                                                          physical sector4 */
135 #define XMC_FLASH_PHY_SECTOR_8     (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x20000UL) /**<Starting address of non cached
136                                                                                          physical sector8 */
137 #define XMC_FLASH_PHY_SECTOR_9     (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x40000UL) /**<Starting address of non cached
138                                                                                          physical sector9 */
139 #define XMC_FLASH_PHY_SECTOR_10    (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x80000UL) /**<Starting address of non cached
140                                                                                          physical sector10 */
141 #define XMC_FLASH_PHY_SECTOR_11    (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xC0000UL) /**<Starting address of non cached
142                                                                                          physical sector11 */
143 #define XMC_FLASH_PHY_SECTOR_12    (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x100000UL) /**<Starting address of non cached
144                                                                                          physical sector12 */
145 #define XMC_FLASH_PHY_SECTOR_13    (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x140000UL) /**<Starting address of non cached
146                                                                                          physical sector13 */
147 #define XMC_FLASH_PHY_SECTOR_14    (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x180000UL) /**<Starting address of non cached
148                                                                                          physical sector14 */
149 #define XMC_FLASH_PHY_SECTOR_15    (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x1C0000UL) /**<Starting address of non cached
150                                                                                          physical sector15 */
151 
152 #if UC_SERIES == XMC45 || UC_SERIES == XMC43 || UC_SERIES == XMC47 || UC_SERIES == XMC48
153 #define XMC_FLASH_READ_ACCESS_TIME (22E-9F) /* Flash read access time  */
154 #else
155 #define XMC_FLASH_READ_ACCESS_TIME (20E-9F)
156 #endif
157 
158 #define XMC_FLASH_BMI_VALID (uint32_t)(0x1 << 31) /**< This is always 0 in UCB. The copy of this BMI word in DSRAM1 has this ?BMI Valid? bit set to 1 after SSW has validated the XOR checksum */
159 
160 /*********************************************************************************************************************
161  * ENUMS
162  ********************************************************************************************************************/
163 /**
164  *  Defines the return status of the API.
165  */
166 typedef enum XMC_FLASH_STATUS
167 {
168   XMC_FLASH_STATUS_OK                               = 0U,                 /**< Operation completed successfully*/
169   XMC_FLASH_STATUS_BUSY                             = FLASH_FSR_PBUSY_Msk, /**< API cannot proceed since FLASH is busy*/
170   XMC_FLASH_STATUS_PROGRAMMING_STATE                = FLASH_FSR_PROG_Msk, /**< Write page is in progress or finished */
171   XMC_FLASH_STATUS_ERASE_STATE                      = FLASH_FSR_ERASE_Msk, /**< Erase page is in progress or finished */
172   XMC_FLASH_STATUS_PAGE_MODE                        = FLASH_FSR_PFPAGE_Msk, /**< Flash is in page mode. Assembly buffer
173                                                                                  of PFLASH is in use */
174   XMC_FLASH_STATUS_OPERATION_ERROR                  = FLASH_FSR_PFOPER_Msk, /**< Flash Operation aborted */
175   XMC_FLASH_STATUS_COMMAND_SEQUENCE_ERROR           = FLASH_FSR_SQER_Msk, /**< Improper address or Invalid state machine
176                                                                                operation */
177   XMC_FLASH_STATUS_PROTECTION_ERROR                 = FLASH_FSR_PROER_Msk, /**< Flash operation addressing the locked
178                                                                                 sector */
179   XMC_FLASH_STATUS_SINGLE_BIT_ERROR_AND_CORRECTION  = FLASH_FSR_PFSBER_Msk, /**< Single bit error detected and
180                                                                                  corrected */
181   XMC_FLASH_STATUS_DOUBLE_BIT_ERROR                 = FLASH_FSR_PFDBER_Msk, /**< Multiple bit error occurred */
182   XMC_FLASH_STATUS_PROTECTION_INSTALLED             = FLASH_FSR_PROIN_Msk, /**< Confirmation of the read or/and write
183                                                                                 protection is successful */
184   XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED        = FLASH_FSR_RPROIN_Msk, /**< Confirmation of read and global write
185                                                                                  protection is successful for user-0 */
186   XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE   = FLASH_FSR_RPRODIS_Msk, /**< Read or/and write protection is
187                                                                                   temporarily disabled */
188   XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB0  = FLASH_FSR_WPROIN0_Msk, /**< Sector write protection is installed
189                                                                                   for user-0 */
190   XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB1  = FLASH_FSR_WPROIN1_Msk, /**< Sector write protection is installed
191                                                                                   for user-1 */
192   XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB2  = FLASH_FSR_WPROIN2_Msk, /**< Sector OTP protection is installed
193                                                                                   for user-2 */
194   XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB0   = FLASH_FSR_WPRODIS0_Msk, /**< Sector write protection is disabled
195                                                                                   for user-0 */
196   XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB1   = FLASH_FSR_WPRODIS1_Msk, /**< Sector write protection is disabled
197                                                                                   for user-1 */
198   XMC_FLASH_STATUS_SLEEP_MODE                       = FLASH_FSR_SLM_Msk, /**< Indicates flash in sleep mode or not  */
199   XMC_FLASH_STATUS_VERIFY_ERROR                     = (int32_t)FLASH_FSR_VER_Msk, /**< Write verification and Erase
200                                                                                        verification error occurred  */
201 } XMC_FLASH_STATUS_t;
202 
203 /**
204  *  Provides the options to select flash margin read settings of the for quality assurance.
205  */
206 typedef enum XMC_FLASH_MARGIN
207 {
208   XMC_FLASH_MARGIN_DEFAULT = 0x0U << FLASH_MARP_MARGIN_Pos, /**< Default margin */
209   XMC_FLASH_MARGIN_TIGHT0  = 0x1U << FLASH_MARP_MARGIN_Pos, /**< Sub-optimal 0-bits are read as 1s */
210   XMC_FLASH_MARGIN_TIGHT1  = 0x4U << FLASH_MARP_MARGIN_Pos  /**< Sub-optimal 1-bits are read as 0s */
211 } XMC_FLASH_MARGIN_t;
212 
213 /**
214  *  Provides the options to select flash operational events
215  */
216 typedef enum XMC_FLASH_EVENT
217 {
218   XMC_FLASH_EVENT_VERIFY_AND_OPERATION_ERROR = 0x01U << FLASH_FCON_VOPERM_Pos, /**< Flash verify and operation error
219                                                                                     event */
220   XMC_FLASH_EVENT_COMMAND_SEQUENCE_ERROR     = 0x02U << FLASH_FCON_VOPERM_Pos, /**< Flash command sequence error event*/
221   XMC_FLASH_EVENT_PROTECTION_ERROR           = 0x04U << FLASH_FCON_VOPERM_Pos, /**< Flash protection error event */
222   XMC_FLASH_EVENT_SINGLE_BIT_ERROR           = 0x08U << FLASH_FCON_VOPERM_Pos, /**< Flash single bit error event */
223   XMC_FLASH_EVENT_DOUBLE_BIT_ERROR           = 0x20U << FLASH_FCON_VOPERM_Pos, /**< Flash double bit error event*/
224   XMC_FLASH_EVENT_END_OF_BUSY                = (int32_t)(0x80U << FLASH_FCON_VOPERM_Pos) /**< Flash end of busy event*/
225 } XMC_FLASH_EVENT_t;
226 
227 /**
228  * Provides the options to select sectors for write protection and select global read protection.
229  * The members can be combined using 'OR' operator for multiple selection.<br>
230  *
231  */
232 typedef enum XMC_FLASH_PROTECTION
233 {
234   XMC_FLASH_PROTECTION_WRITE_SECTOR_0      = 0x0001UL,  /**< Sector 0 write protection */
235   XMC_FLASH_PROTECTION_WRITE_SECTOR_1      = 0x0002UL,  /**< Sector 1 write protection */
236   XMC_FLASH_PROTECTION_WRITE_SECTOR_2      = 0x0004UL,  /**< Sector 3 write protection */
237   XMC_FLASH_PROTECTION_WRITE_SECTOR_3      = 0x0008UL,  /**< Sector 3 write protection */
238   XMC_FLASH_PROTECTION_WRITE_SECTOR_4      = 0x0010UL,  /**< Sector 4 write protection */
239   XMC_FLASH_PROTECTION_WRITE_SECTOR_5      = 0x0020UL,  /**< Sector 5 write protection */
240   XMC_FLASH_PROTECTION_WRITE_SECTOR_6      = 0x0040UL,  /**< Sector 6 write protection */
241   XMC_FLASH_PROTECTION_WRITE_SECTOR_7      = 0x0080UL,  /**< Sector 7 write protection */
242   XMC_FLASH_PROTECTION_WRITE_SECTOR_8      = 0x0100UL,  /**< Sector 8 write protection */
243   XMC_FLASH_PROTECTION_WRITE_SECTOR_9      = 0x0200UL,  /**< Sector 9 write protection */
244   XMC_FLASH_PROTECTION_WRITE_SECTORS_10_11 = 0x0400UL,  /**< Sector 10 and 11 write protection */
245   XMC_FLASH_PROTECTION_WRITE_SECTORS_12_13 = 0x0800UL,  /**< Sector 12 and 13 write protection */
246   XMC_FLASH_PROTECTION_WRITE_SECTORS_14_15 = 0x1000UL,  /**< Sector 14 and 15 write protection */
247   XMC_FLASH_PROTECTION_READ_GLOBAL         = 0x8000UL   /**< Global read protection (Applicable for UserLevel0 alone)*/
248 } XMC_FLASH_PROTECTION_t;
249 
250 /**
251  * BMI Word configuration
252  */
253 typedef enum XMC_FLASH_BMI
254 {
255   XMC_FLASH_BMI_BOOT_MODE_NORMAL = 0x0UL, /**< Normal boot mode */
256   XMC_FLASH_BMI_BOOT_MODE_ASC_BSL = 0x1UL, /**< ASC BSL boot mode */
257   XMC_FLASH_BMI_BOOT_MODE_CAN_BSL = 0x3UL, /**< CAN BSL boot mode */
258   XMC_FLASH_BMI_BOOT_MODE_PSRAM = 0x4UL, /**< PSRAM boot mode */
259   XMC_FLASH_BMI_BOOT_MODE_ABM0 = 0x5UL, /**< ABM0 boot mode */
260   XMC_FLASH_BMI_BOOT_MODE_ABM1 = 0x6UL, /**< ABM1 boot mode */
261   XMC_FLASH_BMI_BOOT_MODE_FALLBACK_ABM = 0x7UL, /**< Fallback ABM boot mode */
262   XMC_FLASH_BMI_MAC_BIT_MSK = 0x1UL << 5, /**< Valid MAC address part of BMI string */
263   XMC_FLASH_BMI_IPV4_BIT_MSK = 0x1UL << 7, /**< Ethernet IP extension contains a IPv4 address */
264   XMC_FLASH_BMI_IPV6_BIT_MSK = 0x1UL << 8, /**< Ethernet IP extension contains a IPv6 address */
265   XMC_FLASH_BMI_USB_BIT_MAK = 0x1UL << 10, /**< Valid USB Serial Number part of BMI string */
266   XMC_FLASH_BMI_PAI_PSRAM_MSK = 0x1UL << 12, /**< Parity of PSRAM to be initialized by SSW */
267   XMC_FLASH_BMI_PAI_DSRAM_MSK = 0x1UL << 13, /**< Parity of DSRAM1 to be initialized by SSW */
268   XMC_FLASH_BMI_PAI_CMSRAM_MSK = 0x1UL << 14, /**< Parity of DSRAM-Comm to be initialized by SSW */
269   XMC_FLASH_BMI_SPEEDUP_BIT_MSK = 0x1UL << 15, /**< Clock Tree of the device to be setup to maximum frequency */
270 } XMC_FLASH_BMI_t;
271 
272 /**
273  * BMI String configuration
274  */
275 typedef struct XMC_FLASH_BMI_STRING
276 {
277   uint32_t bmi; /**< See ::XMC_FLASH_BMI_t */
278   uint8_t mac_addr[6]; /**< MAC address extension */
279   uint8_t ip_extension[16]; /**< Ethernet IP extension */
280   uint8_t usb_serial_no[4]; /**< USB Serial Number */
281   uint32_t reserved;
282   uint16_t reserved1;
283 } XMC_FLASH_BMI_STRING_t;
284 
285 /*********************************************************************************************************************
286  * API PROTOTYPES
287  ********************************************************************************************************************/
288 
289 #ifdef __cplusplus
290 extern "C" {
291 #endif
292 
293 /**
294  *
295  * @param address    Pointer to the starting address of flash page from where the programming starts.
296  * @param data       Pointer to the source address where targeted data is located.
297  *
298  * @return None
299  *
300  * \par<b>Description:</b><br>
301  * Programs a single flash page associated with the specified \a address.\n\n  XMC4000 flash can be programmed with a
302  * granularity of 256 bytes page using this API. Before entering into page write process, it clears the error status
303  * bits inside status register. It starts the write process by issuing the page mode command followed by the load page
304  * command which loads the targeted \a data blocks into internal assembly buffer. Finally, it issues the write page
305  * command which programs the \a data into flash. Call XMC_FLASH_GetStatus() API after calling this API, to verify the
306  * programming operation.\n
307  *
308  * \par<b>Note:</b><br>
309  * Flash will be busy state during write is ongoing, hence no operations allowed until it completes.
310  *
311  * \par<b>Related APIs:</b><BR>
312  * None
313  *
314  */
315 void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data);
316 
317 /**
318  *
319  * @param address Pointer to the starting address of the page to be erased.
320  *
321  * @return None
322  *
323  * \par<b>Description:</b><br>
324  * Erases a sector associated with the specified \a address.\n\n  Before erase, it clears the error status bits inside
325  * FSR status register. Issues the erase sector command sequence with the specified starting \a address to start flash
326  * erase process. Call XMC_FLASH_GetStatus() API after calling this API, to verify the erase operation.\n
327  *
328  * \par<b>Related APIs:</b><BR>
329  * None
330  */
331 void XMC_FLASH_EraseSector(uint32_t *address);
332 
333 /**
334  *
335  * @param None
336  *
337  * @return None
338  *
339  * \par<b>Description:</b><br>
340  * Enables the wait state for error correction.process, It enables one additional wait state for ECC by setting WSECPF
341  * bit of FCON register.\n
342  *
343  * \par<b>Related APIs:</b><BR>
344  * XMC_FLASH_DisableWaitStateForECC()\n\n\n
345  *
346  */
XMC_FLASH_EnableWaitStateForECC(void)347 __STATIC_INLINE void XMC_FLASH_EnableWaitStateForECC(void)
348 {
349   FLASH0->FCON |= FLASH_FCON_WSECPF_Msk;
350 }
351 
352 /**
353  *
354  * @param None
355  *
356  * @return None
357  *
358  * \par<b>Description:</b><br>
359  * Disables the wait state for error correction.\n\n Removes additional wait state for ECC by resetting WSECPF bit of
360  * FCON register.\n
361  *
362  * \par<b>Related APIs:</b><BR>
363  * XMC_FLASH_EnableWaitStateForECC()\n\n\n
364  *
365  */
XMC_FLASH_DisableWaitStateForECC(void)366 __STATIC_INLINE void XMC_FLASH_DisableWaitStateForECC(void)
367 {
368   FLASH0->FCON &= (uint32_t)~FLASH_FCON_WSECPF_Msk;
369 }
370 
371 /**
372  *
373  * @param None
374  *
375  * @return None
376  *
377  * \par<b>Description:</b><br>
378  * Enables dynamic idle mode feature to save power.\n\n It switches off the PFLASH read path when no read access is
379  * pending. Hence power is saved marginally. This slightly reduces the flash read performance because static
380  * pre-fetching is disabled.It sets the FCON register IDLE bit to enable this feature.
381  *
382  * \par<b>Related APIs:</b><BR>
383  * XMC_FLASH_DisableDynamicIdle()\n\n\n
384  *
385  */
XMC_FLASH_EnableDynamicIdle(void)386 __STATIC_INLINE void XMC_FLASH_EnableDynamicIdle(void)
387 {
388   FLASH0->FCON |= FLASH_FCON_IDLE_Msk;
389 }
390 
391 /**
392  *
393  * @param None
394  *
395  * @return None
396  *
397  * \par<b>Description:</b><br>
398  * Disables dynamic idle mode feature.\n\n It resets the FCON register IDLE bit to disable this feature. Hence normal
399  * flash read operation is selected.
400  *
401  * \par<b>Related APIs:</b><BR>
402  * XMC_FLASH_EnableDynamicIdle()\n\n\n
403  *
404  */
XMC_FLASH_DisableDynamicIdle(void)405 __STATIC_INLINE void XMC_FLASH_DisableDynamicIdle(void)
406 {
407   FLASH0->FCON &= (uint32_t)~FLASH_FCON_IDLE_Msk;
408 }
409 
410 /**
411  *
412  * @param None
413  *
414  * @return None
415  *
416  * \par<b>Description:</b><br>
417  * Enables sleep mode of the PFLASH.\n\n Sleep mode is enabled by setting the bit FCON.SLEEP.
418  *
419  * \par<b>Note:</b><br>
420  * fCPU must be equal or above 1 MHz when wake-up request is triggered.
421  *
422  * \par<b>Related APIs:</b><BR>
423  * XMC_FLASH_DisableSleepRequest()\n\n\n
424  *
425  */
XMC_FLASH_EnableSleepRequest(void)426 __STATIC_INLINE void XMC_FLASH_EnableSleepRequest(void)
427 {
428   FLASH0->FCON |= (uint32_t)FLASH_FCON_SLEEP_Msk;
429 }
430 
431 /**
432  *
433  * @param None
434  *
435  * @return None
436  *
437  * \par<b>Description:</b><br>
438  * Wake-up the PFLASH from sleep.\n\n Wakes-up from sleep is done by clearing the bit FCON.SLEEP, if selected via this
439  * bit, or wake-up is initiated by releasing the external sleep signal from SCU.
440  *
441  * \par<b>Note:</b><br>
442  * fCPU must be equal or above 1 MHz when wake-up request is triggered.
443  *
444  * \par<b>Related APIs:</b><BR>
445  * XMC_FLASH_EnableSleepRequest()\n\n\n
446  *
447  */
XMC_FLASH_DisableSleepRequest(void)448 __STATIC_INLINE void XMC_FLASH_DisableSleepRequest(void)
449 {
450   FLASH0->FCON &= (uint32_t)~FLASH_FCON_SLEEP_Msk;
451 }
452 
453 /**
454  *
455  * @param margin PFLASH margin selection. Use type @ref XMC_FLASH_MARGIN_t.
456  *
457  * @return None
458  *
459  * \par<b>Description:</b><br>
460  * Sets the read margin levels for checking the healthiness of flash data.\n\n Configures the margin field of MARP
461  * MARP register with the specified \a margin level. It changes the margin levels for read operations to find
462  * problematic array bits.
463  *
464  * \par<b>Related APIs:</b><BR>
465  * None
466  */
XMC_FLASH_SetMargin(const XMC_FLASH_MARGIN_t margin)467 __STATIC_INLINE void XMC_FLASH_SetMargin(const XMC_FLASH_MARGIN_t margin)
468 {
469   FLASH0->MARP = (FLASH0->MARP & (uint32_t)~FLASH_MARP_MARGIN_Msk) | margin;
470 }
471 
472 /**
473  *
474  * @param None
475  *
476  * @return None
477  *
478  * \par<b>Description:</b><br>
479  * Enables double bit error trap.\n\n. It enables by setting MARP register bit TRAPDIS.
480  *
481  * \par<b>Related APIs:</b><BR>
482  * None
483  */
XMC_FLASH_EnableDoubleBitErrorTrap(void)484 __STATIC_INLINE void XMC_FLASH_EnableDoubleBitErrorTrap(void)
485 {
486   FLASH0->MARP &= (uint32_t)~FLASH_MARP_TRAPDIS_Msk;
487 }
488 
489 /**
490  *
491  * @param None
492  *
493  * @return None
494  *
495  * \par<b>Description:</b><br>
496  * Disables the trap generation for double bit error by clearing MARP register bit TRAPDIS.\n\n The double-bit error
497  * trap can be disabled for margin checks and also redirected to an error interrupt. Any time during the execution the
498  * double bit error trap can be enabled back by calling XMC_FLASH_EnableDoubleBitErrorTrap() API.
499  *
500  * \par<b>Related APIs:</b><BR>
501  * None
502  */
XMC_FLASH_DisableDoubleBitErrorTrap(void)503 __STATIC_INLINE void XMC_FLASH_DisableDoubleBitErrorTrap(void)
504 {
505   FLASH0->MARP |= FLASH_MARP_TRAPDIS_Msk;
506 }
507 
508 /**
509  *
510  * @param num_wait_states number of wait states for initial read access<BR> Range:  [0 to 15]
511  *
512  * @return None
513  *
514  * \par<b>Description:</b><br>
515  * Configures the number of wait states for initial flash read access.\n\n Depending on the configured \a
516  * num_wait_states value into FCON resister \a WSPFLASH field, the read performance gets optimized . The wait cycles
517  * for the flash read access must be configured based on the CPU frequency (fCPU), in relation to the flash access
518  * time (\a ta) defined. The access time formula  (\a WSPFLASH x (\a \a \a 1 / fCPU) \a >= \a ta) applies only for
519  * the values \a \a \a num_wait_states >0.
520  *
521  * \par<b>Related APIs:</b><BR>
522  * None
523  */
XMC_FLASH_SetWaitStates(uint32_t num_wait_states)524 __STATIC_INLINE void XMC_FLASH_SetWaitStates(uint32_t num_wait_states)
525 {
526   FLASH0->FCON = (FLASH0->FCON & (uint32_t)~FLASH_FCON_WSPFLASH_Msk) |
527                  (num_wait_states << FLASH_FCON_WSPFLASH_Pos);
528 }
529 
530 /**
531  *
532  * @param None
533  *
534  * @return None
535  *
536  * \par<b>Description:</b><br>
537  * Configures the cacheable accesses to use the instruction buffer by resetting the register bit PREF_PCON.IBYP.
538  *
539  * \par<b>Related APIs:</b><BR>
540  * None
541  */
XMC_PREFETCH_EnableInstructionBuffer(void)542 __STATIC_INLINE void XMC_PREFETCH_EnableInstructionBuffer(void)
543 {
544 	PREF->PCON &= (uint32_t)~PREF_PCON_IBYP_Msk;
545 }
546 
547 /**
548  *
549  * @param None
550  *
551  * @return None
552  *
553  * \par<b>Description:</b><br>
554  * Bypasses the instruction buffer for cacheable accesses, by setting the register bit PREF_PCON.IBYP.
555  *
556  * \par<b>Related APIs:</b><BR>
557  * None
558  */
XMC_PREFETCH_DisableInstructionBuffer(void)559 __STATIC_INLINE void XMC_PREFETCH_DisableInstructionBuffer(void)
560 {
561 	PREF->PCON |= PREF_PCON_IBYP_Msk;
562 }
563 
564 /**
565  *
566  * @param None
567  *
568  * @return None
569  *
570  * \par<b>Description:</b><br>
571  * Invalidates the instruction buffer by setting PREF_PCON register bit IINV.\n\n After system reset, the instruction
572  * buffer is automatically invalidated.
573  *
574  * \par<b>Note:</b><br>
575  * The complete invalidation operation is performed in a single cycle.
576  *
577  * \par<b>Related APIs:</b><BR>
578  * None
579  */
XMC_PREFETCH_InvalidateInstructionBuffer(void)580 __STATIC_INLINE void XMC_PREFETCH_InvalidateInstructionBuffer(void)
581 {
582   PREF->PCON |= PREF_PCON_IINV_Msk;
583   __DSB();
584   __ISB();
585 
586   PREF->PCON &= ~PREF_PCON_IINV_Msk;
587   __DSB();
588   __ISB();
589 
590 }
591 
592 /**
593  * @param bmi_string BMI string configuration
594  *
595  * @return None
596  *
597  * \par<b>Description:</b><br>
598  * BMI provides a provision for end user to customize boot sequence.
599  * A 32 bit BMI word describes a set of activities that must be performed by SSW.
600  * BMI word along with associated parameters is known as the BMI string.
601  * The function calculates the XOR checksum of the BMI String.
602  * Before calling this function the UCB2 should be erased.
603  *
604  * \par<b>Related APIs:</b><BR>
605  * XMC_FLASH_EraseUCB()
606  */
607 void XMC_FLASH_InstallBMI(XMC_FLASH_BMI_STRING_t *const bmi_string);
608 
609 /**
610  *
611  * @param user ID number of the user configuration block (UCB).<BR> Range:  [0 to 2]
612  *
613  * @param protection_mask ORed values of @ref XMC_FLASH_PROTECTION_t enum type, for which sectors the protection
614  *                        has to be enabled.
615  * @param password_0 First password for protection.<BR> Range:  [0 to 4294967295]
616  * @param password_1 Second password for protection.<BR> Range:  [0 to 4294967295]
617  *
618  * @return None
619  *
620  * \par<b>Description:</b><br>
621  * Installs the global read and sector write protection.\n\n The installation starts by issuing the page mode entry
622  * command followed by the load page command. The load page command mode loads the required sectors intended for
623  * protection specified in \a protection_mask. It also loads the specified passwords \a password0 and \a password1
624  * respectively. Finally, it issues the write page command for the specified \a user configuration block. Calling
625  * XMC_FLASH_ConfirmProtection() after this API completes the protection process by freezing the sectors forever.
626  *
627  *
628  * \par<b>Related APIs:</b><BR>
629  * XMC_FLASH_ConfirmProtection()<BR>
630  * XMC_FLASH_VerifyReadProtection()<BR>
631  */
632 void XMC_FLASH_InstallProtection(uint8_t user,
633                                  uint32_t protection_mask,
634                                  uint32_t password_0,
635                                  uint32_t password_1);
636 
637 /**
638  *
639  * @param user ID number of the user configuration block (UCB).<BR> Range:  [0 to 2]
640  *
641  * @return None
642  *
643  * \par<b>Description:</b><br>
644  * Confirms the protection, so that sectors specified under \a user configurable block are locked forever.\n\n The
645  * protection shall be installed by calling XMC_FLASH_InstallProtection() before calling this API.
646  * The confirmation starts by issuing the page mode entry command followed by the load page command. The load page
647  * command issues the confirmation protection command for the sectors on which the protection installation was done.
648  * It also loads the specified passwords \a password0 and \a password1 respectively. Finally, it issues the confirm
649  * protection command for the specified \a user configuration block so that the sectors will be protected forever.
650  *
651  * \par<b>Related APIs:</b><BR>
652  * XMC_FLASH_InstallProtection()<BR>
653  *
654  */
655 void XMC_FLASH_ConfirmProtection(uint8_t user);
656 
657 /**
658  *
659  * @param password_0 First password used for protection.<BR> Range:  [0 to 4294967295]
660  * @param password_1 Second password used for protection.<BR> Range:  [0 to 4294967295]
661  *
662  * @return true if read protection installed properly else returns \a false.
663  *
664  * \par<b>Description:</b><br>
665  * Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection
666  * process, it clears the error status bits inside status register. It temporarily disables the protection with
667  * passwords \a password0 and \a password1 respectively. It reads the FSR register and verifies the protection state.
668  * Resumption of read protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset.
669  *
670  * \par<b>Related APIs:</b><BR>
671  * XMC_FLASH_InstallProtection()<BR>
672  * XMC_FLASH_VerifyWriteProtection()<BR>
673  * XMC_FLASH_ResumeProtection()<BR>
674  */
675 bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1);
676 
677 /**
678  *
679  * @param user ID number of the user configuration block (UCB).<BR> Range:  [0 to 2]
680  *
681  * @param protection_mask ORed values of @ref XMC_FLASH_PROTECTION_t enum type, for which sectors the protection
682  *                        has to be verified.
683  * @param password_0 First password used for protection.<BR> Range:  [0 to 4294967295]
684  * @param password_1 Second password used for protection.<BR> Range:  [0 to 4294967295]
685  *
686  * @return true if write protection installed properly else returns \a false.
687  *
688  * \par<b>Description:</b><br>
689  * Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection
690  * process, it clears the error status bits inside status register. It temporarily disables the protection with
691  * passwords \a password0 and \a password1 respectively for the intended sectors specified in \a protection_mask.
692  * It reads the FSR register and verifies the write protection state.
693  * Resumption of write protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset.
694  *
695  * \par<b>Related APIs:</b><BR>
696  * XMC_FLASH_InstallProtection()<BR>
697  * XMC_FLASH_VerifyReadProtection()<BR>
698  * XMC_FLASH_ResumeProtection()<BR>
699  */
700 bool XMC_FLASH_VerifyWriteProtection(uint32_t user,
701                                      uint32_t protection_mask,
702                                      uint32_t password_0,
703                                      uint32_t password_1);
704 
705 /**
706  *
707  * @param None
708  *
709  * @return None
710  *
711  * \par<b>Description:</b><br>
712  * Resumes flash protection as it was configured before.\n\n
713  * It clears all the disable proection status flags FSR.WPRODISx and FSR.RPRODIS. But FSR.WPRODISx is not
714  * cleared when corresponding UCBx is not in the ?confirmed? state.
715  *
716  * \par<b>Related APIs:</b><BR>
717  * None
718  */
719 void XMC_FLASH_ResumeProtection(void);
720 
721 /**
722  *
723  * @param None
724  *
725  * @return None
726  *
727  * \par<b>Description:</b><br>
728  * Repairs the physical sector "PS4".\n\n
729  * For selected devices, Erase Physical Sector can also be used for Sector Soft Repair, depending on the configuration
730  * of PROCON1.PSR. This command sequence is required to run an EEPROM emulation algorithm that cycles the logical
731  * sectors S4..S7 of PS4. This command sequence repairs the corrupted logical sectors inside the physical sector due to
732  * interrupted erase operation.
733  *
734  * \par<b>Related APIs:</b><BR>
735  * None
736  */
737 void XMC_FLASH_RepairPhysicalSector(void);
738 /**
739  *
740  * @param sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_SECTOR_x MACRO defined
741  *                             in xmc4_flash.h file.
742  *
743  * @return None
744  *
745  * \par<b>Description:</b><br>
746  * Erases the physical sector "PSA".\n\n If "PSA" does not point to base address of a correct sector or an unavailable
747  * sector, it returns SQER.
748  *
749  *
750  * \par<b>Related APIs:</b><BR>
751  * None
752  */
753 void XMC_FLASH_ErasePhysicalSector(uint32_t *sector_start_address);
754 
755 /**
756  *
757  * @param ucb_sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_UCBx MACRO
758  *                                 defined in xmc4_flash.h file.
759  *
760  * @return None
761  *
762  * \par<b>Description:</b><br>
763  * The addressed user configuration block ?UCB? is erased.\n\n
764  * Erases UCB whose startting address specified in the input parameter \a ucb_sector_start_address. When the UCB has
765  * an active write protection or the Flash module has an active global read protection the execution fails and
766  * PROER is set. The command fails with SQER when \a ucb_sector_start_address is not the start address of a valid UCB.
767  * Call \ref XMC_FLASH_GetStatus API after this API to verify the erase was proper ot not.
768  *
769  * \par<b>Related APIs:</b><BR>
770  * None
771  */
772 void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address);
773 
774 /**
775  *
776  * @param None
777  *
778  * @return None
779  *
780  * \par<b>Description:</b><br>
781  * Resets the command interpreter to its initial state.\n\n
782  * Reset to Read can cancel every command sequence before its last command cycle has been received. All error flags
783  * gets cleared by calling this API.
784  * \par<b>Note:</b><br>
785  * todo
786  *
787  * \par<b>Related APIs:</b><BR>
788  * None
789  */
790 void XMC_FLASH_Reset(void);
791 
792 
793 
794 #ifdef __cplusplus
795 }
796 #endif
797 
798 /**
799  * @}
800  */
801 
802 /**
803  * @}
804  */
805 
806 #endif
807 
808 #endif
809 
810