1 /***************************************************************************//** 2 * \file system_psoc6.h 3 * \version 2.95.1 4 * 5 * \brief Device system header file. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2016-2021 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 26 #ifndef _SYSTEM_PSOC6_H_ 27 #define _SYSTEM_PSOC6_H_ 28 29 /** 30 * \addtogroup group_system_config_cm4 31 * \{ 32 * Provides device startup, system configuration, and linker script files. 33 * The system startup provides the followings features: 34 * - See \ref group_system_config_device_initialization for the: 35 * * \ref group_system_config_dual_core_device_initialization 36 * * \ref group_system_config_single_core_device_initialization 37 * - \ref group_system_config_device_memory_definition 38 * - \ref group_system_config_heap_stack_config 39 * - \ref group_system_config_default_handlers 40 * - \ref group_system_config_device_vector_table 41 * - \ref group_system_config_cm4_functions 42 * 43 * \section group_system_config_configuration Configuration Considerations 44 * 45 * \subsection group_system_config_device_memory_definition Device Memory Definition 46 * The flash and RAM allocation for each CPU is defined by the linker scripts. 47 * For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. 48 * 2 KB of RAM (allocated at the end of RAM) are reserved for system use. 49 * For Single-Core devices the system reserves additional 80 bytes of RAM. 50 * Using the reserved memory area for other purposes will lead to unexpected behavior. 51 * 52 * \note The linker files provided with the PDL are generic and handle all common 53 * use cases. Your project may not use every section defined in the linker files. 54 * In that case you may see warnings during the build process. To eliminate build 55 * warnings in your project, you can simply comment out or remove the relevant 56 * code in the linker file. 57 * 58 * \note For the PSoC 64 Secure MCUs devices, refer to the following page: 59 * https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide 60 * 61 * 62 * <b>ARM GCC</b>\n 63 * The flash and RAM sections for the CPU are defined in the linker files: 64 * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, 65 * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. 66 * \note If the start of the Cortex-M4 application image is changed, the value 67 * of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The 68 * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the 69 * Cy_SysEnableCM4() function call. 70 * By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. 71 * More about CM0+ prebuilt images, see here: 72 * https://github.com/Infineon/psoc6cm0p 73 * 74 * Change the flash and RAM sizes by editing the macros value in the 75 * linker files for both CPUs: 76 * - 'xx_cm0plus.ld', where 'xx' is the device group: 77 * \code 78 * flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 79 * ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 80 * \endcode 81 * - 'xx_cm4_dual.ld', where 'xx' is the device group: 82 * \code 83 * flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 84 * ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 85 * \endcode 86 * 87 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's 88 * value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 89 * of the Cortex-M0+ application should be the same value as the flash LENGTH in 90 * 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 91 * Do this by either: 92 * - Passing the following commands to the compiler:\n 93 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode 94 * or 95 * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 96 * 'xx' is the device family:\n 97 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode 98 * 99 * <b>ARM Compiler</b>\n 100 * The flash and RAM sections for the CPU are defined in the linker files: 101 * 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 102 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. 103 * \note If the start of the Cortex-M4 application image is changed, the value 104 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The 105 * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref 106 * Cy_SysEnableCM4() function call. 107 * By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. 108 * More about CM0+ prebuilt images, see here: 109 * https://github.com/Infineon/psoc6cm0p 110 * 111 * \note The linker files provided with the PDL are generic and handle all common 112 * use cases. Your project may not use every section defined in the linker files. 113 * In that case you may see the warnings during the build process: 114 * L6314W (no section matches pattern) and/or L6329W 115 * (pattern only matches removed unused sections). In your project, you can 116 * suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to 117 * the linker. You can also comment out or remove the relevant code in the linker 118 * file. 119 * 120 * Change the flash and RAM sizes by editing the macros value in the 121 * linker files for both CPUs: 122 * - 'xx_cm0plus.sct', where 'xx' is the device group: 123 * \code 124 * #define FLASH_START 0x10000000 125 * #define FLASH_SIZE 0x00002000 126 * #define RAM_START 0x08000000 127 * #define RAM_SIZE 0x00002000 128 * \endcode 129 * - 'xx_cm4_dual.sct', where 'xx' is the device group: 130 * \code 131 * #define FLASH_START 0x10000000 132 * #define FLASH_SIZE 0x00100000 133 * #define RAM_START 0x08002000 134 * #define RAM_SIZE 0x00045800 135 * \endcode 136 * 137 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START 138 * value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 139 * of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 140 * 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 141 * Do this by either: 142 * - Passing the following commands to the compiler:\n 143 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode 144 * or 145 * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 146 * 'xx' is the device family:\n 147 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode 148 * 149 * <b>IAR</b>\n 150 * The flash and RAM sections for the CPU are defined in the linker files: 151 * 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, 152 * 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. 153 * \note If the start of the Cortex-M4 application image is changed, the value 154 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The 155 * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref 156 * Cy_SysEnableCM4() function call. 157 * By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. 158 * More about CM0+ prebuilt images, see here: 159 * https://github.com/Infineon/psoc6cm0p 160 * 161 * Change the flash and RAM sizes by editing the macros value in the 162 * linker files for both CPUs: 163 * - 'xx_cm0plus.icf', where 'xx' is the device group: 164 * \code 165 * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; 166 * define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; 167 * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; 168 * define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; 169 * \endcode 170 * - 'xx_cm4_dual.icf', where 'xx' is the device group: 171 * \code 172 * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; 173 * define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; 174 * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; 175 * define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; 176 * \endcode 177 * 178 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 179 * __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 180 * (0x2000, the size of a flash image of the Cortex-M0+ application) in the 181 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result 182 * should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 183 * 'xx_cm0plus.icf'. Do this by either: 184 * - Passing the following commands to the compiler:\n 185 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode 186 * or 187 * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 188 * 'xx' is the device family:\n 189 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode 190 * 191 * \subsection group_system_config_device_initialization Device Initialization 192 * After a power-on-reset (POR), the boot process is handled by the boot code 193 * from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot 194 * code passes the control to the Cortex-M0+ startup code located in flash. 195 * 196 * \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices 197 * The Cortex-M0+ startup code performs the device initialization by a call to 198 * SystemInit() and then calls the main() function. The Cortex-M4 core is disabled 199 * by default. Enable the core using the \ref Cy_SysEnableCM4() function. 200 * See \ref group_system_config_cm4_functions for more details. 201 * \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. 202 * The function has a separate implementation on each core. 203 * Both function implementations unlock and disable the WDT. 204 * Therefore enable the WDT after both cores have been initialized. 205 * 206 * \subsubsection group_system_config_single_core_device_initialization Single-Core Devices 207 * The Cortex-M0+ core is not user-accessible on these devices. In this case the 208 * Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. 209 * 210 * \subsection group_system_config_heap_stack_config Heap and Stack Configuration 211 * There are two ways to adjust heap and stack configurations: 212 * -# Editing source code files 213 * -# Specifying via command line 214 * 215 * By default, the stack size is set to 0x00001000 and the heap size is allocated 216 * dynamically to the whole available free memory up to stack memory and it 217 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. 218 * 219 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC 220 * - <b>Editing source code files</b>\n 221 * The heap and stack sizes are defined in the assembler startup files 222 * (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). 223 * Change the heap and stack sizes by modifying the following lines:\n 224 * \code .equ Stack_Size, 0x00001000 \endcode 225 * \code .equ Heap_Size, 0x00000400 \endcode 226 * Also, the stack size is defined in the linker script files: 'xx_yy.ld', 227 * where 'xx' is the device family, and 'yy' is the target CPU; for example, 228 * cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. 229 * Change the stack size by modifying the following line:\n 230 * \code STACK_SIZE = 0x1000; \endcode 231 * 232 * \note Correct operation of malloc and related functions depends on the working 233 * implementation of the 'sbrk' function. Newlib-nano (default C runtime library 234 * used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that 235 * doesn't check for heap and stack collisions during excessive memory allocations. 236 * To ensure the heap always remains within the range defined by __HeapBase and 237 * __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: 238 * \snippet startup/snippet/main.c snippet_sbrk 239 * For FreeRTOS-enabled multi-threaded applications, it is sufficient to include 240 * clib-support library that provides newlib-compatible implementations of 241 * 'sbrk', '__malloc_lock' and '__malloc_unlock': 242 * <br> 243 * https://github.com/Infineon/clib-support. 244 * 245 * \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler 246 * - <b>Editing source code files</b>\n 247 * The stack size is defined in the linker script files: 'xx_yy.sct', 248 * where 'xx' is the device family, and 'yy' is the target CPU; for example, 249 * cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. 250 * Change the stack size by modifying the following line:\n 251 * \code STACK_SIZE = 0x1000; \endcode 252 * 253 * \subsubsection group_system_config_heap_stack_config_iar IAR 254 * - <b>Editing source code files</b>\n 255 * The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', 256 * where 'xx' is the device family, and 'yy' is the target CPU; for example, 257 * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. 258 * Change the heap and stack sizes by modifying the following lines:\n 259 * \code Stack_Size EQU 0x00001000 \endcode 260 * \code Heap_Size EQU 0x00000400 \endcode 261 * 262 * - <b>Specifying via command line</b>\n 263 * Change the heap and stack sizes passing the following commands to the 264 * linker (including quotation marks):\n 265 * \code --define_symbol __STACK_SIZE=0x000000400 \endcode 266 * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode 267 * 268 * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition 269 * The default interrupt handler functions are defined as weak functions to a dummy 270 * handler in the startup file. The naming convention for the interrupt handler names 271 * is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in 272 * user code by defining the handler function using the same name. For example: 273 * \code 274 * void scb_0_interrupt_IRQHandler(void) 275 *{ 276 * ... 277 *} 278 * \endcode 279 * 280 * \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM 281 * This process uses memory sections defined in the linker script. The startup 282 * code actually defines the contents of the vector table and performs the copy. 283 * \subsubsection group_system_config_device_vector_table_gcc ARM GCC 284 * The linker script file is 'xx_yy.ld', where 'xx' is the device family, and 285 * 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. 286 * It defines sections and locations in memory.\n 287 * Copy interrupt vectors from flash to RAM: \n 288 * From: \code LONG (__Vectors) \endcode 289 * To: \code LONG (__ram_vectors_start__) \endcode 290 * Size: \code LONG (__Vectors_End - __Vectors) \endcode 291 * The vector table address (and the vector table itself) are defined in the 292 * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). 293 * The code in these files copies the vector table from Flash to RAM. 294 * \subsubsection group_system_config_device_vector_table_mdk ARM Compiler 295 * The linker script file is 'xx_yy.sct', where 'xx' is the device family, 296 * and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and 297 * cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table 298 * (RESET_RAM) shall be first in the RAM section.\n 299 * RESET_RAM represents the vector table. It is defined in the assembler startup 300 * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). 301 * The code in these files copies the vector table from Flash to RAM. 302 * 303 * \subsubsection group_system_config_device_vector_table_iar IAR 304 * The linker script file is 'xx_yy.icf', where 'xx' is the device family, and 305 * 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. 306 * This file defines the .intvec_ram section and its location. 307 * \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode 308 * The vector table address (and the vector table itself) are defined in the 309 * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). 310 * The code in these files copies the vector table from Flash to RAM. 311 * 312 * \section group_system_config_MISRA MISRA Compliance 313 * 314 * <table class="doxtable"> 315 * <tr> 316 * <th>MISRA Rule</th> 317 * <th>Rule Class (Required/Advisory)</th> 318 * <th>Rule Description</th> 319 * <th>Description of Deviation(s)</th> 320 * </tr> 321 * <tr> 322 * <td>2.3</td> 323 * <td>R</td> 324 * <td>The character sequence // shall not be used within a comment.</td> 325 * <td>The comments provide a useful WEB link to the documentation.</td> 326 * </tr> 327 * </table> 328 * 329 * \section group_system_config_changelog Changelog 330 * <table class="doxtable"> 331 * <tr> 332 * <th>Version</th> 333 * <th>Changes</th> 334 * <th>Reason for Change</th> 335 * </tr> 336 * <tr> 337 * <td rowspan="1">2.95.1</td> 338 * <td>Restructured documentation.</td> 339 * <td>Documentation update.</td> 340 * </tr> 341 * <tr> 342 * <td rowspan="1">2.95</td> 343 * <td>Update FPU enable function with CMSIS macros to disable/enable interrupts</td> 344 * <td>Move to stadnard inline CMSIS ARM macros</td> 345 * </tr> 346 * <tr> 347 * <td rowspan="2">2.91</td> 348 * <td>Updated memory configuration for PSoC 64 devices.</td> 349 * <td>Flash and RAM memory allocation updated.</td> 350 * </tr> 351 * <tr> 352 * <td>Added cys06xxa_cm4 linker scripts.</td> 353 * <td>New device support.</td> 354 * </tr> 355 * <tr> 356 * <td rowspan="4">2.90.1</td> 357 * <td>Updated \ref group_system_config_heap_stack_config_gcc section with the note 358 * on the dynamic memory allocation for ARM GCC.</td> 359 * <td>Documentation update.</td> 360 * </tr> 361 * <tr> 362 * <td>Updated system_psoc6.h to include custom CY_SYSTEM_PSOC6_CONFIG passed as compiler macro.</td> 363 * <td>Improve configuration flexibility.</td> 364 * </tr> 365 * <tr> 366 * <td>Updated attribute usage for the linker section placement in CM0+ startup code</td> 367 * <td>Enhancement based on usability feedback.</td> 368 * </tr> 369 * <tr> 370 * <td>Renamed the '.cy_xip' linker script region as 'cy_xip'</td> 371 * <td>Enable access to the XIP region start/end addresses from the C code.</td> 372 * </tr> 373 * <tr> 374 * <td>2.90</td> 375 * <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td> 376 * <td>Flash allocation adjustment.</td> 377 * </tr> 378 * <tr> 379 * <td rowspan="2">2.80</td> 380 * <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td> 381 * <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates 382 * in accordance with the PSoC 64 Secure Boot SDK policies.</td> 383 * </tr> 384 * <tr> 385 * <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td> 386 * <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td> 387 * </tr> 388 * <tr> 389 * <td>2.70.1</td> 390 * <td>Updated documentation for the better description of the existing startup implementation.</td> 391 * <td>User experience enhancement.</td> 392 * </tr> 393 * <tr> 394 * <td rowspan="5">2.70</td> 395 * <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td> 396 * <td>Code optimization.</td> 397 * </tr> 398 * <tr> 399 * <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td> 400 * <td>Provided support for SysPM driver updates.</td> 401 * </tr> 402 * <tr> 403 * <td>Updated the linker scripts.</td> 404 * <td>Reserved FLASH area for the MCU boot headers.</td> 405 * </tr> 406 * <tr> 407 * <td>Added System Pipe initialization for all devices. </td> 408 * <td>Improved PDL usability according to user experience.</td> 409 * </tr> 410 * <tr> 411 * <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. 412 * Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td> 413 * <td>Defect fixing.</td> 414 * </tr> 415 * <tr> 416 * <td>2.60</td> 417 * <td>Updated linker scripts.</td> 418 * <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td> 419 * </tr> 420 * <tr> 421 * <td>2.50</td> 422 * <td>Updated assembler files, C files, linker scripts.</td> 423 * <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td> 424 * </tr> 425 * <tr> 426 * <td>2.40</td> 427 * <td>Updated assembler files, C files, linker scripts.</td> 428 * <td>Added Arm Compiler 6 support.</td> 429 * </tr> 430 * <tr> 431 * <td rowspan="2">2.30</td> 432 * <td>Added assembler files, linker scripts for Mbed OS.</td> 433 * <td>Added Arm Mbed OS embedded operating system support.</td> 434 * </tr> 435 * <tr> 436 * <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td> 437 * <td>Enhanced PDL usability.</td> 438 * </tr> 439 * <tr> 440 * <td>2.20</td> 441 * <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td> 442 * <td>Changed the IPC driver configuration method from compile time to run time.</td> 443 * </tr> 444 * <tr> 445 * <td rowspan="2"> 2.10</td> 446 * <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n 447 * Removed $Sub$$main symbol for ARM MDK compiler. 448 * </td> 449 * <td>uVision Debugger support.</td> 450 * </tr> 451 * <tr> 452 * <td>Updated description of the Startup behavior for Single-Core Devices. \n 453 * Added note about WDT disabling by SystemInit() function. 454 * </td> 455 * <td>Documentation improvement.</td> 456 * </tr> 457 * <tr> 458 * <td rowspan="4"> 2.0</td> 459 * <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices. 460 * Single core device support. 461 * </td> 462 * <td></td> 463 * </tr> 464 * <tr> 465 * <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n 466 * Renamed 'wflash' memory region to 'em_eeprom'. 467 * </td> 468 * <td>Linker scripts usability improvement.</td> 469 * </tr> 470 * <tr> 471 * <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td> 472 * <td>Reserved system resources for internal operations.</td> 473 * </tr> 474 * <tr> 475 * <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td> 476 * <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td> 477 * </tr> 478 * <tr> 479 * <td>1.0</td> 480 * <td>Initial version</td> 481 * <td></td> 482 * </tr> 483 * </table> 484 * 485 * 486 * \defgroup group_system_config_macro Macros 487 * \{ 488 * \defgroup group_system_config_system_macro System Macros 489 * \defgroup group_system_config_cm4_status_macro Cortex-M4 Status Macros 490 * \defgroup group_system_config_user_settings_macro User Settings Macros 491 * \} 492 * \defgroup group_system_config_functions Functions 493 * \{ 494 * \defgroup group_system_config_cm4_functions Cortex-M4 Control Functions 495 * \} 496 * \defgroup group_system_config_globals Global Variables 497 * 498 * \} 499 */ 500 501 #ifdef __cplusplus 502 extern "C" { 503 #endif 504 505 506 /******************************************************************************* 507 * Include files 508 *******************************************************************************/ 509 #include <stdint.h> 510 511 512 /******************************************************************************* 513 * Global preprocessor symbols/macros ('define') 514 *******************************************************************************/ 515 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 516 (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 517 (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) 518 #define CY_SYSTEM_CPU_CM0P 1UL 519 #else 520 #define CY_SYSTEM_CPU_CM0P 0UL 521 #endif 522 523 524 /******************************************************************************* 525 * 526 * START OF USER SETTINGS HERE 527 * =========================== 528 * 529 * All lines with '<<<' can be set by user. 530 * 531 *******************************************************************************/ 532 533 /** 534 * \addtogroup group_system_config_user_settings_macro 535 * \{ 536 */ 537 538 /* 539 * Include optional application-specific configuration header. 540 * 541 * For example, custom system_psoc6_config.h can be included here 542 * by adding the below macro definition to the build system: 543 * DEFINES+=CY_SYSTEM_PSOC6_CONFIG='"system_psoc6_config.h"' 544 */ 545 #if defined(CY_SYSTEM_PSOC6_CONFIG) 546 #include CY_SYSTEM_PSOC6_CONFIG 547 #endif 548 549 550 /***************************************************************************//** 551 * \brief Start address of the Cortex-M4 application ([address]UL) 552 * <i>(USER SETTING)</i> 553 *******************************************************************************/ 554 #if !defined (CY_CORTEX_M4_APPL_ADDR) 555 #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ 556 #endif /* (CY_CORTEX_M4_APPL_ADDR) */ 557 558 559 /***************************************************************************//** 560 * \brief IPC Semaphores allocation ([value]UL). 561 * <i>(USER SETTING)</i> 562 *******************************************************************************/ 563 #define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ 564 565 566 /***************************************************************************//** 567 * \brief IPC Pipe definitions ([value]UL). 568 * <i>(USER SETTING)</i> 569 *******************************************************************************/ 570 #define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ 571 572 573 /******************************************************************************* 574 * 575 * END OF USER SETTINGS HERE 576 * ========================= 577 * 578 *******************************************************************************/ 579 580 /** \} group_system_config_user_settings_macro */ 581 582 583 /** 584 * \addtogroup group_system_config_system_macro 585 * \{ 586 */ 587 588 #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) 589 /** The Cortex-M0+ startup driver identifier */ 590 #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) 591 #endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ 592 593 #if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) 594 /** The Cortex-M4 startup driver identifier */ 595 #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) 596 #endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ 597 598 /** \} group_system_config_system_macro */ 599 600 601 /** \cond */ 602 #if defined(__ARMCC_VERSION) 603 extern void SystemInit(void) __attribute__((constructor)); 604 #else 605 extern void SystemInit(void); 606 #endif /* (__ARMCC_VERSION) */ 607 608 extern void SystemCoreClockUpdate(void); 609 /** \endcond */ 610 611 612 /** 613 * \addtogroup group_system_config_cm4_functions 614 * \{ 615 */ 616 extern uint32_t Cy_SysGetCM4Status(void); 617 extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); 618 extern void Cy_SysDisableCM4(void); 619 extern void Cy_SysRetainCM4(void); 620 extern void Cy_SysResetCM4(void); 621 /** \} group_system_config_cm4_functions */ 622 623 624 /** \cond */ 625 extern void Default_Handler (void); 626 627 void Cy_SysIpcPipeIsrCm0(void); 628 void Cy_SysIpcPipeIsrCm4(void); 629 630 extern void Cy_SystemInit(void); 631 extern void Cy_SystemInitFpuEnable(void); 632 633 extern uint32_t cy_delayFreqKhz; 634 extern uint8_t cy_delayFreqMhz; 635 /** \endcond */ 636 637 638 #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) 639 /** 640 * \addtogroup group_system_config_cm4_status_macro 641 * \{ 642 */ 643 #define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ 644 #define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ 645 #define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ 646 #define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ 647 /** \} group_system_config_cm4_status_macro */ 648 649 #endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ 650 651 652 /******************************************************************************* 653 * IPC Configuration 654 * ========================= 655 *******************************************************************************/ 656 /* IPC CY_PIPE default configuration */ 657 #define CY_SYS_CYPIPE_CLIENT_CNT (8UL) 658 659 #define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ 660 #define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ 661 #define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ 662 663 #define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) 664 #define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) 665 666 667 /******************************************************************************/ 668 /* 669 * The System pipe configuration defines the IPC channel number, interrupt 670 * number, and the pipe interrupt mask for the endpoint. 671 * 672 * The format of the endPoint configuration 673 * Bits[31:16] Interrupt Mask 674 * Bits[15:8 ] IPC interrupt 675 * Bits[ 7:0 ] IPC channel 676 */ 677 678 /* System Pipe addresses */ 679 /* CyPipe defines */ 680 681 #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) 682 683 #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ 684 | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ 685 | CY_IPC_CHAN_CYPIPE_EP0) 686 #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ 687 | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ 688 | CY_IPC_CHAN_CYPIPE_EP1) 689 690 /******************************************************************************/ 691 692 693 694 /** \addtogroup group_system_config_globals 695 * \{ 696 */ 697 extern uint32_t cy_BleEcoClockFreqHz; 698 /** \} group_system_config_globals */ 699 700 /** \cond INTERNAL */ 701 extern uint32_t cy_Hfclk0FreqHz; 702 extern uint32_t cy_PeriClkFreqHz; 703 extern uint32_t SystemCoreClock; 704 extern uint32_t cy_AhbFreqHz; 705 706 707 708 709 /******************************************************************************* 710 * Backward compatibility macros. The following code is DEPRECATED and must 711 * not be used in new projects 712 *******************************************************************************/ 713 714 /* BWC defines for functions related to enter/exit critical section */ 715 #define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection 716 #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection 717 #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) 718 #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) 719 #define cy_delayFreqHz (SystemCoreClock) 720 721 /** \endcond */ 722 723 #ifdef __cplusplus 724 } 725 #endif 726 727 #endif /* _SYSTEM_PSOC6_H_ */ 728 729 730 /* [] END OF FILE */ 731
