1 /***************************************************************************//** 2 * \file gpio_xmc7200_176_teqfp.h 3 * 4 * \brief 5 * XMC7200 device GPIO header for 176-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_XMC7200_176_TEQFP_H_ 28 #define _GPIO_XMC7200_176_TEQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TEQFP 44 #define CY_GPIO_PIN_COUNT 176u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_EFUSE, 50 AMUXBUS_MAIN, 51 AMUXBUS_REGHC_ISENSE, 52 AMUXBUS_TEST, 53 AMUXBUS_TESTECT, 54 AMUXBUS_TESTSRSS, 55 }; 56 57 /* AMUX Splitter Controls */ 58 typedef enum 59 { 60 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 61 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 62 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_EFUSE */ 63 AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_REGHC_ISENSE */ 64 } cy_en_amux_split_t; 65 66 /* Port List */ 67 /* PORT 0 (AUTOLVL) */ 68 #define P0_0_PORT GPIO_PRT0 69 #define P0_0_PIN 0u 70 #define P0_0_NUM 0u 71 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 72 #define P0_1_PORT GPIO_PRT0 73 #define P0_1_PIN 1u 74 #define P0_1_NUM 1u 75 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 76 #define P0_2_PORT GPIO_PRT0 77 #define P0_2_PIN 2u 78 #define P0_2_NUM 2u 79 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 80 #define P0_3_PORT GPIO_PRT0 81 #define P0_3_PIN 3u 82 #define P0_3_NUM 3u 83 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 84 85 /* PORT 1 (AUTOLVL) */ 86 #define P1_0_PORT GPIO_PRT1 87 #define P1_0_PIN 0u 88 #define P1_0_NUM 0u 89 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 90 #define P1_1_PORT GPIO_PRT1 91 #define P1_1_PIN 1u 92 #define P1_1_NUM 1u 93 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 94 #define P1_2_PORT GPIO_PRT1 95 #define P1_2_PIN 2u 96 #define P1_2_NUM 2u 97 #define P1_2_AMUXSEGMENT AMUXBUS_MAIN 98 #define P1_3_PORT GPIO_PRT1 99 #define P1_3_PIN 3u 100 #define P1_3_NUM 3u 101 #define P1_3_AMUXSEGMENT AMUXBUS_MAIN 102 103 /* PORT 2 (AUTOLVL) */ 104 #define P2_0_PORT GPIO_PRT2 105 #define P2_0_PIN 0u 106 #define P2_0_NUM 0u 107 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 108 #define P2_1_PORT GPIO_PRT2 109 #define P2_1_PIN 1u 110 #define P2_1_NUM 1u 111 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 112 #define P2_2_PORT GPIO_PRT2 113 #define P2_2_PIN 2u 114 #define P2_2_NUM 2u 115 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 116 #define P2_3_PORT GPIO_PRT2 117 #define P2_3_PIN 3u 118 #define P2_3_NUM 3u 119 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 120 #define P2_4_PORT GPIO_PRT2 121 #define P2_4_PIN 4u 122 #define P2_4_NUM 4u 123 #define P2_4_AMUXSEGMENT AMUXBUS_MAIN 124 #define P2_5_PORT GPIO_PRT2 125 #define P2_5_PIN 5u 126 #define P2_5_NUM 5u 127 #define P2_5_AMUXSEGMENT AMUXBUS_MAIN 128 129 /* PORT 3 (AUTOLVL) */ 130 #define P3_0_PORT GPIO_PRT3 131 #define P3_0_PIN 0u 132 #define P3_0_NUM 0u 133 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 134 #define P3_1_PORT GPIO_PRT3 135 #define P3_1_PIN 1u 136 #define P3_1_NUM 1u 137 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 138 #define P3_2_PORT GPIO_PRT3 139 #define P3_2_PIN 2u 140 #define P3_2_NUM 2u 141 #define P3_2_AMUXSEGMENT AMUXBUS_MAIN 142 #define P3_3_PORT GPIO_PRT3 143 #define P3_3_PIN 3u 144 #define P3_3_NUM 3u 145 #define P3_3_AMUXSEGMENT AMUXBUS_MAIN 146 #define P3_4_PORT GPIO_PRT3 147 #define P3_4_PIN 4u 148 #define P3_4_NUM 4u 149 #define P3_4_AMUXSEGMENT AMUXBUS_MAIN 150 #define P3_5_PORT GPIO_PRT3 151 #define P3_5_PIN 5u 152 #define P3_5_NUM 5u 153 #define P3_5_AMUXSEGMENT AMUXBUS_MAIN 154 155 /* PORT 4 (AUTOLVL) */ 156 #define P4_0_PORT GPIO_PRT4 157 #define P4_0_PIN 0u 158 #define P4_0_NUM 0u 159 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 160 #define P4_1_PORT GPIO_PRT4 161 #define P4_1_PIN 1u 162 #define P4_1_NUM 1u 163 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 164 #define P4_2_PORT GPIO_PRT4 165 #define P4_2_PIN 2u 166 #define P4_2_NUM 2u 167 #define P4_2_AMUXSEGMENT AMUXBUS_MAIN 168 #define P4_3_PORT GPIO_PRT4 169 #define P4_3_PIN 3u 170 #define P4_3_NUM 3u 171 #define P4_3_AMUXSEGMENT AMUXBUS_MAIN 172 #define P4_4_PORT GPIO_PRT4 173 #define P4_4_PIN 4u 174 #define P4_4_NUM 4u 175 #define P4_4_AMUXSEGMENT AMUXBUS_MAIN 176 177 /* PORT 5 (AUTOLVL) */ 178 #define P5_0_PORT GPIO_PRT5 179 #define P5_0_PIN 0u 180 #define P5_0_NUM 0u 181 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 182 #define P5_1_PORT GPIO_PRT5 183 #define P5_1_PIN 1u 184 #define P5_1_NUM 1u 185 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 186 #define P5_2_PORT GPIO_PRT5 187 #define P5_2_PIN 2u 188 #define P5_2_NUM 2u 189 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 190 #define P5_3_PORT GPIO_PRT5 191 #define P5_3_PIN 3u 192 #define P5_3_NUM 3u 193 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 194 #define P5_4_PORT GPIO_PRT5 195 #define P5_4_PIN 4u 196 #define P5_4_NUM 4u 197 #define P5_4_AMUXSEGMENT AMUXBUS_MAIN 198 #define P5_5_PORT GPIO_PRT5 199 #define P5_5_PIN 5u 200 #define P5_5_NUM 5u 201 #define P5_5_AMUXSEGMENT AMUXBUS_MAIN 202 203 /* PORT 6 (AUTOLVL) */ 204 #define P6_0_PORT GPIO_PRT6 205 #define P6_0_PIN 0u 206 #define P6_0_NUM 0u 207 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 208 #define P6_1_PORT GPIO_PRT6 209 #define P6_1_PIN 1u 210 #define P6_1_NUM 1u 211 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 212 #define P6_2_PORT GPIO_PRT6 213 #define P6_2_PIN 2u 214 #define P6_2_NUM 2u 215 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 216 #define P6_3_PORT GPIO_PRT6 217 #define P6_3_PIN 3u 218 #define P6_3_NUM 3u 219 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 220 #define P6_4_PORT GPIO_PRT6 221 #define P6_4_PIN 4u 222 #define P6_4_NUM 4u 223 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 224 #define P6_5_PORT GPIO_PRT6 225 #define P6_5_PIN 5u 226 #define P6_5_NUM 5u 227 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 228 #define P6_6_PORT GPIO_PRT6 229 #define P6_6_PIN 6u 230 #define P6_6_NUM 6u 231 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 232 #define P6_7_PORT GPIO_PRT6 233 #define P6_7_PIN 7u 234 #define P6_7_NUM 7u 235 #define P6_7_AMUXSEGMENT AMUXBUS_MAIN 236 237 /* PORT 7 (AUTOLVL) */ 238 #define P7_0_PORT GPIO_PRT7 239 #define P7_0_PIN 0u 240 #define P7_0_NUM 0u 241 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 242 #define P7_1_PORT GPIO_PRT7 243 #define P7_1_PIN 1u 244 #define P7_1_NUM 1u 245 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 246 #define P7_2_PORT GPIO_PRT7 247 #define P7_2_PIN 2u 248 #define P7_2_NUM 2u 249 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 250 #define P7_3_PORT GPIO_PRT7 251 #define P7_3_PIN 3u 252 #define P7_3_NUM 3u 253 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 254 #define P7_4_PORT GPIO_PRT7 255 #define P7_4_PIN 4u 256 #define P7_4_NUM 4u 257 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 258 #define P7_5_PORT GPIO_PRT7 259 #define P7_5_PIN 5u 260 #define P7_5_NUM 5u 261 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 262 #define P7_6_PORT GPIO_PRT7 263 #define P7_6_PIN 6u 264 #define P7_6_NUM 6u 265 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 266 #define P7_7_PORT GPIO_PRT7 267 #define P7_7_PIN 7u 268 #define P7_7_NUM 7u 269 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 270 271 /* PORT 8 (AUTOLVL) */ 272 #define P8_0_PORT GPIO_PRT8 273 #define P8_0_PIN 0u 274 #define P8_0_NUM 0u 275 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 276 #define P8_1_PORT GPIO_PRT8 277 #define P8_1_PIN 1u 278 #define P8_1_NUM 1u 279 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 280 #define P8_2_PORT GPIO_PRT8 281 #define P8_2_PIN 2u 282 #define P8_2_NUM 2u 283 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 284 #define P8_3_PORT GPIO_PRT8 285 #define P8_3_PIN 3u 286 #define P8_3_NUM 3u 287 #define P8_3_AMUXSEGMENT AMUXBUS_MAIN 288 #define P8_4_PORT GPIO_PRT8 289 #define P8_4_PIN 4u 290 #define P8_4_NUM 4u 291 #define P8_4_AMUXSEGMENT AMUXBUS_MAIN 292 293 /* PORT 9 (AUTOLVL) */ 294 #define P9_0_PORT GPIO_PRT9 295 #define P9_0_PIN 0u 296 #define P9_0_NUM 0u 297 #define P9_0_AMUXSEGMENT AMUXBUS_MAIN 298 #define P9_1_PORT GPIO_PRT9 299 #define P9_1_PIN 1u 300 #define P9_1_NUM 1u 301 #define P9_1_AMUXSEGMENT AMUXBUS_MAIN 302 #define P9_2_PORT GPIO_PRT9 303 #define P9_2_PIN 2u 304 #define P9_2_NUM 2u 305 #define P9_2_AMUXSEGMENT AMUXBUS_MAIN 306 #define P9_3_PORT GPIO_PRT9 307 #define P9_3_PIN 3u 308 #define P9_3_NUM 3u 309 #define P9_3_AMUXSEGMENT AMUXBUS_MAIN 310 311 /* PORT 10 (AUTOLVL) */ 312 #define P10_0_PORT GPIO_PRT10 313 #define P10_0_PIN 0u 314 #define P10_0_NUM 0u 315 #define P10_0_AMUXSEGMENT AMUXBUS_MAIN 316 #define P10_1_PORT GPIO_PRT10 317 #define P10_1_PIN 1u 318 #define P10_1_NUM 1u 319 #define P10_1_AMUXSEGMENT AMUXBUS_MAIN 320 #define P10_2_PORT GPIO_PRT10 321 #define P10_2_PIN 2u 322 #define P10_2_NUM 2u 323 #define P10_2_AMUXSEGMENT AMUXBUS_MAIN 324 #define P10_3_PORT GPIO_PRT10 325 #define P10_3_PIN 3u 326 #define P10_3_NUM 3u 327 #define P10_3_AMUXSEGMENT AMUXBUS_MAIN 328 #define P10_4_PORT GPIO_PRT10 329 #define P10_4_PIN 4u 330 #define P10_4_NUM 4u 331 #define P10_4_AMUXSEGMENT AMUXBUS_MAIN 332 #define P10_5_PORT GPIO_PRT10 333 #define P10_5_PIN 5u 334 #define P10_5_NUM 5u 335 #define P10_5_AMUXSEGMENT AMUXBUS_MAIN 336 #define P10_6_PORT GPIO_PRT10 337 #define P10_6_PIN 6u 338 #define P10_6_NUM 6u 339 #define P10_6_AMUXSEGMENT AMUXBUS_MAIN 340 #define P10_7_PORT GPIO_PRT10 341 #define P10_7_PIN 7u 342 #define P10_7_NUM 7u 343 #define P10_7_AMUXSEGMENT AMUXBUS_MAIN 344 345 /* PORT 11 (AUTOLVL) */ 346 #define P11_0_PORT GPIO_PRT11 347 #define P11_0_PIN 0u 348 #define P11_0_NUM 0u 349 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 350 #define P11_1_PORT GPIO_PRT11 351 #define P11_1_PIN 1u 352 #define P11_1_NUM 1u 353 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 354 #define P11_2_PORT GPIO_PRT11 355 #define P11_2_PIN 2u 356 #define P11_2_NUM 2u 357 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 358 359 /* PORT 12 (AUTOLVL) */ 360 #define P12_0_PORT GPIO_PRT12 361 #define P12_0_PIN 0u 362 #define P12_0_NUM 0u 363 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 364 #define P12_1_PORT GPIO_PRT12 365 #define P12_1_PIN 1u 366 #define P12_1_NUM 1u 367 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 368 #define P12_2_PORT GPIO_PRT12 369 #define P12_2_PIN 2u 370 #define P12_2_NUM 2u 371 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 372 #define P12_3_PORT GPIO_PRT12 373 #define P12_3_PIN 3u 374 #define P12_3_NUM 3u 375 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 376 #define P12_4_PORT GPIO_PRT12 377 #define P12_4_PIN 4u 378 #define P12_4_NUM 4u 379 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 380 #define P12_5_PORT GPIO_PRT12 381 #define P12_5_PIN 5u 382 #define P12_5_NUM 5u 383 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 384 #define P12_6_PORT GPIO_PRT12 385 #define P12_6_PIN 6u 386 #define P12_6_NUM 6u 387 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 388 #define P12_7_PORT GPIO_PRT12 389 #define P12_7_PIN 7u 390 #define P12_7_NUM 7u 391 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 392 393 /* PORT 13 (AUTOLVL) */ 394 #define P13_0_PORT GPIO_PRT13 395 #define P13_0_PIN 0u 396 #define P13_0_NUM 0u 397 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 398 #define P13_1_PORT GPIO_PRT13 399 #define P13_1_PIN 1u 400 #define P13_1_NUM 1u 401 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 402 #define P13_2_PORT GPIO_PRT13 403 #define P13_2_PIN 2u 404 #define P13_2_NUM 2u 405 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 406 #define P13_3_PORT GPIO_PRT13 407 #define P13_3_PIN 3u 408 #define P13_3_NUM 3u 409 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 410 #define P13_4_PORT GPIO_PRT13 411 #define P13_4_PIN 4u 412 #define P13_4_NUM 4u 413 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 414 #define P13_5_PORT GPIO_PRT13 415 #define P13_5_PIN 5u 416 #define P13_5_NUM 5u 417 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 418 #define P13_6_PORT GPIO_PRT13 419 #define P13_6_PIN 6u 420 #define P13_6_NUM 6u 421 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 422 #define P13_7_PORT GPIO_PRT13 423 #define P13_7_PIN 7u 424 #define P13_7_NUM 7u 425 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 426 427 /* PORT 14 (AUTOLVL) */ 428 #define P14_0_PORT GPIO_PRT14 429 #define P14_0_PIN 0u 430 #define P14_0_NUM 0u 431 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 432 #define P14_1_PORT GPIO_PRT14 433 #define P14_1_PIN 1u 434 #define P14_1_NUM 1u 435 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 436 #define P14_2_PORT GPIO_PRT14 437 #define P14_2_PIN 2u 438 #define P14_2_NUM 2u 439 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 440 #define P14_3_PORT GPIO_PRT14 441 #define P14_3_PIN 3u 442 #define P14_3_NUM 3u 443 #define P14_3_AMUXSEGMENT AMUXBUS_MAIN 444 #define P14_4_PORT GPIO_PRT14 445 #define P14_4_PIN 4u 446 #define P14_4_NUM 4u 447 #define P14_4_AMUXSEGMENT AMUXBUS_MAIN 448 #define P14_5_PORT GPIO_PRT14 449 #define P14_5_PIN 5u 450 #define P14_5_NUM 5u 451 #define P14_5_AMUXSEGMENT AMUXBUS_MAIN 452 #define P14_6_PORT GPIO_PRT14 453 #define P14_6_PIN 6u 454 #define P14_6_NUM 6u 455 #define P14_6_AMUXSEGMENT AMUXBUS_MAIN 456 #define P14_7_PORT GPIO_PRT14 457 #define P14_7_PIN 7u 458 #define P14_7_NUM 7u 459 #define P14_7_AMUXSEGMENT AMUXBUS_MAIN 460 461 /* PORT 15 (AUTOLVL) */ 462 #define P15_0_PORT GPIO_PRT15 463 #define P15_0_PIN 0u 464 #define P15_0_NUM 0u 465 #define P15_0_AMUXSEGMENT AMUXBUS_MAIN 466 #define P15_1_PORT GPIO_PRT15 467 #define P15_1_PIN 1u 468 #define P15_1_NUM 1u 469 #define P15_1_AMUXSEGMENT AMUXBUS_MAIN 470 #define P15_2_PORT GPIO_PRT15 471 #define P15_2_PIN 2u 472 #define P15_2_NUM 2u 473 #define P15_2_AMUXSEGMENT AMUXBUS_MAIN 474 #define P15_3_PORT GPIO_PRT15 475 #define P15_3_PIN 3u 476 #define P15_3_NUM 3u 477 #define P15_3_AMUXSEGMENT AMUXBUS_MAIN 478 479 /* PORT 16 (AUTOLVL) */ 480 #define P16_3_PORT GPIO_PRT16 481 #define P16_3_PIN 3u 482 #define P16_3_NUM 3u 483 #define P16_3_AMUXSEGMENT AMUXBUS_MAIN 484 485 /* PORT 17 (AUTOLVL) */ 486 #define P17_0_PORT GPIO_PRT17 487 #define P17_0_PIN 0u 488 #define P17_0_NUM 0u 489 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 490 #define P17_1_PORT GPIO_PRT17 491 #define P17_1_PIN 1u 492 #define P17_1_NUM 1u 493 #define P17_1_AMUXSEGMENT AMUXBUS_MAIN 494 #define P17_2_PORT GPIO_PRT17 495 #define P17_2_PIN 2u 496 #define P17_2_NUM 2u 497 #define P17_2_AMUXSEGMENT AMUXBUS_MAIN 498 #define P17_3_PORT GPIO_PRT17 499 #define P17_3_PIN 3u 500 #define P17_3_NUM 3u 501 #define P17_3_AMUXSEGMENT AMUXBUS_MAIN 502 #define P17_4_PORT GPIO_PRT17 503 #define P17_4_PIN 4u 504 #define P17_4_NUM 4u 505 #define P17_4_AMUXSEGMENT AMUXBUS_MAIN 506 #define P17_5_PORT GPIO_PRT17 507 #define P17_5_PIN 5u 508 #define P17_5_NUM 5u 509 #define P17_5_AMUXSEGMENT AMUXBUS_MAIN 510 #define P17_6_PORT GPIO_PRT17 511 #define P17_6_PIN 6u 512 #define P17_6_NUM 6u 513 #define P17_6_AMUXSEGMENT AMUXBUS_MAIN 514 #define P17_7_PORT GPIO_PRT17 515 #define P17_7_PIN 7u 516 #define P17_7_NUM 7u 517 #define P17_7_AMUXSEGMENT AMUXBUS_MAIN 518 519 /* PORT 18 (AUTOLVL) */ 520 #define P18_0_PORT GPIO_PRT18 521 #define P18_0_PIN 0u 522 #define P18_0_NUM 0u 523 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 524 #define P18_1_PORT GPIO_PRT18 525 #define P18_1_PIN 1u 526 #define P18_1_NUM 1u 527 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 528 #define P18_2_PORT GPIO_PRT18 529 #define P18_2_PIN 2u 530 #define P18_2_NUM 2u 531 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 532 #define P18_3_PORT GPIO_PRT18 533 #define P18_3_PIN 3u 534 #define P18_3_NUM 3u 535 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 536 #define P18_4_PORT GPIO_PRT18 537 #define P18_4_PIN 4u 538 #define P18_4_NUM 4u 539 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 540 #define P18_5_PORT GPIO_PRT18 541 #define P18_5_PIN 5u 542 #define P18_5_NUM 5u 543 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 544 #define P18_6_PORT GPIO_PRT18 545 #define P18_6_PIN 6u 546 #define P18_6_NUM 6u 547 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 548 #define P18_7_PORT GPIO_PRT18 549 #define P18_7_PIN 7u 550 #define P18_7_NUM 7u 551 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 552 553 /* PORT 19 (AUTOLVL) */ 554 #define P19_0_PORT GPIO_PRT19 555 #define P19_0_PIN 0u 556 #define P19_0_NUM 0u 557 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 558 #define P19_1_PORT GPIO_PRT19 559 #define P19_1_PIN 1u 560 #define P19_1_NUM 1u 561 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 562 #define P19_2_PORT GPIO_PRT19 563 #define P19_2_PIN 2u 564 #define P19_2_NUM 2u 565 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 566 #define P19_3_PORT GPIO_PRT19 567 #define P19_3_PIN 3u 568 #define P19_3_NUM 3u 569 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 570 #define P19_4_PORT GPIO_PRT19 571 #define P19_4_PIN 4u 572 #define P19_4_NUM 4u 573 #define P19_4_AMUXSEGMENT AMUXBUS_MAIN 574 575 /* PORT 20 (AUTOLVL) */ 576 #define P20_0_PORT GPIO_PRT20 577 #define P20_0_PIN 0u 578 #define P20_0_NUM 0u 579 #define P20_0_AMUXSEGMENT AMUXBUS_MAIN 580 #define P20_1_PORT GPIO_PRT20 581 #define P20_1_PIN 1u 582 #define P20_1_NUM 1u 583 #define P20_1_AMUXSEGMENT AMUXBUS_MAIN 584 #define P20_2_PORT GPIO_PRT20 585 #define P20_2_PIN 2u 586 #define P20_2_NUM 2u 587 #define P20_2_AMUXSEGMENT AMUXBUS_MAIN 588 #define P20_3_PORT GPIO_PRT20 589 #define P20_3_PIN 3u 590 #define P20_3_NUM 3u 591 #define P20_3_AMUXSEGMENT AMUXBUS_MAIN 592 #define P20_4_PORT GPIO_PRT20 593 #define P20_4_PIN 4u 594 #define P20_4_NUM 4u 595 #define P20_4_AMUXSEGMENT AMUXBUS_MAIN 596 #define P20_5_PORT GPIO_PRT20 597 #define P20_5_PIN 5u 598 #define P20_5_NUM 5u 599 #define P20_5_AMUXSEGMENT AMUXBUS_MAIN 600 #define P20_6_PORT GPIO_PRT20 601 #define P20_6_PIN 6u 602 #define P20_6_NUM 6u 603 #define P20_6_AMUXSEGMENT AMUXBUS_MAIN 604 #define P20_7_PORT GPIO_PRT20 605 #define P20_7_PIN 7u 606 #define P20_7_NUM 7u 607 #define P20_7_AMUXSEGMENT AMUXBUS_MAIN 608 609 /* PORT 21 (AUTOLVL) */ 610 #define P21_0_PORT GPIO_PRT21 611 #define P21_0_PIN 0u 612 #define P21_0_NUM 0u 613 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 614 #define P21_1_PORT GPIO_PRT21 615 #define P21_1_PIN 1u 616 #define P21_1_NUM 1u 617 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 618 #define P21_2_PORT GPIO_PRT21 619 #define P21_2_PIN 2u 620 #define P21_2_NUM 2u 621 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 622 #define P21_3_PORT GPIO_PRT21 623 #define P21_3_PIN 3u 624 #define P21_3_NUM 3u 625 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 626 #define P21_4_PORT GPIO_PRT21 627 #define P21_4_PIN 4u 628 #define P21_4_NUM 4u 629 #define P21_4_AMUXSEGMENT AMUXBUS_MAIN 630 #define P21_5_PORT GPIO_PRT21 631 #define P21_5_PIN 5u 632 #define P21_5_NUM 5u 633 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 634 #define P21_6_PORT GPIO_PRT21 635 #define P21_6_PIN 6u 636 #define P21_6_NUM 6u 637 #define P21_6_AMUXSEGMENT AMUXBUS_MAIN 638 #define P21_7_PORT GPIO_PRT21 639 #define P21_7_PIN 7u 640 #define P21_7_NUM 7u 641 #define P21_7_AMUXSEGMENT AMUXBUS_MAIN 642 643 /* PORT 22 (AUTOLVL) */ 644 #define P22_1_PORT GPIO_PRT22 645 #define P22_1_PIN 1u 646 #define P22_1_NUM 1u 647 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 648 #define P22_2_PORT GPIO_PRT22 649 #define P22_2_PIN 2u 650 #define P22_2_NUM 2u 651 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 652 #define P22_3_PORT GPIO_PRT22 653 #define P22_3_PIN 3u 654 #define P22_3_NUM 3u 655 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 656 #define P22_4_PORT GPIO_PRT22 657 #define P22_4_PIN 4u 658 #define P22_4_NUM 4u 659 #define P22_4_AMUXSEGMENT AMUXBUS_MAIN 660 #define P22_5_PORT GPIO_PRT22 661 #define P22_5_PIN 5u 662 #define P22_5_NUM 5u 663 #define P22_5_AMUXSEGMENT AMUXBUS_MAIN 664 #define P22_6_PORT GPIO_PRT22 665 #define P22_6_PIN 6u 666 #define P22_6_NUM 6u 667 #define P22_6_AMUXSEGMENT AMUXBUS_MAIN 668 #define P22_7_PORT GPIO_PRT22 669 #define P22_7_PIN 7u 670 #define P22_7_NUM 7u 671 #define P22_7_AMUXSEGMENT AMUXBUS_MAIN 672 673 /* PORT 23 (AUTOLVL) */ 674 #define P23_0_PORT GPIO_PRT23 675 #define P23_0_PIN 0u 676 #define P23_0_NUM 0u 677 #define P23_0_AMUXSEGMENT AMUXBUS_MAIN 678 #define P23_1_PORT GPIO_PRT23 679 #define P23_1_PIN 1u 680 #define P23_1_NUM 1u 681 #define P23_1_AMUXSEGMENT AMUXBUS_MAIN 682 #define P23_2_PORT GPIO_PRT23 683 #define P23_2_PIN 2u 684 #define P23_2_NUM 2u 685 #define P23_2_AMUXSEGMENT AMUXBUS_MAIN 686 #define P23_3_PORT GPIO_PRT23 687 #define P23_3_PIN 3u 688 #define P23_3_NUM 3u 689 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 690 #define P23_4_PORT GPIO_PRT23 691 #define P23_4_PIN 4u 692 #define P23_4_NUM 4u 693 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 694 #define P23_5_PORT GPIO_PRT23 695 #define P23_5_PIN 5u 696 #define P23_5_NUM 5u 697 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 698 #define P23_6_PORT GPIO_PRT23 699 #define P23_6_PIN 6u 700 #define P23_6_NUM 6u 701 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 702 #define P23_7_PORT GPIO_PRT23 703 #define P23_7_PIN 7u 704 #define P23_7_NUM 7u 705 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 706 707 /* Analog Connections */ 708 #define PASS0_I_TEMP_KELVIN_PORT 21u 709 #define PASS0_I_TEMP_KELVIN_PIN 2u 710 #define PASS0_SARMUX_MOTOR0_PORT 11u 711 #define PASS0_SARMUX_MOTOR0_PIN 0u 712 #define PASS0_SARMUX_MOTOR1_PORT 11u 713 #define PASS0_SARMUX_MOTOR1_PIN 1u 714 #define PASS0_SARMUX_MOTOR2_PORT 11u 715 #define PASS0_SARMUX_MOTOR2_PIN 2u 716 #define PASS0_SARMUX_PADS0_PORT 6u 717 #define PASS0_SARMUX_PADS0_PIN 0u 718 #define PASS0_SARMUX_PADS1_PORT 6u 719 #define PASS0_SARMUX_PADS1_PIN 1u 720 #define PASS0_SARMUX_PADS16_PORT 7u 721 #define PASS0_SARMUX_PADS16_PIN 0u 722 #define PASS0_SARMUX_PADS17_PORT 7u 723 #define PASS0_SARMUX_PADS17_PIN 1u 724 #define PASS0_SARMUX_PADS18_PORT 7u 725 #define PASS0_SARMUX_PADS18_PIN 2u 726 #define PASS0_SARMUX_PADS19_PORT 7u 727 #define PASS0_SARMUX_PADS19_PIN 3u 728 #define PASS0_SARMUX_PADS2_PORT 6u 729 #define PASS0_SARMUX_PADS2_PIN 2u 730 #define PASS0_SARMUX_PADS20_PORT 7u 731 #define PASS0_SARMUX_PADS20_PIN 4u 732 #define PASS0_SARMUX_PADS21_PORT 7u 733 #define PASS0_SARMUX_PADS21_PIN 5u 734 #define PASS0_SARMUX_PADS22_PORT 7u 735 #define PASS0_SARMUX_PADS22_PIN 6u 736 #define PASS0_SARMUX_PADS23_PORT 7u 737 #define PASS0_SARMUX_PADS23_PIN 7u 738 #define PASS0_SARMUX_PADS24_PORT 8u 739 #define PASS0_SARMUX_PADS24_PIN 1u 740 #define PASS0_SARMUX_PADS25_PORT 8u 741 #define PASS0_SARMUX_PADS25_PIN 2u 742 #define PASS0_SARMUX_PADS26_PORT 8u 743 #define PASS0_SARMUX_PADS26_PIN 3u 744 #define PASS0_SARMUX_PADS27_PORT 8u 745 #define PASS0_SARMUX_PADS27_PIN 4u 746 #define PASS0_SARMUX_PADS28_PORT 9u 747 #define PASS0_SARMUX_PADS28_PIN 0u 748 #define PASS0_SARMUX_PADS29_PORT 9u 749 #define PASS0_SARMUX_PADS29_PIN 1u 750 #define PASS0_SARMUX_PADS3_PORT 6u 751 #define PASS0_SARMUX_PADS3_PIN 3u 752 #define PASS0_SARMUX_PADS30_PORT 9u 753 #define PASS0_SARMUX_PADS30_PIN 2u 754 #define PASS0_SARMUX_PADS31_PORT 9u 755 #define PASS0_SARMUX_PADS31_PIN 3u 756 #define PASS0_SARMUX_PADS32_PORT 10u 757 #define PASS0_SARMUX_PADS32_PIN 4u 758 #define PASS0_SARMUX_PADS33_PORT 10u 759 #define PASS0_SARMUX_PADS33_PIN 5u 760 #define PASS0_SARMUX_PADS34_PORT 10u 761 #define PASS0_SARMUX_PADS34_PIN 6u 762 #define PASS0_SARMUX_PADS35_PORT 10u 763 #define PASS0_SARMUX_PADS35_PIN 7u 764 #define PASS0_SARMUX_PADS36_PORT 12u 765 #define PASS0_SARMUX_PADS36_PIN 0u 766 #define PASS0_SARMUX_PADS37_PORT 12u 767 #define PASS0_SARMUX_PADS37_PIN 1u 768 #define PASS0_SARMUX_PADS38_PORT 12u 769 #define PASS0_SARMUX_PADS38_PIN 2u 770 #define PASS0_SARMUX_PADS39_PORT 12u 771 #define PASS0_SARMUX_PADS39_PIN 3u 772 #define PASS0_SARMUX_PADS4_PORT 6u 773 #define PASS0_SARMUX_PADS4_PIN 4u 774 #define PASS0_SARMUX_PADS40_PORT 12u 775 #define PASS0_SARMUX_PADS40_PIN 4u 776 #define PASS0_SARMUX_PADS41_PORT 12u 777 #define PASS0_SARMUX_PADS41_PIN 5u 778 #define PASS0_SARMUX_PADS42_PORT 12u 779 #define PASS0_SARMUX_PADS42_PIN 6u 780 #define PASS0_SARMUX_PADS43_PORT 12u 781 #define PASS0_SARMUX_PADS43_PIN 7u 782 #define PASS0_SARMUX_PADS44_PORT 13u 783 #define PASS0_SARMUX_PADS44_PIN 0u 784 #define PASS0_SARMUX_PADS45_PORT 13u 785 #define PASS0_SARMUX_PADS45_PIN 1u 786 #define PASS0_SARMUX_PADS46_PORT 13u 787 #define PASS0_SARMUX_PADS46_PIN 2u 788 #define PASS0_SARMUX_PADS47_PORT 13u 789 #define PASS0_SARMUX_PADS47_PIN 3u 790 #define PASS0_SARMUX_PADS48_PORT 13u 791 #define PASS0_SARMUX_PADS48_PIN 4u 792 #define PASS0_SARMUX_PADS49_PORT 13u 793 #define PASS0_SARMUX_PADS49_PIN 5u 794 #define PASS0_SARMUX_PADS5_PORT 6u 795 #define PASS0_SARMUX_PADS5_PIN 5u 796 #define PASS0_SARMUX_PADS50_PORT 13u 797 #define PASS0_SARMUX_PADS50_PIN 6u 798 #define PASS0_SARMUX_PADS51_PORT 13u 799 #define PASS0_SARMUX_PADS51_PIN 7u 800 #define PASS0_SARMUX_PADS52_PORT 14u 801 #define PASS0_SARMUX_PADS52_PIN 0u 802 #define PASS0_SARMUX_PADS53_PORT 14u 803 #define PASS0_SARMUX_PADS53_PIN 1u 804 #define PASS0_SARMUX_PADS54_PORT 14u 805 #define PASS0_SARMUX_PADS54_PIN 2u 806 #define PASS0_SARMUX_PADS55_PORT 14u 807 #define PASS0_SARMUX_PADS55_PIN 3u 808 #define PASS0_SARMUX_PADS56_PORT 14u 809 #define PASS0_SARMUX_PADS56_PIN 4u 810 #define PASS0_SARMUX_PADS57_PORT 14u 811 #define PASS0_SARMUX_PADS57_PIN 5u 812 #define PASS0_SARMUX_PADS58_PORT 14u 813 #define PASS0_SARMUX_PADS58_PIN 6u 814 #define PASS0_SARMUX_PADS59_PORT 14u 815 #define PASS0_SARMUX_PADS59_PIN 7u 816 #define PASS0_SARMUX_PADS6_PORT 6u 817 #define PASS0_SARMUX_PADS6_PIN 6u 818 #define PASS0_SARMUX_PADS60_PORT 15u 819 #define PASS0_SARMUX_PADS60_PIN 0u 820 #define PASS0_SARMUX_PADS61_PORT 15u 821 #define PASS0_SARMUX_PADS61_PIN 1u 822 #define PASS0_SARMUX_PADS62_PORT 15u 823 #define PASS0_SARMUX_PADS62_PIN 2u 824 #define PASS0_SARMUX_PADS63_PORT 15u 825 #define PASS0_SARMUX_PADS63_PIN 3u 826 #define PASS0_SARMUX_PADS67_PORT 16u 827 #define PASS0_SARMUX_PADS67_PIN 3u 828 #define PASS0_SARMUX_PADS7_PORT 6u 829 #define PASS0_SARMUX_PADS7_PIN 7u 830 #define PASS0_SARMUX_PADS72_PORT 17u 831 #define PASS0_SARMUX_PADS72_PIN 0u 832 #define PASS0_SARMUX_PADS73_PORT 17u 833 #define PASS0_SARMUX_PADS73_PIN 1u 834 #define PASS0_SARMUX_PADS74_PORT 17u 835 #define PASS0_SARMUX_PADS74_PIN 2u 836 #define PASS0_SARMUX_PADS75_PORT 17u 837 #define PASS0_SARMUX_PADS75_PIN 3u 838 #define PASS0_SARMUX_PADS76_PORT 17u 839 #define PASS0_SARMUX_PADS76_PIN 4u 840 #define PASS0_SARMUX_PADS77_PORT 17u 841 #define PASS0_SARMUX_PADS77_PIN 5u 842 #define PASS0_SARMUX_PADS78_PORT 17u 843 #define PASS0_SARMUX_PADS78_PIN 6u 844 #define PASS0_SARMUX_PADS79_PORT 17u 845 #define PASS0_SARMUX_PADS79_PIN 7u 846 #define PASS0_SARMUX_PADS80_PORT 18u 847 #define PASS0_SARMUX_PADS80_PIN 0u 848 #define PASS0_SARMUX_PADS81_PORT 18u 849 #define PASS0_SARMUX_PADS81_PIN 1u 850 #define PASS0_SARMUX_PADS82_PORT 18u 851 #define PASS0_SARMUX_PADS82_PIN 2u 852 #define PASS0_SARMUX_PADS83_PORT 18u 853 #define PASS0_SARMUX_PADS83_PIN 3u 854 #define PASS0_SARMUX_PADS84_PORT 18u 855 #define PASS0_SARMUX_PADS84_PIN 4u 856 #define PASS0_SARMUX_PADS85_PORT 18u 857 #define PASS0_SARMUX_PADS85_PIN 5u 858 #define PASS0_SARMUX_PADS86_PORT 18u 859 #define PASS0_SARMUX_PADS86_PIN 6u 860 #define PASS0_SARMUX_PADS87_PORT 18u 861 #define PASS0_SARMUX_PADS87_PIN 7u 862 #define PASS0_SARMUX_PADS88_PORT 19u 863 #define PASS0_SARMUX_PADS88_PIN 0u 864 #define PASS0_SARMUX_PADS89_PORT 19u 865 #define PASS0_SARMUX_PADS89_PIN 1u 866 #define PASS0_SARMUX_PADS90_PORT 19u 867 #define PASS0_SARMUX_PADS90_PIN 2u 868 #define PASS0_SARMUX_PADS91_PORT 19u 869 #define PASS0_SARMUX_PADS91_PIN 3u 870 #define PASS0_SARMUX_PADS92_PORT 19u 871 #define PASS0_SARMUX_PADS92_PIN 4u 872 #define PASS0_SARMUX_PADS93_PORT 20u 873 #define PASS0_SARMUX_PADS93_PIN 0u 874 #define PASS0_SARMUX_PADS94_PORT 20u 875 #define PASS0_SARMUX_PADS94_PIN 1u 876 #define PASS0_SARMUX_PADS95_PORT 20u 877 #define PASS0_SARMUX_PADS95_PIN 2u 878 #define PASS0_VB_TEMP_KELVIN_PORT 10u 879 #define PASS0_VB_TEMP_KELVIN_PIN 4u 880 #define PASS0_VE_TEMP_KELVIN_PORT 23u 881 #define PASS0_VE_TEMP_KELVIN_PIN 4u 882 #define SRSS_ADFT_PIN0_PORT 23u 883 #define SRSS_ADFT_PIN0_PIN 4u 884 #define SRSS_ADFT_PIN1_PORT 23u 885 #define SRSS_ADFT_PIN1_PIN 3u 886 #define SRSS_ADFT_POR_PAD_HV_PORT 21u 887 #define SRSS_ADFT_POR_PAD_HV_PIN 4u 888 #define SRSS_ECO_IN_PORT 21u 889 #define SRSS_ECO_IN_PIN 2u 890 #define SRSS_ECO_OUT_PORT 21u 891 #define SRSS_ECO_OUT_PIN 3u 892 #define SRSS_REGHC_ISENSE_INM_PORT 22u 893 #define SRSS_REGHC_ISENSE_INM_PIN 2u 894 #define SRSS_REGHC_ISENSE_INP_PORT 22u 895 #define SRSS_REGHC_ISENSE_INP_PIN 1u 896 #define SRSS_REGHC_RST_VOUT_PORT 22u 897 #define SRSS_REGHC_RST_VOUT_PIN 3u 898 #define SRSS_VEXT_REF_REG_PORT 21u 899 #define SRSS_VEXT_REF_REG_PIN 3u 900 #define SRSS_WCO_IN_PORT 21u 901 #define SRSS_WCO_IN_PIN 0u 902 #define SRSS_WCO_OUT_PORT 21u 903 #define SRSS_WCO_OUT_PIN 1u 904 905 /* HSIOM Connections */ 906 typedef enum 907 { 908 /* Generic HSIOM connections */ 909 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 910 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 911 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 912 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 913 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 914 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 915 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 916 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 917 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 918 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 919 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 920 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 921 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 922 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 923 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 924 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 925 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 926 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 927 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 928 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 929 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 930 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 931 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 932 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 933 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 934 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 935 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 936 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 937 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 938 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 939 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 940 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 941 942 /* P0.0 */ 943 P0_0_GPIO = 0, /* GPIO controls 'out' */ 944 P0_0_AMUXA = 4, /* Analog mux bus A */ 945 P0_0_AMUXB = 5, /* Analog mux bus B */ 946 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 947 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 948 P0_0_TCPWM1_LINE18 = 8, /* Digital Active - tcpwm[1].line[18]:1 */ 949 P0_0_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:1 */ 950 P0_0_TCPWM1_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[54]:1 */ 951 P0_0_TCPWM1_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[67]:1 */ 952 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 953 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 954 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 955 P0_0_TCPWM0_LINE512 = 22, /* Digital Active - tcpwm[0].line[512] */ 956 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 957 958 /* P0.1 */ 959 P0_1_GPIO = 0, /* GPIO controls 'out' */ 960 P0_1_AMUXA = 4, /* Analog mux bus A */ 961 P0_1_AMUXB = 5, /* Analog mux bus B */ 962 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 963 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 964 P0_1_TCPWM1_LINE17 = 8, /* Digital Active - tcpwm[1].line[17]:1 */ 965 P0_1_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ 966 P0_1_TCPWM1_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[51]:1 */ 967 P0_1_TCPWM1_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[55]:1 */ 968 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 969 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 970 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 971 P0_1_TCPWM0_LINE_COMPL512 = 22, /* Digital Active - tcpwm[0].line_compl[512] */ 972 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 973 974 /* P0.2 */ 975 P0_2_GPIO = 0, /* GPIO controls 'out' */ 976 P0_2_AMUXA = 4, /* Analog mux bus A */ 977 P0_2_AMUXB = 5, /* Analog mux bus B */ 978 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 979 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 980 P0_2_TCPWM1_LINE14 = 8, /* Digital Active - tcpwm[1].line[14]:1 */ 981 P0_2_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ 982 P0_2_TCPWM1_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[42]:1 */ 983 P0_2_TCPWM1_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[52]:1 */ 984 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 985 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 986 P0_2_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:2 */ 987 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 988 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 989 P0_2_TCPWM0_TR_ONE_CNT_IN1536 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536] */ 990 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 991 992 /* P0.3 */ 993 P0_3_GPIO = 0, /* GPIO controls 'out' */ 994 P0_3_AMUXA = 4, /* Analog mux bus A */ 995 P0_3_AMUXB = 5, /* Analog mux bus B */ 996 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 997 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 998 P0_3_TCPWM1_LINE13 = 8, /* Digital Active - tcpwm[1].line[13]:1 */ 999 P0_3_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 1000 P0_3_TCPWM1_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[39]:1 */ 1001 P0_3_TCPWM1_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[43]:1 */ 1002 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 1003 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 1004 P0_3_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:2 */ 1005 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 1006 P0_3_TCPWM0_TR_ONE_CNT_IN1537 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537] */ 1007 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 1008 1009 /* P1.0 */ 1010 P1_0_GPIO = 0, /* GPIO controls 'out' */ 1011 P1_0_AMUXA = 4, /* Analog mux bus A */ 1012 P1_0_AMUXB = 5, /* Analog mux bus B */ 1013 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1014 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1015 P1_0_TCPWM1_LINE12 = 8, /* Digital Active - tcpwm[1].line[12]:1 */ 1016 P1_0_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:1 */ 1017 P1_0_TCPWM1_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[36]:1 */ 1018 P1_0_TCPWM1_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[40]:1 */ 1019 P1_0_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 1020 P1_0_TCPWM1_LINE516 = 16, /* Digital Active - tcpwm[1].line[516]:0 */ 1021 P1_0_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:2 */ 1022 P1_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 1023 1024 /* P1.1 */ 1025 P1_1_GPIO = 0, /* GPIO controls 'out' */ 1026 P1_1_AMUXA = 4, /* Analog mux bus A */ 1027 P1_1_AMUXB = 5, /* Analog mux bus B */ 1028 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1029 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1030 P1_1_TCPWM1_LINE11 = 8, /* Digital Active - tcpwm[1].line[11]:1 */ 1031 P1_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ 1032 P1_1_TCPWM1_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[33]:1 */ 1033 P1_1_TCPWM1_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[37]:1 */ 1034 P1_1_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 1035 P1_1_TCPWM1_LINE517 = 16, /* Digital Active - tcpwm[1].line[517]:0 */ 1036 P1_1_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:2 */ 1037 P1_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 1038 1039 /* P1.2 */ 1040 P1_2_GPIO = 0, /* GPIO controls 'out' */ 1041 P1_2_AMUXA = 4, /* Analog mux bus A */ 1042 P1_2_AMUXB = 5, /* Analog mux bus B */ 1043 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1044 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1045 P1_2_TCPWM1_LINE10 = 8, /* Digital Active - tcpwm[1].line[10]:1 */ 1046 P1_2_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ 1047 P1_2_TCPWM1_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[30]:1 */ 1048 P1_2_TCPWM1_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[34]:1 */ 1049 P1_2_TCPWM1_LINE518 = 16, /* Digital Active - tcpwm[1].line[518]:0 */ 1050 P1_2_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:2 */ 1051 P1_2_PERI_TR_IO_INPUT0 = 26, /* Digital Active - peri.tr_io_input[0]:0 */ 1052 P1_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:1 */ 1053 1054 /* P1.3 */ 1055 P1_3_GPIO = 0, /* GPIO controls 'out' */ 1056 P1_3_AMUXA = 4, /* Analog mux bus A */ 1057 P1_3_AMUXB = 5, /* Analog mux bus B */ 1058 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1059 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1060 P1_3_TCPWM1_LINE8 = 8, /* Digital Active - tcpwm[1].line[8]:1 */ 1061 P1_3_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:1 */ 1062 P1_3_TCPWM1_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[24]:1 */ 1063 P1_3_TCPWM1_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[31]:1 */ 1064 P1_3_TCPWM1_LINE519 = 16, /* Digital Active - tcpwm[1].line[519]:0 */ 1065 P1_3_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:2 */ 1066 P1_3_PERI_TR_IO_INPUT1 = 26, /* Digital Active - peri.tr_io_input[1]:0 */ 1067 P1_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:1 */ 1068 1069 /* P2.0 */ 1070 P2_0_GPIO = 0, /* GPIO controls 'out' */ 1071 P2_0_AMUXA = 4, /* Analog mux bus A */ 1072 P2_0_AMUXB = 5, /* Analog mux bus B */ 1073 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1074 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1075 P2_0_TCPWM1_LINE7 = 8, /* Digital Active - tcpwm[1].line[7]:1 */ 1076 P2_0_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 1077 P2_0_TCPWM1_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[21]:1 */ 1078 P2_0_TCPWM1_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[25]:1 */ 1079 P2_0_TCPWM1_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1548]:0 */ 1080 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 1081 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 1082 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 1083 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 1084 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 1085 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 1086 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 1087 1088 /* P2.1 */ 1089 P2_1_GPIO = 0, /* GPIO controls 'out' */ 1090 P2_1_AMUXA = 4, /* Analog mux bus A */ 1091 P2_1_AMUXB = 5, /* Analog mux bus B */ 1092 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1093 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1094 P2_1_TCPWM1_LINE6 = 8, /* Digital Active - tcpwm[1].line[6]:1 */ 1095 P2_1_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 1096 P2_1_TCPWM1_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[18]:1 */ 1097 P2_1_TCPWM1_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[22]:1 */ 1098 P2_1_TCPWM1_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1551]:0 */ 1099 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 1100 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 1101 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 1102 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 1103 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 1104 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 1105 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 1106 1107 /* P2.2 */ 1108 P2_2_GPIO = 0, /* GPIO controls 'out' */ 1109 P2_2_AMUXA = 4, /* Analog mux bus A */ 1110 P2_2_AMUXB = 5, /* Analog mux bus B */ 1111 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1112 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1113 P2_2_TCPWM1_LINE5 = 8, /* Digital Active - tcpwm[1].line[5]:1 */ 1114 P2_2_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 1115 P2_2_TCPWM1_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[15]:1 */ 1116 P2_2_TCPWM1_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[19]:1 */ 1117 P2_2_TCPWM1_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1554]:0 */ 1118 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 1119 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 1120 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 1121 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 1122 P2_2_ETH0_RX_ER = 24, /* Digital Active - eth[0].rx_er:0 */ 1123 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 1124 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 1125 1126 /* P2.3 */ 1127 P2_3_GPIO = 0, /* GPIO controls 'out' */ 1128 P2_3_AMUXA = 4, /* Analog mux bus A */ 1129 P2_3_AMUXB = 5, /* Analog mux bus B */ 1130 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1131 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1132 P2_3_TCPWM1_LINE4 = 8, /* Digital Active - tcpwm[1].line[4]:1 */ 1133 P2_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 1134 P2_3_TCPWM1_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[12]:1 */ 1135 P2_3_TCPWM1_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[16]:1 */ 1136 P2_3_TCPWM1_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1557]:0 */ 1137 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 1138 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 1139 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 1140 P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL = 24, /* Digital Active - eth[0].eth_tsu_timer_cmp_val:0 */ 1141 P2_3_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:2 */ 1142 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 1143 1144 /* P2.4 */ 1145 P2_4_GPIO = 0, /* GPIO controls 'out' */ 1146 P2_4_AMUXA = 4, /* Analog mux bus A */ 1147 P2_4_AMUXB = 5, /* Analog mux bus B */ 1148 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1149 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1150 P2_4_TCPWM1_LINE3 = 8, /* Digital Active - tcpwm[1].line[3]:1 */ 1151 P2_4_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 1152 P2_4_TCPWM1_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[9]:1 */ 1153 P2_4_TCPWM1_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[13]:1 */ 1154 P2_4_TCPWM1_LINE_COMPL516 = 16, /* Digital Active - tcpwm[1].line_compl[516]:0 */ 1155 P2_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:0 */ 1156 P2_4_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:1 */ 1157 P2_4_PERI_TR_IO_INPUT6 = 26, /* Digital Active - peri.tr_io_input[6]:0 */ 1158 1159 /* P2.5 */ 1160 P2_5_GPIO = 0, /* GPIO controls 'out' */ 1161 P2_5_AMUXA = 4, /* Analog mux bus A */ 1162 P2_5_AMUXB = 5, /* Analog mux bus B */ 1163 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1164 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1165 P2_5_TCPWM1_LINE2 = 8, /* Digital Active - tcpwm[1].line[2]:1 */ 1166 P2_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1167 P2_5_TCPWM1_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[6]:1 */ 1168 P2_5_TCPWM1_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[10]:1 */ 1169 P2_5_TCPWM1_LINE_COMPL517 = 16, /* Digital Active - tcpwm[1].line_compl[517]:0 */ 1170 P2_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:0 */ 1171 P2_5_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:1 */ 1172 P2_5_PERI_TR_IO_INPUT7 = 26, /* Digital Active - peri.tr_io_input[7]:0 */ 1173 1174 /* P3.0 */ 1175 P3_0_GPIO = 0, /* GPIO controls 'out' */ 1176 P3_0_AMUXA = 4, /* Analog mux bus A */ 1177 P3_0_AMUXB = 5, /* Analog mux bus B */ 1178 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1179 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1180 P3_0_TCPWM1_LINE1 = 8, /* Digital Active - tcpwm[1].line[1]:1 */ 1181 P3_0_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1182 P3_0_TCPWM1_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[3]:1 */ 1183 P3_0_TCPWM1_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[7]:1 */ 1184 P3_0_TCPWM1_LINE_COMPL518 = 16, /* Digital Active - tcpwm[1].line_compl[518]:0 */ 1185 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 1186 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 1187 P3_0_CANFD0_TTCAN_TX3 = 21, /* Digital Active - canfd[0].ttcan_tx[3]:0 */ 1188 P3_0_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio:0 */ 1189 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 1190 1191 /* P3.1 */ 1192 P3_1_GPIO = 0, /* GPIO controls 'out' */ 1193 P3_1_AMUXA = 4, /* Analog mux bus A */ 1194 P3_1_AMUXB = 5, /* Analog mux bus B */ 1195 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1196 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1197 P3_1_TCPWM1_LINE0 = 8, /* Digital Active - tcpwm[1].line[0]:1 */ 1198 P3_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1199 P3_1_TCPWM1_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[0]:1 */ 1200 P3_1_TCPWM1_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[4]:1 */ 1201 P3_1_TCPWM1_LINE_COMPL519 = 16, /* Digital Active - tcpwm[1].line_compl[519]:0 */ 1202 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 1203 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 1204 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 1205 P3_1_CANFD0_TTCAN_RX3 = 21, /* Digital Active - canfd[0].ttcan_rx[3]:0 */ 1206 P3_1_ETH0_MDC = 24, /* Digital Active - eth[0].mdc:0 */ 1207 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 1208 1209 /* P3.2 */ 1210 P3_2_GPIO = 0, /* GPIO controls 'out' */ 1211 P3_2_AMUXA = 4, /* Analog mux bus A */ 1212 P3_2_AMUXB = 5, /* Analog mux bus B */ 1213 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1214 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1215 P3_2_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:1 */ 1216 P3_2_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1217 P3_2_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:1 */ 1218 P3_2_TCPWM1_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[1]:1 */ 1219 P3_2_TCPWM1_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1549]:0 */ 1220 P3_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:0 */ 1221 P3_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:0 */ 1222 P3_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:0 */ 1223 1224 /* P3.3 */ 1225 P3_3_GPIO = 0, /* GPIO controls 'out' */ 1226 P3_3_AMUXA = 4, /* Analog mux bus A */ 1227 P3_3_AMUXB = 5, /* Analog mux bus B */ 1228 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1229 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1230 P3_3_TCPWM1_LINE258 = 8, /* Digital Active - tcpwm[1].line[258]:1 */ 1231 P3_3_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:1 */ 1232 P3_3_TCPWM1_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[774]:1 */ 1233 P3_3_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:1 */ 1234 P3_3_TCPWM1_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1552]:0 */ 1235 P3_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:0 */ 1236 P3_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:0 */ 1237 1238 /* P3.4 */ 1239 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1240 P3_4_AMUXA = 4, /* Analog mux bus A */ 1241 P3_4_AMUXB = 5, /* Analog mux bus B */ 1242 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1243 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1244 P3_4_TCPWM1_LINE257 = 8, /* Digital Active - tcpwm[1].line[257]:1 */ 1245 P3_4_TCPWM1_LINE_COMPL258 = 9, /* Digital Active - tcpwm[1].line_compl[258]:1 */ 1246 P3_4_TCPWM1_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[771]:1 */ 1247 P3_4_TCPWM1_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[775]:1 */ 1248 P3_4_TCPWM1_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1555]:0 */ 1249 P3_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:0 */ 1250 P3_4_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:2 */ 1251 1252 /* P3.5 */ 1253 P3_5_GPIO = 0, /* GPIO controls 'out' */ 1254 P3_5_AMUXA = 4, /* Analog mux bus A */ 1255 P3_5_AMUXB = 5, /* Analog mux bus B */ 1256 P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1257 P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1258 P3_5_TCPWM1_LINE256 = 8, /* Digital Active - tcpwm[1].line[256]:1 */ 1259 P3_5_TCPWM1_LINE_COMPL257 = 9, /* Digital Active - tcpwm[1].line_compl[257]:1 */ 1260 P3_5_TCPWM1_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[768]:1 */ 1261 P3_5_TCPWM1_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[772]:1 */ 1262 P3_5_TCPWM1_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1558]:0 */ 1263 P3_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:0 */ 1264 P3_5_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:2 */ 1265 1266 /* P4.0 */ 1267 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1268 P4_0_AMUXA = 4, /* Analog mux bus A */ 1269 P4_0_AMUXB = 5, /* Analog mux bus B */ 1270 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1271 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1272 P4_0_TCPWM1_LINE4 = 8, /* Digital Active - tcpwm[1].line[4]:0 */ 1273 P4_0_TCPWM1_LINE_COMPL256 = 9, /* Digital Active - tcpwm[1].line_compl[256]:1 */ 1274 P4_0_TCPWM1_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[12]:0 */ 1275 P4_0_TCPWM1_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[769]:1 */ 1276 P4_0_PASS0_SAR_EXT_MUX_SEL0 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[0] */ 1277 P4_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:0 */ 1278 P4_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:0 */ 1279 P4_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:1 */ 1280 P4_0_PERI_TR_IO_INPUT10 = 26, /* Digital Active - peri.tr_io_input[10]:0 */ 1281 1282 /* P4.1 */ 1283 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1284 P4_1_AMUXA = 4, /* Analog mux bus A */ 1285 P4_1_AMUXB = 5, /* Analog mux bus B */ 1286 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1287 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1288 P4_1_TCPWM1_LINE5 = 8, /* Digital Active - tcpwm[1].line[5]:0 */ 1289 P4_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 1290 P4_1_TCPWM1_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[15]:0 */ 1291 P4_1_TCPWM1_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[13]:0 */ 1292 P4_1_PASS0_SAR_EXT_MUX_SEL1 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[1] */ 1293 P4_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:0 */ 1294 P4_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:0 */ 1295 P4_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:0 */ 1296 P4_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:1 */ 1297 P4_1_PERI_TR_IO_INPUT11 = 26, /* Digital Active - peri.tr_io_input[11]:0 */ 1298 1299 /* P4.2 */ 1300 P4_2_GPIO = 0, /* GPIO controls 'out' */ 1301 P4_2_AMUXA = 4, /* Analog mux bus A */ 1302 P4_2_AMUXB = 5, /* Analog mux bus B */ 1303 P4_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1304 P4_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1305 P4_2_TCPWM1_LINE6 = 8, /* Digital Active - tcpwm[1].line[6]:0 */ 1306 P4_2_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 1307 P4_2_TCPWM1_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[18]:0 */ 1308 P4_2_TCPWM1_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[16]:0 */ 1309 P4_2_PASS0_SAR_EXT_MUX_SEL2 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[2] */ 1310 P4_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:0 */ 1311 P4_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:0 */ 1312 P4_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:0 */ 1313 P4_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:1 */ 1314 P4_2_PERI_TR_IO_INPUT12 = 26, /* Digital Active - peri.tr_io_input[12]:0 */ 1315 1316 /* P4.3 */ 1317 P4_3_GPIO = 0, /* GPIO controls 'out' */ 1318 P4_3_AMUXA = 4, /* Analog mux bus A */ 1319 P4_3_AMUXB = 5, /* Analog mux bus B */ 1320 P4_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1321 P4_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1322 P4_3_TCPWM1_LINE7 = 8, /* Digital Active - tcpwm[1].line[7]:0 */ 1323 P4_3_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 1324 P4_3_TCPWM1_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[21]:0 */ 1325 P4_3_TCPWM1_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[19]:0 */ 1326 P4_3_PASS0_SAR_EXT_MUX_EN0 = 16, /* Digital Active - pass[0].sar_ext_mux_en[0] */ 1327 P4_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:0 */ 1328 P4_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:0 */ 1329 P4_3_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:1 */ 1330 P4_3_PERI_TR_IO_INPUT13 = 26, /* Digital Active - peri.tr_io_input[13]:0 */ 1331 1332 /* P4.4 */ 1333 P4_4_GPIO = 0, /* GPIO controls 'out' */ 1334 P4_4_AMUXA = 4, /* Analog mux bus A */ 1335 P4_4_AMUXB = 5, /* Analog mux bus B */ 1336 P4_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1337 P4_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1338 P4_4_TCPWM1_LINE8 = 8, /* Digital Active - tcpwm[1].line[8]:0 */ 1339 P4_4_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 1340 P4_4_TCPWM1_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[24]:0 */ 1341 P4_4_TCPWM1_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[22]:0 */ 1342 P4_4_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:1 */ 1343 P4_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:0 */ 1344 P4_4_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:1 */ 1345 1346 /* P5.0 */ 1347 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1348 P5_0_AMUXA = 4, /* Analog mux bus A */ 1349 P5_0_AMUXB = 5, /* Analog mux bus B */ 1350 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1351 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1352 P5_0_TCPWM1_LINE9 = 8, /* Digital Active - tcpwm[1].line[9]:0 */ 1353 P5_0_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 1354 P5_0_TCPWM1_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[27]:0 */ 1355 P5_0_TCPWM1_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[25]:0 */ 1356 P5_0_TCPWM1_LINE522 = 16, /* Digital Active - tcpwm[1].line[522]:0 */ 1357 P5_0_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:1 */ 1358 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 1359 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 1360 P5_0_TCPWM0_LINE256 = 22, /* Digital Active - tcpwm[0].line[256] */ 1361 P5_0_PERI_TR_IO_INPUT38 = 26, /* Digital Active - peri.tr_io_input[38]:0 */ 1362 1363 /* P5.1 */ 1364 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1365 P5_1_AMUXA = 4, /* Analog mux bus A */ 1366 P5_1_AMUXB = 5, /* Analog mux bus B */ 1367 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1368 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1369 P5_1_TCPWM1_LINE10 = 8, /* Digital Active - tcpwm[1].line[10]:0 */ 1370 P5_1_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 1371 P5_1_TCPWM1_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[30]:0 */ 1372 P5_1_TCPWM1_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[28]:0 */ 1373 P5_1_TCPWM1_LINE_COMPL522 = 16, /* Digital Active - tcpwm[1].line_compl[522]:0 */ 1374 P5_1_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:1 */ 1375 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 1376 P5_1_TCPWM0_LINE_COMPL256 = 22, /* Digital Active - tcpwm[0].line_compl[256] */ 1377 P5_1_PERI_TR_IO_INPUT39 = 26, /* Digital Active - peri.tr_io_input[39]:0 */ 1378 1379 /* P5.2 */ 1380 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1381 P5_2_AMUXA = 4, /* Analog mux bus A */ 1382 P5_2_AMUXB = 5, /* Analog mux bus B */ 1383 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1384 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1385 P5_2_TCPWM1_LINE11 = 8, /* Digital Active - tcpwm[1].line[11]:0 */ 1386 P5_2_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 1387 P5_2_TCPWM1_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[33]:0 */ 1388 P5_2_TCPWM1_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[31]:0 */ 1389 P5_2_TCPWM1_TR_ONE_CNT_IN1566 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1566]:0 */ 1390 P5_2_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:2 */ 1391 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 1392 P5_2_TCPWM0_TR_ONE_CNT_IN768 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[768] */ 1393 1394 /* P5.3 */ 1395 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1396 P5_3_AMUXA = 4, /* Analog mux bus A */ 1397 P5_3_AMUXB = 5, /* Analog mux bus B */ 1398 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1399 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1400 P5_3_TCPWM1_LINE12 = 8, /* Digital Active - tcpwm[1].line[12]:0 */ 1401 P5_3_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1402 P5_3_TCPWM1_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[36]:0 */ 1403 P5_3_TCPWM1_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[34]:0 */ 1404 P5_3_TCPWM1_TR_ONE_CNT_IN1567 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1567]:0 */ 1405 P5_3_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:2 */ 1406 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 1407 P5_3_TCPWM0_TR_ONE_CNT_IN769 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[769] */ 1408 1409 /* P5.4 */ 1410 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1411 P5_4_AMUXA = 4, /* Analog mux bus A */ 1412 P5_4_AMUXB = 5, /* Analog mux bus B */ 1413 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1414 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1415 P5_4_TCPWM1_LINE13 = 8, /* Digital Active - tcpwm[1].line[13]:0 */ 1416 P5_4_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1417 P5_4_TCPWM1_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[39]:0 */ 1418 P5_4_TCPWM1_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[37]:0 */ 1419 P5_4_TCPWM1_LINE523 = 16, /* Digital Active - tcpwm[1].line[523]:0 */ 1420 P5_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:0 */ 1421 P5_4_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:1 */ 1422 1423 /* P5.5 */ 1424 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1425 P5_5_AMUXA = 4, /* Analog mux bus A */ 1426 P5_5_AMUXB = 5, /* Analog mux bus B */ 1427 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1428 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1429 P5_5_TCPWM1_LINE14 = 8, /* Digital Active - tcpwm[1].line[14]:0 */ 1430 P5_5_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1431 P5_5_TCPWM1_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[42]:0 */ 1432 P5_5_TCPWM1_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[40]:0 */ 1433 P5_5_TCPWM1_LINE_COMPL523 = 16, /* Digital Active - tcpwm[1].line_compl[523]:0 */ 1434 P5_5_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:0 */ 1435 P5_5_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:1 */ 1436 1437 /* P6.0 */ 1438 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1439 P6_0_AMUXA = 4, /* Analog mux bus A */ 1440 P6_0_AMUXB = 5, /* Analog mux bus B */ 1441 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1442 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1443 P6_0_TCPWM1_LINE256 = 8, /* Digital Active - tcpwm[1].line[256]:0 */ 1444 P6_0_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 1445 P6_0_TCPWM1_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[768]:0 */ 1446 P6_0_TCPWM1_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[43]:0 */ 1447 P6_0_TCPWM1_TR_ONE_CNT_IN1569 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1569]:0 */ 1448 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 1449 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 1450 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 1451 P6_0_TCPWM0_LINE0 = 22, /* Digital Active - tcpwm[0].line[0] */ 1452 P6_0_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:1 */ 1453 1454 /* P6.1 */ 1455 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1456 P6_1_AMUXA = 4, /* Analog mux bus A */ 1457 P6_1_AMUXB = 5, /* Analog mux bus B */ 1458 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1459 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1460 P6_1_TCPWM1_LINE0 = 8, /* Digital Active - tcpwm[1].line[0]:0 */ 1461 P6_1_TCPWM1_LINE_COMPL256 = 9, /* Digital Active - tcpwm[1].line_compl[256]:0 */ 1462 P6_1_TCPWM1_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[0]:0 */ 1463 P6_1_TCPWM1_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[769]:0 */ 1464 P6_1_TCPWM1_TR_ONE_CNT_IN1570 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1570]:0 */ 1465 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 1466 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 1467 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 1468 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 1469 1470 /* P6.2 */ 1471 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1472 P6_2_AMUXA = 4, /* Analog mux bus A */ 1473 P6_2_AMUXB = 5, /* Analog mux bus B */ 1474 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1475 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1476 P6_2_TCPWM1_LINE257 = 8, /* Digital Active - tcpwm[1].line[257]:0 */ 1477 P6_2_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 1478 P6_2_TCPWM1_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[771]:0 */ 1479 P6_2_TCPWM1_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[1]:0 */ 1480 P6_2_TCPWM1_LINE524 = 16, /* Digital Active - tcpwm[1].line[524]:0 */ 1481 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 1482 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 1483 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 1484 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 1485 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 1486 P6_2_TCPWM0_LINE_COMPL0 = 22, /* Digital Active - tcpwm[0].line_compl[0] */ 1487 P6_2_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:0 */ 1488 1489 /* P6.3 */ 1490 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1491 P6_3_AMUXA = 4, /* Analog mux bus A */ 1492 P6_3_AMUXB = 5, /* Analog mux bus B */ 1493 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1494 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1495 P6_3_TCPWM1_LINE1 = 8, /* Digital Active - tcpwm[1].line[1]:0 */ 1496 P6_3_TCPWM1_LINE_COMPL257 = 9, /* Digital Active - tcpwm[1].line_compl[257]:0 */ 1497 P6_3_TCPWM1_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[3]:0 */ 1498 P6_3_TCPWM1_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[772]:0 */ 1499 P6_3_TCPWM1_LINE_COMPL524 = 16, /* Digital Active - tcpwm[1].line_compl[524]:0 */ 1500 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 1501 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 1502 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 1503 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 1504 P6_3_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:0 */ 1505 P6_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:0 */ 1506 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 1507 1508 /* P6.4 */ 1509 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1510 P6_4_AMUXA = 4, /* Analog mux bus A */ 1511 P6_4_AMUXB = 5, /* Analog mux bus B */ 1512 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1513 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1514 P6_4_TCPWM1_LINE258 = 8, /* Digital Active - tcpwm[1].line[258]:0 */ 1515 P6_4_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 1516 P6_4_TCPWM1_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[774]:0 */ 1517 P6_4_TCPWM1_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[4]:0 */ 1518 P6_4_TCPWM1_TR_ONE_CNT_IN1572 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1572]:0 */ 1519 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 1520 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 1521 P6_4_TCPWM0_TR_ONE_CNT_IN0 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[0] */ 1522 P6_4_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:0 */ 1523 P6_4_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:0 */ 1524 1525 /* P6.5 */ 1526 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1527 P6_5_AMUXA = 4, /* Analog mux bus A */ 1528 P6_5_AMUXB = 5, /* Analog mux bus B */ 1529 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1530 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1531 P6_5_TCPWM1_LINE2 = 8, /* Digital Active - tcpwm[1].line[2]:0 */ 1532 P6_5_TCPWM1_LINE_COMPL258 = 9, /* Digital Active - tcpwm[1].line_compl[258]:0 */ 1533 P6_5_TCPWM1_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[6]:0 */ 1534 P6_5_TCPWM1_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[775]:0 */ 1535 P6_5_TCPWM1_TR_ONE_CNT_IN1573 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1573]:0 */ 1536 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 1537 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 1538 P6_5_TCPWM0_TR_ONE_CNT_IN1 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1] */ 1539 P6_5_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:0 */ 1540 P6_5_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:0 */ 1541 1542 /* P6.6 */ 1543 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1544 P6_6_AMUXA = 4, /* Analog mux bus A */ 1545 P6_6_AMUXB = 5, /* Analog mux bus B */ 1546 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1547 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1548 P6_6_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:0 */ 1549 P6_6_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 1550 P6_6_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:0 */ 1551 P6_6_TCPWM1_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[7]:0 */ 1552 P6_6_SCB4_SPI_SELECT3 = 19, /* Digital Active - scb[4].spi_select3:0 */ 1553 P6_6_PERI_TR_IO_INPUT8 = 26, /* Digital Active - peri.tr_io_input[8]:0 */ 1554 1555 /* P6.7 */ 1556 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1557 P6_7_AMUXA = 4, /* Analog mux bus A */ 1558 P6_7_AMUXB = 5, /* Analog mux bus B */ 1559 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1560 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1561 P6_7_TCPWM1_LINE3 = 8, /* Digital Active - tcpwm[1].line[3]:0 */ 1562 P6_7_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:0 */ 1563 P6_7_TCPWM1_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[9]:0 */ 1564 P6_7_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:0 */ 1565 P6_7_PERI_TR_IO_INPUT9 = 26, /* Digital Active - peri.tr_io_input[9]:0 */ 1566 1567 /* P7.0 */ 1568 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1569 P7_0_AMUXA = 4, /* Analog mux bus A */ 1570 P7_0_AMUXB = 5, /* Analog mux bus B */ 1571 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1572 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1573 P7_0_TCPWM1_LINE260 = 8, /* Digital Active - tcpwm[1].line[260]:0 */ 1574 P7_0_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 1575 P7_0_TCPWM1_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[780]:0 */ 1576 P7_0_TCPWM1_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[10]:0 */ 1577 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 1578 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 1579 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 1580 P7_0_TCPWM0_LINE1 = 22, /* Digital Active - tcpwm[0].line[1] */ 1581 P7_0_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:0 */ 1582 P7_0_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:0 */ 1583 1584 /* P7.1 */ 1585 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1586 P7_1_AMUXA = 4, /* Analog mux bus A */ 1587 P7_1_AMUXB = 5, /* Analog mux bus B */ 1588 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1589 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1590 P7_1_TCPWM1_LINE15 = 8, /* Digital Active - tcpwm[1].line[15]:0 */ 1591 P7_1_TCPWM1_LINE_COMPL260 = 9, /* Digital Active - tcpwm[1].line_compl[260]:0 */ 1592 P7_1_TCPWM1_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[45]:0 */ 1593 P7_1_TCPWM1_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[781]:0 */ 1594 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 1595 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 1596 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 1597 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 1598 P7_1_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:0 */ 1599 P7_1_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:0 */ 1600 1601 /* P7.2 */ 1602 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1603 P7_2_AMUXA = 4, /* Analog mux bus A */ 1604 P7_2_AMUXB = 5, /* Analog mux bus B */ 1605 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1606 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1607 P7_2_TCPWM1_LINE261 = 8, /* Digital Active - tcpwm[1].line[261]:0 */ 1608 P7_2_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 1609 P7_2_TCPWM1_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[783]:0 */ 1610 P7_2_TCPWM1_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[46]:0 */ 1611 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 1612 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 1613 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 1614 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 1615 P7_2_TCPWM0_LINE_COMPL1 = 22, /* Digital Active - tcpwm[0].line_compl[1] */ 1616 P7_2_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:0 */ 1617 P7_2_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:0 */ 1618 1619 /* P7.3 */ 1620 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1621 P7_3_AMUXA = 4, /* Analog mux bus A */ 1622 P7_3_AMUXB = 5, /* Analog mux bus B */ 1623 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1624 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1625 P7_3_TCPWM1_LINE16 = 8, /* Digital Active - tcpwm[1].line[16]:0 */ 1626 P7_3_TCPWM1_LINE_COMPL261 = 9, /* Digital Active - tcpwm[1].line_compl[261]:0 */ 1627 P7_3_TCPWM1_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[48]:0 */ 1628 P7_3_TCPWM1_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[784]:0 */ 1629 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 1630 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 1631 P7_3_CANFD0_TTCAN_TX4 = 21, /* Digital Active - canfd[0].ttcan_tx[4]:0 */ 1632 P7_3_TCPWM0_TR_ONE_CNT_IN3 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[3] */ 1633 P7_3_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:0 */ 1634 P7_3_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:0 */ 1635 1636 /* P7.4 */ 1637 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1638 P7_4_AMUXA = 4, /* Analog mux bus A */ 1639 P7_4_AMUXB = 5, /* Analog mux bus B */ 1640 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1641 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1642 P7_4_TCPWM1_LINE262 = 8, /* Digital Active - tcpwm[1].line[262]:0 */ 1643 P7_4_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 1644 P7_4_TCPWM1_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[786]:0 */ 1645 P7_4_TCPWM1_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[49]:0 */ 1646 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 1647 P7_4_CANFD0_TTCAN_RX4 = 21, /* Digital Active - canfd[0].ttcan_rx[4]:0 */ 1648 P7_4_TCPWM0_TR_ONE_CNT_IN4 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[4] */ 1649 P7_4_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:0 */ 1650 P7_4_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:0 */ 1651 1652 /* P7.5 */ 1653 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1654 P7_5_AMUXA = 4, /* Analog mux bus A */ 1655 P7_5_AMUXB = 5, /* Analog mux bus B */ 1656 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1657 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1658 P7_5_TCPWM1_LINE17 = 8, /* Digital Active - tcpwm[1].line[17]:0 */ 1659 P7_5_TCPWM1_LINE_COMPL262 = 9, /* Digital Active - tcpwm[1].line_compl[262]:0 */ 1660 P7_5_TCPWM1_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[51]:0 */ 1661 P7_5_TCPWM1_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[787]:0 */ 1662 P7_5_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:0 */ 1663 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 1664 P7_5_TCPWM0_LINE514 = 22, /* Digital Active - tcpwm[0].line[514] */ 1665 P7_5_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:0 */ 1666 P7_5_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:0 */ 1667 1668 /* P7.6 */ 1669 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1670 P7_6_AMUXA = 4, /* Analog mux bus A */ 1671 P7_6_AMUXB = 5, /* Analog mux bus B */ 1672 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1673 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1674 P7_6_TCPWM1_LINE263 = 8, /* Digital Active - tcpwm[1].line[263]:0 */ 1675 P7_6_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 1676 P7_6_TCPWM1_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[789]:0 */ 1677 P7_6_TCPWM1_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[52]:0 */ 1678 P7_6_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:0 */ 1679 P7_6_PERI_TR_IO_INPUT16 = 26, /* Digital Active - peri.tr_io_input[16]:0 */ 1680 1681 /* P7.7 */ 1682 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1683 P7_7_AMUXA = 4, /* Analog mux bus A */ 1684 P7_7_AMUXB = 5, /* Analog mux bus B */ 1685 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1686 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1687 P7_7_TCPWM1_LINE18 = 8, /* Digital Active - tcpwm[1].line[18]:0 */ 1688 P7_7_TCPWM1_LINE_COMPL263 = 9, /* Digital Active - tcpwm[1].line_compl[263]:0 */ 1689 P7_7_TCPWM1_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[54]:0 */ 1690 P7_7_TCPWM1_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[790]:0 */ 1691 P7_7_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:0 */ 1692 P7_7_PERI_TR_IO_INPUT17 = 26, /* Digital Active - peri.tr_io_input[17]:0 */ 1693 1694 /* P8.0 */ 1695 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1696 P8_0_AMUXA = 4, /* Analog mux bus A */ 1697 P8_0_AMUXB = 5, /* Analog mux bus B */ 1698 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1699 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1700 P8_0_TCPWM1_LINE19 = 8, /* Digital Active - tcpwm[1].line[19]:0 */ 1701 P8_0_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ 1702 P8_0_TCPWM1_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[57]:0 */ 1703 P8_0_TCPWM1_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[55]:0 */ 1704 P8_0_TCPWM1_LINE520 = 16, /* Digital Active - tcpwm[1].line[520]:1 */ 1705 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 1706 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 1707 P8_0_TCPWM0_LINE_COMPL514 = 22, /* Digital Active - tcpwm[0].line_compl[514] */ 1708 P8_0_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:0 */ 1709 P8_0_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:0 */ 1710 1711 /* P8.1 */ 1712 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1713 P8_1_AMUXA = 4, /* Analog mux bus A */ 1714 P8_1_AMUXB = 5, /* Analog mux bus B */ 1715 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1716 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1717 P8_1_TCPWM1_LINE20 = 8, /* Digital Active - tcpwm[1].line[20]:0 */ 1718 P8_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ 1719 P8_1_TCPWM1_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[60]:0 */ 1720 P8_1_TCPWM1_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[58]:0 */ 1721 P8_1_TCPWM1_LINE_COMPL520 = 16, /* Digital Active - tcpwm[1].line_compl[520]:1 */ 1722 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 1723 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 1724 P8_1_TCPWM0_TR_ONE_CNT_IN1542 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1542] */ 1725 P8_1_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:0 */ 1726 P8_1_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:0 */ 1727 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 1728 1729 /* P8.2 */ 1730 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1731 P8_2_AMUXA = 4, /* Analog mux bus A */ 1732 P8_2_AMUXB = 5, /* Analog mux bus B */ 1733 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1734 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1735 P8_2_TCPWM1_LINE21 = 8, /* Digital Active - tcpwm[1].line[21]:0 */ 1736 P8_2_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 1737 P8_2_TCPWM1_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[63]:0 */ 1738 P8_2_TCPWM1_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[61]:0 */ 1739 P8_2_TCPWM1_TR_ONE_CNT_IN1560 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1560]:1 */ 1740 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 1741 P8_2_TCPWM0_TR_ONE_CNT_IN1543 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1543] */ 1742 P8_2_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:0 */ 1743 P8_2_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:0 */ 1744 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 1745 1746 /* P8.3 */ 1747 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1748 P8_3_AMUXA = 4, /* Analog mux bus A */ 1749 P8_3_AMUXB = 5, /* Analog mux bus B */ 1750 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1751 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1752 P8_3_TCPWM1_LINE22 = 8, /* Digital Active - tcpwm[1].line[22]:0 */ 1753 P8_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1754 P8_3_TCPWM1_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[66]:0 */ 1755 P8_3_TCPWM1_TR_ONE_CNT_IN64 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[64]:0 */ 1756 P8_3_TCPWM1_TR_ONE_CNT_IN1561 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1561]:1 */ 1757 P8_3_LIN0_LIN_RX16 = 20, /* Digital Active - lin[0].lin_rx[16]:1 */ 1758 P8_3_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:1 */ 1759 1760 /* P8.4 */ 1761 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1762 P8_4_AMUXA = 4, /* Analog mux bus A */ 1763 P8_4_AMUXB = 5, /* Analog mux bus B */ 1764 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1765 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1766 P8_4_TCPWM1_LINE23 = 8, /* Digital Active - tcpwm[1].line[23]:0 */ 1767 P8_4_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1768 P8_4_TCPWM1_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[69]:0 */ 1769 P8_4_TCPWM1_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[67]:0 */ 1770 P8_4_LIN0_LIN_TX16 = 20, /* Digital Active - lin[0].lin_tx[16]:1 */ 1771 P8_4_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:1 */ 1772 1773 /* P9.0 */ 1774 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1775 P9_0_AMUXA = 4, /* Analog mux bus A */ 1776 P9_0_AMUXB = 5, /* Analog mux bus B */ 1777 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1778 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1779 P9_0_TCPWM1_LINE24 = 8, /* Digital Active - tcpwm[1].line[24]:0 */ 1780 P9_0_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 1781 P9_0_TCPWM1_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[72]:0 */ 1782 P9_0_TCPWM1_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[70]:0 */ 1783 P9_0_TCPWM1_LINE521 = 16, /* Digital Active - tcpwm[1].line[521]:1 */ 1784 P9_0_LIN0_LIN_EN16 = 20, /* Digital Active - lin[0].lin_en[16]:1 */ 1785 1786 /* P9.1 */ 1787 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1788 P9_1_AMUXA = 4, /* Analog mux bus A */ 1789 P9_1_AMUXB = 5, /* Analog mux bus B */ 1790 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1791 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1792 P9_1_TCPWM1_LINE25 = 8, /* Digital Active - tcpwm[1].line[25]:0 */ 1793 P9_1_TCPWM1_LINE_COMPL24 = 9, /* Digital Active - tcpwm[1].line_compl[24]:0 */ 1794 P9_1_TCPWM1_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[75]:0 */ 1795 P9_1_TCPWM1_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[73]:0 */ 1796 P9_1_TCPWM1_LINE_COMPL521 = 16, /* Digital Active - tcpwm[1].line_compl[521]:1 */ 1797 P9_1_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:0 */ 1798 1799 /* P9.2 */ 1800 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1801 P9_2_AMUXA = 4, /* Analog mux bus A */ 1802 P9_2_AMUXB = 5, /* Analog mux bus B */ 1803 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1804 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1805 P9_2_TCPWM1_LINE26 = 8, /* Digital Active - tcpwm[1].line[26]:0 */ 1806 P9_2_TCPWM1_LINE_COMPL25 = 9, /* Digital Active - tcpwm[1].line_compl[25]:0 */ 1807 P9_2_TCPWM1_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[78]:0 */ 1808 P9_2_TCPWM1_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[76]:0 */ 1809 P9_2_TCPWM1_TR_ONE_CNT_IN1563 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1563]:1 */ 1810 P9_2_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:0 */ 1811 1812 /* P9.3 */ 1813 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1814 P9_3_AMUXA = 4, /* Analog mux bus A */ 1815 P9_3_AMUXB = 5, /* Analog mux bus B */ 1816 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1817 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1818 P9_3_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:0 */ 1819 P9_3_TCPWM1_LINE_COMPL26 = 9, /* Digital Active - tcpwm[1].line_compl[26]:0 */ 1820 P9_3_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:0 */ 1821 P9_3_TCPWM1_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[79]:0 */ 1822 P9_3_TCPWM1_TR_ONE_CNT_IN1564 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1564]:1 */ 1823 P9_3_LIN0_LIN_EN12 = 21, /* Digital Active - lin[0].lin_en[12]:0 */ 1824 1825 /* P10.0 */ 1826 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1827 P10_0_AMUXA = 4, /* Analog mux bus A */ 1828 P10_0_AMUXB = 5, /* Analog mux bus B */ 1829 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1830 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1831 P10_0_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:0 */ 1832 P10_0_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:0 */ 1833 P10_0_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:0 */ 1834 P10_0_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:0 */ 1835 P10_0_TCPWM1_LINE522 = 16, /* Digital Active - tcpwm[1].line[522]:1 */ 1836 P10_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:1 */ 1837 P10_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:1 */ 1838 P10_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:2 */ 1839 P10_0_PERI_TR_IO_INPUT18 = 26, /* Digital Active - peri.tr_io_input[18]:0 */ 1840 1841 /* P10.1 */ 1842 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1843 P10_1_AMUXA = 4, /* Analog mux bus A */ 1844 P10_1_AMUXB = 5, /* Analog mux bus B */ 1845 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1846 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1847 P10_1_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:0 */ 1848 P10_1_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:0 */ 1849 P10_1_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:0 */ 1850 P10_1_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:0 */ 1851 P10_1_TCPWM1_LINE_COMPL522 = 16, /* Digital Active - tcpwm[1].line_compl[522]:1 */ 1852 P10_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:1 */ 1853 P10_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:1 */ 1854 P10_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:1 */ 1855 P10_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:2 */ 1856 P10_1_PERI_TR_IO_INPUT19 = 26, /* Digital Active - peri.tr_io_input[19]:0 */ 1857 1858 /* P10.2 */ 1859 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1860 P10_2_AMUXA = 4, /* Analog mux bus A */ 1861 P10_2_AMUXB = 5, /* Analog mux bus B */ 1862 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1863 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1864 P10_2_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:0 */ 1865 P10_2_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:0 */ 1866 P10_2_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:0 */ 1867 P10_2_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:0 */ 1868 P10_2_TCPWM1_TR_ONE_CNT_IN1566 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1566]:1 */ 1869 P10_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:1 */ 1870 P10_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:1 */ 1871 P10_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:1 */ 1872 P10_2_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:1 */ 1873 P10_2_FLEXRAY0_RXDA = 26, /* Digital Active - flexray[0].rxda:0 */ 1874 1875 /* P10.3 */ 1876 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1877 P10_3_AMUXA = 4, /* Analog mux bus A */ 1878 P10_3_AMUXB = 5, /* Analog mux bus B */ 1879 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1880 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1881 P10_3_TCPWM1_LINE31 = 8, /* Digital Active - tcpwm[1].line[31]:0 */ 1882 P10_3_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:0 */ 1883 P10_3_TCPWM1_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[93]:0 */ 1884 P10_3_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:0 */ 1885 P10_3_TCPWM1_TR_ONE_CNT_IN1567 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1567]:1 */ 1886 P10_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:1 */ 1887 P10_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:1 */ 1888 P10_3_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:1 */ 1889 P10_3_FLEXRAY0_TXDA = 26, /* Digital Active - flexray[0].txda:0 */ 1890 1891 /* P10.4 */ 1892 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1893 P10_4_AMUXA = 4, /* Analog mux bus A */ 1894 P10_4_AMUXB = 5, /* Analog mux bus B */ 1895 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1896 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1897 P10_4_TCPWM1_LINE32 = 8, /* Digital Active - tcpwm[1].line[32]:0 */ 1898 P10_4_TCPWM1_LINE_COMPL31 = 9, /* Digital Active - tcpwm[1].line_compl[31]:0 */ 1899 P10_4_TCPWM1_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[96]:0 */ 1900 P10_4_TCPWM1_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[94]:0 */ 1901 P10_4_TCPWM1_LINE523 = 16, /* Digital Active - tcpwm[1].line[523]:1 */ 1902 P10_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:1 */ 1903 P10_4_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:1 */ 1904 P10_4_FLEXRAY0_TXENA_N = 26, /* Digital Active - flexray[0].txena_n:0 */ 1905 1906 /* P10.5 */ 1907 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1908 P10_5_AMUXA = 4, /* Analog mux bus A */ 1909 P10_5_AMUXB = 5, /* Analog mux bus B */ 1910 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1911 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1912 P10_5_TCPWM1_LINE33 = 8, /* Digital Active - tcpwm[1].line[33]:0 */ 1913 P10_5_TCPWM1_LINE_COMPL32 = 9, /* Digital Active - tcpwm[1].line_compl[32]:0 */ 1914 P10_5_TCPWM1_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[99]:0 */ 1915 P10_5_TCPWM1_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[97]:0 */ 1916 P10_5_TCPWM1_LINE_COMPL523 = 16, /* Digital Active - tcpwm[1].line_compl[523]:1 */ 1917 P10_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:1 */ 1918 P10_5_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:0 */ 1919 P10_5_FLEXRAY0_RXDB = 26, /* Digital Active - flexray[0].rxdb:0 */ 1920 1921 /* P10.6 */ 1922 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1923 P10_6_AMUXA = 4, /* Analog mux bus A */ 1924 P10_6_AMUXB = 5, /* Analog mux bus B */ 1925 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1926 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1927 P10_6_TCPWM1_LINE_COMPL33 = 9, /* Digital Active - tcpwm[1].line_compl[33]:0 */ 1928 P10_6_TCPWM1_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[100]:0 */ 1929 P10_6_TCPWM1_TR_ONE_CNT_IN1569 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1569]:1 */ 1930 P10_6_TCPWM1_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[1].tr_one_cnt_in[102]:0 */ 1931 P10_6_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:0 */ 1932 P10_6_TCPWM1_LINE34 = 22, /* Digital Active - tcpwm[1].line[34]:0 */ 1933 P10_6_FLEXRAY0_TXDB = 26, /* Digital Active - flexray[0].txdb:0 */ 1934 1935 /* P10.7 */ 1936 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1937 P10_7_AMUXA = 4, /* Analog mux bus A */ 1938 P10_7_AMUXB = 5, /* Analog mux bus B */ 1939 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1940 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1941 P10_7_TCPWM1_LINE35 = 8, /* Digital Active - tcpwm[1].line[35]:0 */ 1942 P10_7_TCPWM1_LINE_COMPL34 = 9, /* Digital Active - tcpwm[1].line_compl[34]:0 */ 1943 P10_7_TCPWM1_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[105]:0 */ 1944 P10_7_TCPWM1_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[103]:0 */ 1945 P10_7_TCPWM1_TR_ONE_CNT_IN1570 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1570]:1 */ 1946 P10_7_LIN0_LIN_EN13 = 21, /* Digital Active - lin[0].lin_en[13]:0 */ 1947 P10_7_FLEXRAY0_TXENB_N = 26, /* Digital Active - flexray[0].txenb_n:0 */ 1948 1949 /* P11.0 */ 1950 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1951 P11_0_AMUXA = 4, /* Analog mux bus A */ 1952 P11_0_AMUXB = 5, /* Analog mux bus B */ 1953 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1954 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1955 P11_0_TCPWM1_LINE61 = 8, /* Digital Active - tcpwm[1].line[61]:2 */ 1956 P11_0_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:2 */ 1957 P11_0_TCPWM1_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[183]:2 */ 1958 P11_0_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:2 */ 1959 P11_0_AUDIOSS0_MCLK = 25, /* Digital Active - audioss[0].mclk:0 */ 1960 1961 /* P11.1 */ 1962 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1963 P11_1_AMUXA = 4, /* Analog mux bus A */ 1964 P11_1_AMUXB = 5, /* Analog mux bus B */ 1965 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1966 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1967 P11_1_TCPWM1_LINE60 = 8, /* Digital Active - tcpwm[1].line[60]:2 */ 1968 P11_1_TCPWM1_LINE_COMPL61 = 9, /* Digital Active - tcpwm[1].line_compl[61]:2 */ 1969 P11_1_TCPWM1_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[180]:2 */ 1970 P11_1_TCPWM1_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[184]:2 */ 1971 P11_1_AUDIOSS0_TX_SCK = 25, /* Digital Active - audioss[0].tx_sck:0 */ 1972 1973 /* P11.2 */ 1974 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1975 P11_2_AMUXA = 4, /* Analog mux bus A */ 1976 P11_2_AMUXB = 5, /* Analog mux bus B */ 1977 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1978 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1979 P11_2_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:2 */ 1980 P11_2_TCPWM1_LINE_COMPL60 = 9, /* Digital Active - tcpwm[1].line_compl[60]:2 */ 1981 P11_2_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:2 */ 1982 P11_2_TCPWM1_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[181]:2 */ 1983 P11_2_AUDIOSS0_TX_WS = 25, /* Digital Active - audioss[0].tx_ws:0 */ 1984 1985 /* P12.0 */ 1986 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1987 P12_0_AMUXA = 4, /* Analog mux bus A */ 1988 P12_0_AMUXB = 5, /* Analog mux bus B */ 1989 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1990 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1991 P12_0_TCPWM1_LINE36 = 8, /* Digital Active - tcpwm[1].line[36]:0 */ 1992 P12_0_TCPWM1_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[108]:0 */ 1993 P12_0_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:0 */ 1994 P12_0_TCPWM1_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[1].tr_one_cnt_in[106]:0 */ 1995 P12_0_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:0 */ 1996 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 1997 P12_0_TCPWM0_LINE513 = 22, /* Digital Active - tcpwm[0].line[513] */ 1998 P12_0_TCPWM1_LINE_COMPL35 = 23, /* Digital Active - tcpwm[1].line_compl[35]:0 */ 1999 P12_0_AUDIOSS0_TX_SDO = 25, /* Digital Active - audioss[0].tx_sdo:0 */ 2000 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 2001 2002 /* P12.1 */ 2003 P12_1_GPIO = 0, /* GPIO controls 'out' */ 2004 P12_1_AMUXA = 4, /* Analog mux bus A */ 2005 P12_1_AMUXB = 5, /* Analog mux bus B */ 2006 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2007 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2008 P12_1_TCPWM1_LINE37 = 8, /* Digital Active - tcpwm[1].line[37]:0 */ 2009 P12_1_TCPWM1_LINE_COMPL36 = 9, /* Digital Active - tcpwm[1].line_compl[36]:0 */ 2010 P12_1_TCPWM1_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[111]:0 */ 2011 P12_1_TCPWM1_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[109]:0 */ 2012 P12_1_SCB8_UART_TX = 17, /* Digital Active - scb[8].uart_tx:0 */ 2013 P12_1_SCB8_I2C_SDA = 18, /* Digital Active - scb[8].i2c_sda:0 */ 2014 P12_1_SCB8_SPI_MOSI = 19, /* Digital Active - scb[8].spi_mosi:0 */ 2015 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 2016 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 2017 P12_1_TCPWM0_LINE_COMPL513 = 22, /* Digital Active - tcpwm[0].line_compl[513] */ 2018 P12_1_AUDIOSS0_CLK_I2S_IF = 25, /* Digital Active - audioss[0].clk_i2s_if:0 */ 2019 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 2020 2021 /* P12.2 */ 2022 P12_2_GPIO = 0, /* GPIO controls 'out' */ 2023 P12_2_AMUXA = 4, /* Analog mux bus A */ 2024 P12_2_AMUXB = 5, /* Analog mux bus B */ 2025 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2026 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2027 P12_2_TCPWM1_LINE38 = 8, /* Digital Active - tcpwm[1].line[38]:0 */ 2028 P12_2_TCPWM1_LINE_COMPL37 = 9, /* Digital Active - tcpwm[1].line_compl[37]:0 */ 2029 P12_2_TCPWM1_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[114]:0 */ 2030 P12_2_TCPWM1_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[112]:0 */ 2031 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 2032 P12_2_SCB8_UART_RTS = 17, /* Digital Active - scb[8].uart_rts:0 */ 2033 P12_2_SCB8_I2C_SCL = 18, /* Digital Active - scb[8].i2c_scl:0 */ 2034 P12_2_SCB8_SPI_CLK = 19, /* Digital Active - scb[8].spi_clk:0 */ 2035 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 2036 P12_2_TCPWM0_TR_ONE_CNT_IN1539 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539] */ 2037 P12_2_AUDIOSS0_RX_SCK = 25, /* Digital Active - audioss[0].rx_sck:0 */ 2038 2039 /* P12.3 */ 2040 P12_3_GPIO = 0, /* GPIO controls 'out' */ 2041 P12_3_AMUXA = 4, /* Analog mux bus A */ 2042 P12_3_AMUXB = 5, /* Analog mux bus B */ 2043 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2044 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2045 P12_3_TCPWM1_LINE39 = 8, /* Digital Active - tcpwm[1].line[39]:0 */ 2046 P12_3_TCPWM1_LINE_COMPL38 = 9, /* Digital Active - tcpwm[1].line_compl[38]:0 */ 2047 P12_3_TCPWM1_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[117]:0 */ 2048 P12_3_TCPWM1_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[115]:0 */ 2049 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 2050 P12_3_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:0 */ 2051 P12_3_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:0 */ 2052 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 2053 P12_3_TCPWM0_TR_ONE_CNT_IN1540 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540] */ 2054 P12_3_AUDIOSS0_RX_WS = 25, /* Digital Active - audioss[0].rx_ws:0 */ 2055 2056 /* P12.4 */ 2057 P12_4_GPIO = 0, /* GPIO controls 'out' */ 2058 P12_4_AMUXA = 4, /* Analog mux bus A */ 2059 P12_4_AMUXB = 5, /* Analog mux bus B */ 2060 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2061 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2062 P12_4_TCPWM1_LINE40 = 8, /* Digital Active - tcpwm[1].line[40]:0 */ 2063 P12_4_TCPWM1_LINE_COMPL39 = 9, /* Digital Active - tcpwm[1].line_compl[39]:0 */ 2064 P12_4_TCPWM1_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[120]:0 */ 2065 P12_4_TCPWM1_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[118]:0 */ 2066 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 2067 P12_4_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:0 */ 2068 P12_4_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:2 */ 2069 P12_4_TCPWM0_TR_ONE_CNT_IN7 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[7] */ 2070 P12_4_AUDIOSS0_RX_SDI = 25, /* Digital Active - audioss[0].rx_sdi:0 */ 2071 2072 /* P12.5 */ 2073 P12_5_GPIO = 0, /* GPIO controls 'out' */ 2074 P12_5_AMUXA = 4, /* Analog mux bus A */ 2075 P12_5_AMUXB = 5, /* Analog mux bus B */ 2076 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2077 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2078 P12_5_TCPWM1_LINE41 = 8, /* Digital Active - tcpwm[1].line[41]:0 */ 2079 P12_5_TCPWM1_LINE_COMPL40 = 9, /* Digital Active - tcpwm[1].line_compl[40]:0 */ 2080 P12_5_TCPWM1_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[123]:0 */ 2081 P12_5_TCPWM1_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[121]:0 */ 2082 P12_5_PASS0_SAR_EXT_MUX_SEL5 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[5] */ 2083 P12_5_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:2 */ 2084 2085 /* P12.6 */ 2086 P12_6_GPIO = 0, /* GPIO controls 'out' */ 2087 P12_6_AMUXA = 4, /* Analog mux bus A */ 2088 P12_6_AMUXB = 5, /* Analog mux bus B */ 2089 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2090 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2091 P12_6_TCPWM1_LINE42 = 8, /* Digital Active - tcpwm[1].line[42]:0 */ 2092 P12_6_TCPWM1_LINE_COMPL41 = 9, /* Digital Active - tcpwm[1].line_compl[41]:0 */ 2093 P12_6_TCPWM1_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[126]:0 */ 2094 P12_6_TCPWM1_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[124]:0 */ 2095 2096 /* P12.7 */ 2097 P12_7_GPIO = 0, /* GPIO controls 'out' */ 2098 P12_7_AMUXA = 4, /* Analog mux bus A */ 2099 P12_7_AMUXB = 5, /* Analog mux bus B */ 2100 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2101 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2102 P12_7_TCPWM1_LINE43 = 8, /* Digital Active - tcpwm[1].line[43]:0 */ 2103 P12_7_TCPWM1_LINE_COMPL42 = 9, /* Digital Active - tcpwm[1].line_compl[42]:0 */ 2104 P12_7_TCPWM1_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[129]:0 */ 2105 P12_7_TCPWM1_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[127]:0 */ 2106 2107 /* P13.0 */ 2108 P13_0_GPIO = 0, /* GPIO controls 'out' */ 2109 P13_0_AMUXA = 4, /* Analog mux bus A */ 2110 P13_0_AMUXB = 5, /* Analog mux bus B */ 2111 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2112 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2113 P13_0_TCPWM1_LINE264 = 8, /* Digital Active - tcpwm[1].line[264]:0 */ 2114 P13_0_TCPWM1_LINE_COMPL43 = 9, /* Digital Active - tcpwm[1].line_compl[43]:0 */ 2115 P13_0_TCPWM1_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[792]:0 */ 2116 P13_0_TCPWM1_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[130]:0 */ 2117 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 2118 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 2119 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 2120 P13_0_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:0 */ 2121 P13_0_TCPWM0_TR_ONE_CNT_IN6 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[6] */ 2122 P13_0_AUDIOSS1_MCLK = 25, /* Digital Active - audioss[1].mclk:0 */ 2123 2124 /* P13.1 */ 2125 P13_1_GPIO = 0, /* GPIO controls 'out' */ 2126 P13_1_AMUXA = 4, /* Analog mux bus A */ 2127 P13_1_AMUXB = 5, /* Analog mux bus B */ 2128 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2129 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2130 P13_1_TCPWM1_LINE44 = 8, /* Digital Active - tcpwm[1].line[44]:0 */ 2131 P13_1_TCPWM1_LINE_COMPL264 = 9, /* Digital Active - tcpwm[1].line_compl[264]:0 */ 2132 P13_1_TCPWM1_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[132]:0 */ 2133 P13_1_TCPWM1_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[793]:0 */ 2134 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 2135 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 2136 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 2137 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 2138 P13_1_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:0 */ 2139 P13_1_TCPWM0_LINE_COMPL2 = 22, /* Digital Active - tcpwm[0].line_compl[2] */ 2140 P13_1_AUDIOSS1_TX_SCK = 25, /* Digital Active - audioss[1].tx_sck:0 */ 2141 2142 /* P13.2 */ 2143 P13_2_GPIO = 0, /* GPIO controls 'out' */ 2144 P13_2_AMUXA = 4, /* Analog mux bus A */ 2145 P13_2_AMUXB = 5, /* Analog mux bus B */ 2146 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2147 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2148 P13_2_TCPWM1_LINE265 = 8, /* Digital Active - tcpwm[1].line[265]:0 */ 2149 P13_2_TCPWM1_LINE_COMPL44 = 9, /* Digital Active - tcpwm[1].line_compl[44]:0 */ 2150 P13_2_TCPWM1_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[795]:0 */ 2151 P13_2_TCPWM1_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[133]:0 */ 2152 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 2153 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 2154 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 2155 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 2156 P13_2_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:0 */ 2157 P13_2_TCPWM0_LINE2 = 22, /* Digital Active - tcpwm[0].line[2] */ 2158 P13_2_AUDIOSS1_TX_WS = 25, /* Digital Active - audioss[1].tx_ws:0 */ 2159 2160 /* P13.3 */ 2161 P13_3_GPIO = 0, /* GPIO controls 'out' */ 2162 P13_3_AMUXA = 4, /* Analog mux bus A */ 2163 P13_3_AMUXB = 5, /* Analog mux bus B */ 2164 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2165 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2166 P13_3_TCPWM1_LINE45 = 8, /* Digital Active - tcpwm[1].line[45]:0 */ 2167 P13_3_TCPWM1_LINE_COMPL265 = 9, /* Digital Active - tcpwm[1].line_compl[265]:0 */ 2168 P13_3_TCPWM1_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[135]:0 */ 2169 P13_3_TCPWM1_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[796]:0 */ 2170 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 2171 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 2172 P13_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:2 */ 2173 P13_3_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:0 */ 2174 P13_3_AUDIOSS1_TX_SDO = 25, /* Digital Active - audioss[1].tx_sdo:0 */ 2175 2176 /* P13.4 */ 2177 P13_4_GPIO = 0, /* GPIO controls 'out' */ 2178 P13_4_AMUXA = 4, /* Analog mux bus A */ 2179 P13_4_AMUXB = 5, /* Analog mux bus B */ 2180 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2181 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2182 P13_4_TCPWM1_LINE266 = 8, /* Digital Active - tcpwm[1].line[266]:0 */ 2183 P13_4_TCPWM1_LINE_COMPL45 = 9, /* Digital Active - tcpwm[1].line_compl[45]:0 */ 2184 P13_4_TCPWM1_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[798]:0 */ 2185 P13_4_TCPWM1_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[136]:0 */ 2186 P13_4_TCPWM1_LINE516 = 16, /* Digital Active - tcpwm[1].line[516]:1 */ 2187 P13_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:2 */ 2188 P13_4_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:0 */ 2189 P13_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:0 */ 2190 P13_4_AUDIOSS1_CLK_I2S_IF = 25, /* Digital Active - audioss[1].clk_i2s_if:0 */ 2191 2192 /* P13.5 */ 2193 P13_5_GPIO = 0, /* GPIO controls 'out' */ 2194 P13_5_AMUXA = 4, /* Analog mux bus A */ 2195 P13_5_AMUXB = 5, /* Analog mux bus B */ 2196 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2197 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2198 P13_5_TCPWM1_LINE46 = 8, /* Digital Active - tcpwm[1].line[46]:0 */ 2199 P13_5_TCPWM1_LINE_COMPL266 = 9, /* Digital Active - tcpwm[1].line_compl[266]:0 */ 2200 P13_5_TCPWM1_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[138]:0 */ 2201 P13_5_TCPWM1_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[799]:0 */ 2202 P13_5_TCPWM1_LINE_COMPL516 = 16, /* Digital Active - tcpwm[1].line_compl[516]:1 */ 2203 P13_5_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:0 */ 2204 P13_5_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:0 */ 2205 P13_5_AUDIOSS1_RX_SCK = 25, /* Digital Active - audioss[1].rx_sck:0 */ 2206 2207 /* P13.6 */ 2208 P13_6_GPIO = 0, /* GPIO controls 'out' */ 2209 P13_6_AMUXA = 4, /* Analog mux bus A */ 2210 P13_6_AMUXB = 5, /* Analog mux bus B */ 2211 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2212 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2213 P13_6_TCPWM1_LINE267 = 8, /* Digital Active - tcpwm[1].line[267]:0 */ 2214 P13_6_TCPWM1_LINE_COMPL46 = 9, /* Digital Active - tcpwm[1].line_compl[46]:0 */ 2215 P13_6_TCPWM1_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[801]:0 */ 2216 P13_6_TCPWM1_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[139]:0 */ 2217 P13_6_TCPWM1_LINE517 = 16, /* Digital Active - tcpwm[1].line[517]:1 */ 2218 P13_6_SCB3_SPI_SELECT3 = 21, /* Digital Active - scb[3].spi_select3:0 */ 2219 P13_6_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:0 */ 2220 P13_6_AUDIOSS1_RX_WS = 25, /* Digital Active - audioss[1].rx_ws:0 */ 2221 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 2222 2223 /* P13.7 */ 2224 P13_7_GPIO = 0, /* GPIO controls 'out' */ 2225 P13_7_AMUXA = 4, /* Analog mux bus A */ 2226 P13_7_AMUXB = 5, /* Analog mux bus B */ 2227 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2228 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2229 P13_7_TCPWM1_LINE47 = 8, /* Digital Active - tcpwm[1].line[47]:0 */ 2230 P13_7_TCPWM1_LINE_COMPL267 = 9, /* Digital Active - tcpwm[1].line_compl[267]:0 */ 2231 P13_7_TCPWM1_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[141]:0 */ 2232 P13_7_TCPWM1_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[802]:0 */ 2233 P13_7_TCPWM1_LINE_COMPL517 = 16, /* Digital Active - tcpwm[1].line_compl[517]:1 */ 2234 P13_7_AUDIOSS1_RX_SDI = 25, /* Digital Active - audioss[1].rx_sdi:0 */ 2235 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 2236 2237 /* P14.0 */ 2238 P14_0_GPIO = 0, /* GPIO controls 'out' */ 2239 P14_0_AMUXA = 4, /* Analog mux bus A */ 2240 P14_0_AMUXB = 5, /* Analog mux bus B */ 2241 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2242 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2243 P14_0_TCPWM1_LINE48 = 8, /* Digital Active - tcpwm[1].line[48]:0 */ 2244 P14_0_TCPWM1_LINE_COMPL47 = 9, /* Digital Active - tcpwm[1].line_compl[47]:0 */ 2245 P14_0_TCPWM1_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[144]:0 */ 2246 P14_0_TCPWM1_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[142]:0 */ 2247 P14_0_TCPWM1_LINE518 = 16, /* Digital Active - tcpwm[1].line[518]:1 */ 2248 P14_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:0 */ 2249 P14_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:0 */ 2250 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 2251 P14_0_TCPWM0_LINE257 = 22, /* Digital Active - tcpwm[0].line[257] */ 2252 P14_0_AUDIOSS2_MCLK = 25, /* Digital Active - audioss[2].mclk:0 */ 2253 2254 /* P14.1 */ 2255 P14_1_GPIO = 0, /* GPIO controls 'out' */ 2256 P14_1_AMUXA = 4, /* Analog mux bus A */ 2257 P14_1_AMUXB = 5, /* Analog mux bus B */ 2258 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2259 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2260 P14_1_TCPWM1_LINE49 = 8, /* Digital Active - tcpwm[1].line[49]:0 */ 2261 P14_1_TCPWM1_LINE_COMPL48 = 9, /* Digital Active - tcpwm[1].line_compl[48]:0 */ 2262 P14_1_TCPWM1_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[147]:0 */ 2263 P14_1_TCPWM1_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[145]:0 */ 2264 P14_1_TCPWM1_LINE_COMPL518 = 16, /* Digital Active - tcpwm[1].line_compl[518]:1 */ 2265 P14_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:0 */ 2266 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 2267 P14_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:0 */ 2268 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 2269 P14_1_TCPWM0_LINE_COMPL257 = 22, /* Digital Active - tcpwm[0].line_compl[257] */ 2270 P14_1_AUDIOSS2_TX_SCK = 25, /* Digital Active - audioss[2].tx_sck:0 */ 2271 2272 /* P14.2 */ 2273 P14_2_GPIO = 0, /* GPIO controls 'out' */ 2274 P14_2_AMUXA = 4, /* Analog mux bus A */ 2275 P14_2_AMUXB = 5, /* Analog mux bus B */ 2276 P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2277 P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2278 P14_2_TCPWM1_LINE50 = 8, /* Digital Active - tcpwm[1].line[50]:0 */ 2279 P14_2_TCPWM1_LINE_COMPL49 = 9, /* Digital Active - tcpwm[1].line_compl[49]:0 */ 2280 P14_2_TCPWM1_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[150]:0 */ 2281 P14_2_TCPWM1_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[148]:0 */ 2282 P14_2_TCPWM1_LINE519 = 16, /* Digital Active - tcpwm[1].line[519]:1 */ 2283 P14_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:0 */ 2284 P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ 2285 P14_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:0 */ 2286 P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ 2287 P14_2_TCPWM0_TR_ONE_CNT_IN771 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[771] */ 2288 2289 /* P14.3 */ 2290 P14_3_GPIO = 0, /* GPIO controls 'out' */ 2291 P14_3_AMUXA = 4, /* Analog mux bus A */ 2292 P14_3_AMUXB = 5, /* Analog mux bus B */ 2293 P14_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2294 P14_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2295 P14_3_TCPWM1_LINE51 = 8, /* Digital Active - tcpwm[1].line[51]:0 */ 2296 P14_3_TCPWM1_LINE_COMPL50 = 9, /* Digital Active - tcpwm[1].line_compl[50]:0 */ 2297 P14_3_TCPWM1_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[153]:0 */ 2298 P14_3_TCPWM1_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[151]:0 */ 2299 P14_3_TCPWM1_LINE_COMPL519 = 16, /* Digital Active - tcpwm[1].line_compl[519]:1 */ 2300 P14_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:0 */ 2301 P14_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:0 */ 2302 P14_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:1 */ 2303 P14_3_TCPWM0_TR_ONE_CNT_IN772 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[772] */ 2304 2305 /* P14.4 */ 2306 P14_4_GPIO = 0, /* GPIO controls 'out' */ 2307 P14_4_AMUXA = 4, /* Analog mux bus A */ 2308 P14_4_AMUXB = 5, /* Analog mux bus B */ 2309 P14_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2310 P14_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2311 P14_4_TCPWM1_LINE52 = 8, /* Digital Active - tcpwm[1].line[52]:0 */ 2312 P14_4_TCPWM1_LINE_COMPL51 = 9, /* Digital Active - tcpwm[1].line_compl[51]:0 */ 2313 P14_4_TCPWM1_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[156]:0 */ 2314 P14_4_TCPWM1_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[154]:0 */ 2315 P14_4_TCPWM1_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1548]:1 */ 2316 P14_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:0 */ 2317 P14_4_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:1 */ 2318 P14_4_AUDIOSS2_TX_WS = 25, /* Digital Active - audioss[2].tx_ws:0 */ 2319 2320 /* P14.5 */ 2321 P14_5_GPIO = 0, /* GPIO controls 'out' */ 2322 P14_5_AMUXA = 4, /* Analog mux bus A */ 2323 P14_5_AMUXB = 5, /* Analog mux bus B */ 2324 P14_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2325 P14_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2326 P14_5_TCPWM1_LINE53 = 8, /* Digital Active - tcpwm[1].line[53]:0 */ 2327 P14_5_TCPWM1_LINE_COMPL52 = 9, /* Digital Active - tcpwm[1].line_compl[52]:0 */ 2328 P14_5_TCPWM1_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[159]:0 */ 2329 P14_5_TCPWM1_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[157]:0 */ 2330 P14_5_TCPWM1_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1549]:1 */ 2331 P14_5_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:0 */ 2332 P14_5_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:0 */ 2333 P14_5_AUDIOSS2_TX_SDO = 25, /* Digital Active - audioss[2].tx_sdo:0 */ 2334 2335 /* P14.6 */ 2336 P14_6_GPIO = 0, /* GPIO controls 'out' */ 2337 P14_6_AMUXA = 4, /* Analog mux bus A */ 2338 P14_6_AMUXB = 5, /* Analog mux bus B */ 2339 P14_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2340 P14_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2341 P14_6_TCPWM1_LINE54 = 8, /* Digital Active - tcpwm[1].line[54]:0 */ 2342 P14_6_TCPWM1_LINE_COMPL53 = 9, /* Digital Active - tcpwm[1].line_compl[53]:0 */ 2343 P14_6_TCPWM1_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[162]:0 */ 2344 P14_6_TCPWM1_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[160]:0 */ 2345 P14_6_TCPWM1_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1551]:1 */ 2346 P14_6_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:0 */ 2347 P14_6_PERI_TR_IO_INPUT24 = 26, /* Digital Active - peri.tr_io_input[24]:0 */ 2348 2349 /* P14.7 */ 2350 P14_7_GPIO = 0, /* GPIO controls 'out' */ 2351 P14_7_AMUXA = 4, /* Analog mux bus A */ 2352 P14_7_AMUXB = 5, /* Analog mux bus B */ 2353 P14_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2354 P14_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2355 P14_7_TCPWM1_LINE55 = 8, /* Digital Active - tcpwm[1].line[55]:0 */ 2356 P14_7_TCPWM1_LINE_COMPL54 = 9, /* Digital Active - tcpwm[1].line_compl[54]:0 */ 2357 P14_7_TCPWM1_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[165]:0 */ 2358 P14_7_TCPWM1_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[163]:0 */ 2359 P14_7_TCPWM1_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1552]:1 */ 2360 P14_7_LIN0_LIN_EN14 = 18, /* Digital Active - lin[0].lin_en[14]:0 */ 2361 P14_7_PERI_TR_IO_INPUT25 = 26, /* Digital Active - peri.tr_io_input[25]:0 */ 2362 2363 /* P15.0 */ 2364 P15_0_GPIO = 0, /* GPIO controls 'out' */ 2365 P15_0_AMUXA = 4, /* Analog mux bus A */ 2366 P15_0_AMUXB = 5, /* Analog mux bus B */ 2367 P15_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2368 P15_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2369 P15_0_TCPWM1_LINE56 = 8, /* Digital Active - tcpwm[1].line[56]:0 */ 2370 P15_0_TCPWM1_LINE_COMPL55 = 9, /* Digital Active - tcpwm[1].line_compl[55]:0 */ 2371 P15_0_TCPWM1_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[168]:0 */ 2372 P15_0_TCPWM1_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[166]:0 */ 2373 P15_0_TCPWM1_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1554]:1 */ 2374 P15_0_SCB9_UART_RX = 17, /* Digital Active - scb[9].uart_rx:0 */ 2375 P15_0_SCB9_SPI_MISO = 19, /* Digital Active - scb[9].spi_miso:0 */ 2376 P15_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:1 */ 2377 P15_0_AUDIOSS2_CLK_I2S_IF = 25, /* Digital Active - audioss[2].clk_i2s_if:0 */ 2378 2379 /* P15.1 */ 2380 P15_1_GPIO = 0, /* GPIO controls 'out' */ 2381 P15_1_AMUXA = 4, /* Analog mux bus A */ 2382 P15_1_AMUXB = 5, /* Analog mux bus B */ 2383 P15_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2384 P15_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2385 P15_1_TCPWM1_LINE57 = 8, /* Digital Active - tcpwm[1].line[57]:0 */ 2386 P15_1_TCPWM1_LINE_COMPL56 = 9, /* Digital Active - tcpwm[1].line_compl[56]:0 */ 2387 P15_1_TCPWM1_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[171]:0 */ 2388 P15_1_TCPWM1_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[169]:0 */ 2389 P15_1_TCPWM1_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1555]:1 */ 2390 P15_1_SCB9_UART_TX = 17, /* Digital Active - scb[9].uart_tx:0 */ 2391 P15_1_SCB9_I2C_SDA = 18, /* Digital Active - scb[9].i2c_sda:0 */ 2392 P15_1_SCB9_SPI_MOSI = 19, /* Digital Active - scb[9].spi_mosi:0 */ 2393 P15_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:1 */ 2394 P15_1_AUDIOSS2_RX_SCK = 25, /* Digital Active - audioss[2].rx_sck:0 */ 2395 2396 /* P15.2 */ 2397 P15_2_GPIO = 0, /* GPIO controls 'out' */ 2398 P15_2_AMUXA = 4, /* Analog mux bus A */ 2399 P15_2_AMUXB = 5, /* Analog mux bus B */ 2400 P15_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2401 P15_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2402 P15_2_TCPWM1_LINE58 = 8, /* Digital Active - tcpwm[1].line[58]:0 */ 2403 P15_2_TCPWM1_LINE_COMPL57 = 9, /* Digital Active - tcpwm[1].line_compl[57]:0 */ 2404 P15_2_TCPWM1_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[174]:0 */ 2405 P15_2_TCPWM1_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[172]:0 */ 2406 P15_2_TCPWM1_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1557]:1 */ 2407 P15_2_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:0 */ 2408 P15_2_SCB9_I2C_SCL = 18, /* Digital Active - scb[9].i2c_scl:0 */ 2409 P15_2_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:0 */ 2410 P15_2_AUDIOSS2_RX_WS = 25, /* Digital Active - audioss[2].rx_ws:0 */ 2411 2412 /* P15.3 */ 2413 P15_3_GPIO = 0, /* GPIO controls 'out' */ 2414 P15_3_AMUXA = 4, /* Analog mux bus A */ 2415 P15_3_AMUXB = 5, /* Analog mux bus B */ 2416 P15_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2417 P15_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2418 P15_3_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:0 */ 2419 P15_3_TCPWM1_LINE_COMPL58 = 9, /* Digital Active - tcpwm[1].line_compl[58]:0 */ 2420 P15_3_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:0 */ 2421 P15_3_TCPWM1_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[175]:0 */ 2422 P15_3_TCPWM1_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1558]:1 */ 2423 P15_3_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:0 */ 2424 P15_3_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:0 */ 2425 P15_3_AUDIOSS2_RX_SDI = 25, /* Digital Active - audioss[2].rx_sdi:0 */ 2426 2427 /* P16.3 */ 2428 P16_3_GPIO = 0, /* GPIO controls 'out' */ 2429 P16_3_AMUXA = 4, /* Analog mux bus A */ 2430 P16_3_AMUXB = 5, /* Analog mux bus B */ 2431 P16_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2432 P16_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2433 P16_3_TCPWM1_LINE62 = 8, /* Digital Active - tcpwm[1].line[62]:1 */ 2434 P16_3_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:0 */ 2435 P16_3_TCPWM1_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[186]:1 */ 2436 P16_3_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:0 */ 2437 P16_3_TCPWM1_LINE_COMPL513 = 16, /* Digital Active - tcpwm[1].line_compl[513]:1 */ 2438 2439 /* P17.0 */ 2440 P17_0_GPIO = 0, /* GPIO controls 'out' */ 2441 P17_0_AMUXA = 4, /* Analog mux bus A */ 2442 P17_0_AMUXB = 5, /* Analog mux bus B */ 2443 P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2444 P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2445 P17_0_TCPWM1_LINE61 = 8, /* Digital Active - tcpwm[1].line[61]:1 */ 2446 P17_0_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:1 */ 2447 P17_0_TCPWM1_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[183]:1 */ 2448 P17_0_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:1 */ 2449 P17_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:2 */ 2450 P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ 2451 2452 /* P17.1 */ 2453 P17_1_GPIO = 0, /* GPIO controls 'out' */ 2454 P17_1_AMUXA = 4, /* Analog mux bus A */ 2455 P17_1_AMUXB = 5, /* Analog mux bus B */ 2456 P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2457 P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2458 P17_1_TCPWM1_LINE60 = 8, /* Digital Active - tcpwm[1].line[60]:1 */ 2459 P17_1_TCPWM1_LINE_COMPL61 = 9, /* Digital Active - tcpwm[1].line_compl[61]:1 */ 2460 P17_1_TCPWM1_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[180]:1 */ 2461 P17_1_TCPWM1_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[184]:1 */ 2462 P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ 2463 P17_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:2 */ 2464 P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ 2465 2466 /* P17.2 */ 2467 P17_2_GPIO = 0, /* GPIO controls 'out' */ 2468 P17_2_AMUXA = 4, /* Analog mux bus A */ 2469 P17_2_AMUXB = 5, /* Analog mux bus B */ 2470 P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2471 P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2472 P17_2_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:1 */ 2473 P17_2_TCPWM1_LINE_COMPL60 = 9, /* Digital Active - tcpwm[1].line_compl[60]:1 */ 2474 P17_2_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:1 */ 2475 P17_2_TCPWM1_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[181]:1 */ 2476 P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ 2477 P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ 2478 P17_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:2 */ 2479 2480 /* P17.3 */ 2481 P17_3_GPIO = 0, /* GPIO controls 'out' */ 2482 P17_3_AMUXA = 4, /* Analog mux bus A */ 2483 P17_3_AMUXB = 5, /* Analog mux bus B */ 2484 P17_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2485 P17_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2486 P17_3_TCPWM1_LINE58 = 8, /* Digital Active - tcpwm[1].line[58]:1 */ 2487 P17_3_TCPWM1_LINE_COMPL59 = 9, /* Digital Active - tcpwm[1].line_compl[59]:1 */ 2488 P17_3_TCPWM1_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[174]:1 */ 2489 P17_3_TCPWM1_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[178]:1 */ 2490 P17_3_TCPWM1_LINE515 = 16, /* Digital Active - tcpwm[1].line[515]:1 */ 2491 P17_3_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:1 */ 2492 P17_3_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:1 */ 2493 P17_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:1 */ 2494 P17_3_PERI_TR_IO_INPUT26 = 26, /* Digital Active - peri.tr_io_input[26]:0 */ 2495 2496 /* P17.4 */ 2497 P17_4_GPIO = 0, /* GPIO controls 'out' */ 2498 P17_4_AMUXA = 4, /* Analog mux bus A */ 2499 P17_4_AMUXB = 5, /* Analog mux bus B */ 2500 P17_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2501 P17_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2502 P17_4_TCPWM1_LINE57 = 8, /* Digital Active - tcpwm[1].line[57]:1 */ 2503 P17_4_TCPWM1_LINE_COMPL58 = 9, /* Digital Active - tcpwm[1].line_compl[58]:1 */ 2504 P17_4_TCPWM1_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[171]:1 */ 2505 P17_4_TCPWM1_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[175]:1 */ 2506 P17_4_TCPWM1_LINE_COMPL515 = 16, /* Digital Active - tcpwm[1].line_compl[515]:1 */ 2507 P17_4_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:1 */ 2508 P17_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:1 */ 2509 P17_4_PERI_TR_IO_INPUT27 = 26, /* Digital Active - peri.tr_io_input[27]:0 */ 2510 2511 /* P17.5 */ 2512 P17_5_GPIO = 0, /* GPIO controls 'out' */ 2513 P17_5_AMUXA = 4, /* Analog mux bus A */ 2514 P17_5_AMUXB = 5, /* Analog mux bus B */ 2515 P17_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2516 P17_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2517 P17_5_TCPWM1_LINE56 = 8, /* Digital Active - tcpwm[1].line[56]:1 */ 2518 P17_5_TCPWM1_LINE_COMPL57 = 9, /* Digital Active - tcpwm[1].line_compl[57]:1 */ 2519 P17_5_TCPWM1_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[168]:1 */ 2520 P17_5_TCPWM1_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[172]:1 */ 2521 P17_5_TCPWM1_LINE514 = 16, /* Digital Active - tcpwm[1].line[514]:1 */ 2522 P17_5_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:0 */ 2523 P17_5_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:1 */ 2524 2525 /* P17.6 */ 2526 P17_6_GPIO = 0, /* GPIO controls 'out' */ 2527 P17_6_AMUXA = 4, /* Analog mux bus A */ 2528 P17_6_AMUXB = 5, /* Analog mux bus B */ 2529 P17_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2530 P17_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2531 P17_6_TCPWM1_LINE260 = 8, /* Digital Active - tcpwm[1].line[260]:1 */ 2532 P17_6_TCPWM1_LINE_COMPL56 = 9, /* Digital Active - tcpwm[1].line_compl[56]:1 */ 2533 P17_6_TCPWM1_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[780]:1 */ 2534 P17_6_TCPWM1_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[169]:1 */ 2535 P17_6_TCPWM1_LINE_COMPL514 = 16, /* Digital Active - tcpwm[1].line_compl[514]:1 */ 2536 P17_6_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:0 */ 2537 P17_6_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:1 */ 2538 2539 /* P17.7 */ 2540 P17_7_GPIO = 0, /* GPIO controls 'out' */ 2541 P17_7_AMUXA = 4, /* Analog mux bus A */ 2542 P17_7_AMUXB = 5, /* Analog mux bus B */ 2543 P17_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2544 P17_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2545 P17_7_TCPWM1_LINE261 = 8, /* Digital Active - tcpwm[1].line[261]:1 */ 2546 P17_7_TCPWM1_LINE_COMPL260 = 9, /* Digital Active - tcpwm[1].line_compl[260]:1 */ 2547 P17_7_TCPWM1_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[783]:1 */ 2548 P17_7_TCPWM1_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[781]:1 */ 2549 P17_7_LIN0_LIN_EN15 = 18, /* Digital Active - lin[0].lin_en[15]:0 */ 2550 P17_7_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:1 */ 2551 2552 /* P18.0 */ 2553 P18_0_GPIO = 0, /* GPIO controls 'out' */ 2554 P18_0_AMUXA = 4, /* Analog mux bus A */ 2555 P18_0_AMUXB = 5, /* Analog mux bus B */ 2556 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2557 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2558 P18_0_TCPWM1_LINE262 = 8, /* Digital Active - tcpwm[1].line[262]:1 */ 2559 P18_0_TCPWM1_LINE_COMPL261 = 9, /* Digital Active - tcpwm[1].line_compl[261]:1 */ 2560 P18_0_TCPWM1_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[786]:1 */ 2561 P18_0_TCPWM1_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[784]:1 */ 2562 P18_0_TCPWM1_LINE512 = 16, /* Digital Active - tcpwm[1].line[512]:0 */ 2563 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 2564 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 2565 P18_0_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:1 */ 2566 P18_0_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk:0 */ 2567 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 2568 2569 /* P18.1 */ 2570 P18_1_GPIO = 0, /* GPIO controls 'out' */ 2571 P18_1_AMUXA = 4, /* Analog mux bus A */ 2572 P18_1_AMUXB = 5, /* Analog mux bus B */ 2573 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2574 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2575 P18_1_TCPWM1_LINE263 = 8, /* Digital Active - tcpwm[1].line[263]:1 */ 2576 P18_1_TCPWM1_LINE_COMPL262 = 9, /* Digital Active - tcpwm[1].line_compl[262]:1 */ 2577 P18_1_TCPWM1_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[789]:1 */ 2578 P18_1_TCPWM1_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[787]:1 */ 2579 P18_1_TCPWM1_LINE_COMPL512 = 16, /* Digital Active - tcpwm[1].line_compl[512]:0 */ 2580 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 2581 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 2582 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 2583 P18_1_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:1 */ 2584 P18_1_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl:0 */ 2585 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 2586 2587 /* P18.2 */ 2588 P18_2_GPIO = 0, /* GPIO controls 'out' */ 2589 P18_2_AMUXA = 4, /* Analog mux bus A */ 2590 P18_2_AMUXB = 5, /* Analog mux bus B */ 2591 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2592 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2593 P18_2_TCPWM1_LINE55 = 8, /* Digital Active - tcpwm[1].line[55]:1 */ 2594 P18_2_TCPWM1_LINE_COMPL263 = 9, /* Digital Active - tcpwm[1].line_compl[263]:1 */ 2595 P18_2_TCPWM1_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[165]:1 */ 2596 P18_2_TCPWM1_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[790]:1 */ 2597 P18_2_TCPWM1_LINE513 = 16, /* Digital Active - tcpwm[1].line[513]:0 */ 2598 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 2599 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 2600 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 2601 P18_2_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:1 */ 2602 P18_2_ETH0_TX_ER = 24, /* Digital Active - eth[0].tx_er:0 */ 2603 2604 /* P18.3 */ 2605 P18_3_GPIO = 0, /* GPIO controls 'out' */ 2606 P18_3_AMUXA = 4, /* Analog mux bus A */ 2607 P18_3_AMUXB = 5, /* Analog mux bus B */ 2608 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2609 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2610 P18_3_TCPWM1_LINE54 = 8, /* Digital Active - tcpwm[1].line[54]:1 */ 2611 P18_3_TCPWM1_LINE_COMPL55 = 9, /* Digital Active - tcpwm[1].line_compl[55]:1 */ 2612 P18_3_TCPWM1_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[162]:1 */ 2613 P18_3_TCPWM1_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[166]:1 */ 2614 P18_3_TCPWM1_LINE_COMPL513 = 16, /* Digital Active - tcpwm[1].line_compl[513]:0 */ 2615 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 2616 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 2617 P18_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:2 */ 2618 P18_3_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk:0 */ 2619 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 2620 2621 /* P18.4 */ 2622 P18_4_GPIO = 0, /* GPIO controls 'out' */ 2623 P18_4_AMUXA = 4, /* Analog mux bus A */ 2624 P18_4_AMUXB = 5, /* Analog mux bus B */ 2625 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2626 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2627 P18_4_TCPWM1_LINE53 = 8, /* Digital Active - tcpwm[1].line[53]:1 */ 2628 P18_4_TCPWM1_LINE_COMPL54 = 9, /* Digital Active - tcpwm[1].line_compl[54]:1 */ 2629 P18_4_TCPWM1_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[159]:1 */ 2630 P18_4_TCPWM1_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[163]:1 */ 2631 P18_4_TCPWM1_LINE514 = 16, /* Digital Active - tcpwm[1].line[514]:0 */ 2632 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 2633 P18_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:2 */ 2634 P18_4_TCPWM0_LINE258 = 22, /* Digital Active - tcpwm[0].line[258] */ 2635 P18_4_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0]:0 */ 2636 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 2637 2638 /* P18.5 */ 2639 P18_5_GPIO = 0, /* GPIO controls 'out' */ 2640 P18_5_AMUXA = 4, /* Analog mux bus A */ 2641 P18_5_AMUXB = 5, /* Analog mux bus B */ 2642 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2643 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2644 P18_5_TCPWM1_LINE52 = 8, /* Digital Active - tcpwm[1].line[52]:1 */ 2645 P18_5_TCPWM1_LINE_COMPL53 = 9, /* Digital Active - tcpwm[1].line_compl[53]:1 */ 2646 P18_5_TCPWM1_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[156]:1 */ 2647 P18_5_TCPWM1_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[160]:1 */ 2648 P18_5_TCPWM1_LINE_COMPL514 = 16, /* Digital Active - tcpwm[1].line_compl[514]:0 */ 2649 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 2650 P18_5_TCPWM0_LINE_COMPL258 = 22, /* Digital Active - tcpwm[0].line_compl[258] */ 2651 P18_5_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1]:0 */ 2652 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 2653 2654 /* P18.6 */ 2655 P18_6_GPIO = 0, /* GPIO controls 'out' */ 2656 P18_6_AMUXA = 4, /* Analog mux bus A */ 2657 P18_6_AMUXB = 5, /* Analog mux bus B */ 2658 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2659 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2660 P18_6_TCPWM1_LINE51 = 8, /* Digital Active - tcpwm[1].line[51]:1 */ 2661 P18_6_TCPWM1_LINE_COMPL52 = 9, /* Digital Active - tcpwm[1].line_compl[52]:1 */ 2662 P18_6_TCPWM1_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[153]:1 */ 2663 P18_6_TCPWM1_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[157]:1 */ 2664 P18_6_TCPWM1_LINE515 = 16, /* Digital Active - tcpwm[1].line[515]:0 */ 2665 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 2666 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 2667 P18_6_TCPWM0_TR_ONE_CNT_IN774 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[774] */ 2668 P18_6_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2]:0 */ 2669 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 2670 2671 /* P18.7 */ 2672 P18_7_GPIO = 0, /* GPIO controls 'out' */ 2673 P18_7_AMUXA = 4, /* Analog mux bus A */ 2674 P18_7_AMUXB = 5, /* Analog mux bus B */ 2675 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2676 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2677 P18_7_TCPWM1_LINE50 = 8, /* Digital Active - tcpwm[1].line[50]:1 */ 2678 P18_7_TCPWM1_LINE_COMPL51 = 9, /* Digital Active - tcpwm[1].line_compl[51]:1 */ 2679 P18_7_TCPWM1_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[150]:1 */ 2680 P18_7_TCPWM1_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[154]:1 */ 2681 P18_7_TCPWM1_LINE_COMPL515 = 16, /* Digital Active - tcpwm[1].line_compl[515]:0 */ 2682 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 2683 P18_7_TCPWM0_TR_ONE_CNT_IN775 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[775] */ 2684 P18_7_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3]:0 */ 2685 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 2686 2687 /* P19.0 */ 2688 P19_0_GPIO = 0, /* GPIO controls 'out' */ 2689 P19_0_AMUXA = 4, /* Analog mux bus A */ 2690 P19_0_AMUXB = 5, /* Analog mux bus B */ 2691 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2692 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2693 P19_0_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:2 */ 2694 P19_0_TCPWM1_LINE_COMPL50 = 9, /* Digital Active - tcpwm[1].line_compl[50]:1 */ 2695 P19_0_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:2 */ 2696 P19_0_TCPWM1_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[151]:1 */ 2697 P19_0_TCPWM1_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1536]:0 */ 2698 P19_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:1 */ 2699 P19_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:1 */ 2700 P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ 2701 P19_0_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0]:0 */ 2702 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 2703 2704 /* P19.1 */ 2705 P19_1_GPIO = 0, /* GPIO controls 'out' */ 2706 P19_1_AMUXA = 4, /* Analog mux bus A */ 2707 P19_1_AMUXB = 5, /* Analog mux bus B */ 2708 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2709 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2710 P19_1_TCPWM1_LINE26 = 8, /* Digital Active - tcpwm[1].line[26]:1 */ 2711 P19_1_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:2 */ 2712 P19_1_TCPWM1_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[78]:1 */ 2713 P19_1_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:2 */ 2714 P19_1_TCPWM1_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1537]:0 */ 2715 P19_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:1 */ 2716 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 2717 P19_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:1 */ 2718 P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ 2719 P19_1_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1]:0 */ 2720 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 2721 2722 /* P19.2 */ 2723 P19_2_GPIO = 0, /* GPIO controls 'out' */ 2724 P19_2_AMUXA = 4, /* Analog mux bus A */ 2725 P19_2_AMUXB = 5, /* Analog mux bus B */ 2726 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2727 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2728 P19_2_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:2 */ 2729 P19_2_TCPWM1_LINE_COMPL26 = 9, /* Digital Active - tcpwm[1].line_compl[26]:1 */ 2730 P19_2_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:2 */ 2731 P19_2_TCPWM1_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[79]:1 */ 2732 P19_2_TCPWM1_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1539]:0 */ 2733 P19_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:1 */ 2734 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 2735 P19_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:1 */ 2736 P19_2_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2]:0 */ 2737 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 2738 2739 /* P19.3 */ 2740 P19_3_GPIO = 0, /* GPIO controls 'out' */ 2741 P19_3_AMUXA = 4, /* Analog mux bus A */ 2742 P19_3_AMUXB = 5, /* Analog mux bus B */ 2743 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2744 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2745 P19_3_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:2 */ 2746 P19_3_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:2 */ 2747 P19_3_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:2 */ 2748 P19_3_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:2 */ 2749 P19_3_TCPWM1_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1540]:0 */ 2750 P19_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:1 */ 2751 P19_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:1 */ 2752 P19_3_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3]:0 */ 2753 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 2754 2755 /* P19.4 */ 2756 P19_4_GPIO = 0, /* GPIO controls 'out' */ 2757 P19_4_AMUXA = 4, /* Analog mux bus A */ 2758 P19_4_AMUXB = 5, /* Analog mux bus B */ 2759 P19_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2760 P19_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2761 P19_4_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:2 */ 2762 P19_4_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:2 */ 2763 P19_4_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:2 */ 2764 P19_4_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:2 */ 2765 P19_4_TCPWM1_TR_ONE_CNT_IN1542 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1542]:0 */ 2766 P19_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:1 */ 2767 2768 /* P20.0 */ 2769 P20_0_GPIO = 0, /* GPIO controls 'out' */ 2770 P20_0_AMUXA = 4, /* Analog mux bus A */ 2771 P20_0_AMUXB = 5, /* Analog mux bus B */ 2772 P20_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2773 P20_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2774 P20_0_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:2 */ 2775 P20_0_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:2 */ 2776 P20_0_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:2 */ 2777 P20_0_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:2 */ 2778 P20_0_TCPWM1_TR_ONE_CNT_IN1543 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1543]:0 */ 2779 P20_0_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:1 */ 2780 P20_0_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:0 */ 2781 2782 /* P20.1 */ 2783 P20_1_GPIO = 0, /* GPIO controls 'out' */ 2784 P20_1_AMUXA = 4, /* Analog mux bus A */ 2785 P20_1_AMUXB = 5, /* Analog mux bus B */ 2786 P20_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2787 P20_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2788 P20_1_TCPWM1_LINE49 = 8, /* Digital Active - tcpwm[1].line[49]:1 */ 2789 P20_1_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:2 */ 2790 P20_1_TCPWM1_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[147]:1 */ 2791 P20_1_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:2 */ 2792 P20_1_TCPWM1_TR_ONE_CNT_IN1545 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1545]:0 */ 2793 P20_1_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:0 */ 2794 2795 /* P20.2 */ 2796 P20_2_GPIO = 0, /* GPIO controls 'out' */ 2797 P20_2_AMUXA = 4, /* Analog mux bus A */ 2798 P20_2_AMUXB = 5, /* Analog mux bus B */ 2799 P20_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2800 P20_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2801 P20_2_TCPWM1_LINE48 = 8, /* Digital Active - tcpwm[1].line[48]:1 */ 2802 P20_2_TCPWM1_LINE_COMPL49 = 9, /* Digital Active - tcpwm[1].line_compl[49]:1 */ 2803 P20_2_TCPWM1_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[144]:1 */ 2804 P20_2_TCPWM1_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[148]:1 */ 2805 P20_2_TCPWM1_TR_ONE_CNT_IN1546 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1546]:0 */ 2806 P20_2_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:0 */ 2807 2808 /* P20.3 */ 2809 P20_3_GPIO = 0, /* GPIO controls 'out' */ 2810 P20_3_AMUXA = 4, /* Analog mux bus A */ 2811 P20_3_AMUXB = 5, /* Analog mux bus B */ 2812 P20_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2813 P20_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2814 P20_3_TCPWM1_LINE47 = 8, /* Digital Active - tcpwm[1].line[47]:1 */ 2815 P20_3_TCPWM1_LINE_COMPL48 = 9, /* Digital Active - tcpwm[1].line_compl[48]:1 */ 2816 P20_3_TCPWM1_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[141]:1 */ 2817 P20_3_TCPWM1_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[145]:1 */ 2818 P20_3_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:1 */ 2819 P20_3_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:1 */ 2820 P20_3_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:1 */ 2821 2822 /* P20.4 */ 2823 P20_4_GPIO = 0, /* GPIO controls 'out' */ 2824 P20_4_AMUXA = 4, /* Analog mux bus A */ 2825 P20_4_AMUXB = 5, /* Analog mux bus B */ 2826 P20_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2827 P20_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2828 P20_4_TCPWM1_LINE46 = 8, /* Digital Active - tcpwm[1].line[46]:1 */ 2829 P20_4_TCPWM1_LINE_COMPL47 = 9, /* Digital Active - tcpwm[1].line_compl[47]:1 */ 2830 P20_4_TCPWM1_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[138]:1 */ 2831 P20_4_TCPWM1_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[142]:1 */ 2832 P20_4_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:1 */ 2833 P20_4_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:1 */ 2834 P20_4_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:1 */ 2835 P20_4_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:1 */ 2836 2837 /* P20.5 */ 2838 P20_5_GPIO = 0, /* GPIO controls 'out' */ 2839 P20_5_AMUXA = 4, /* Analog mux bus A */ 2840 P20_5_AMUXB = 5, /* Analog mux bus B */ 2841 P20_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2842 P20_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2843 P20_5_TCPWM1_LINE45 = 8, /* Digital Active - tcpwm[1].line[45]:1 */ 2844 P20_5_TCPWM1_LINE_COMPL46 = 9, /* Digital Active - tcpwm[1].line_compl[46]:1 */ 2845 P20_5_TCPWM1_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[135]:1 */ 2846 P20_5_TCPWM1_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[139]:1 */ 2847 P20_5_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:1 */ 2848 P20_5_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:1 */ 2849 P20_5_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:1 */ 2850 2851 /* P20.6 */ 2852 P20_6_GPIO = 0, /* GPIO controls 'out' */ 2853 P20_6_AMUXA = 4, /* Analog mux bus A */ 2854 P20_6_AMUXB = 5, /* Analog mux bus B */ 2855 P20_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2856 P20_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2857 P20_6_TCPWM1_LINE44 = 8, /* Digital Active - tcpwm[1].line[44]:1 */ 2858 P20_6_TCPWM1_LINE_COMPL45 = 9, /* Digital Active - tcpwm[1].line_compl[45]:1 */ 2859 P20_6_TCPWM1_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[132]:1 */ 2860 P20_6_TCPWM1_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[136]:1 */ 2861 P20_6_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:1 */ 2862 P20_6_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:1 */ 2863 P20_6_CANFD1_TTCAN_TX4 = 21, /* Digital Active - canfd[1].ttcan_tx[4]:0 */ 2864 2865 /* P20.7 */ 2866 P20_7_GPIO = 0, /* GPIO controls 'out' */ 2867 P20_7_AMUXA = 4, /* Analog mux bus A */ 2868 P20_7_AMUXB = 5, /* Analog mux bus B */ 2869 P20_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2870 P20_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2871 P20_7_TCPWM1_LINE43 = 8, /* Digital Active - tcpwm[1].line[43]:1 */ 2872 P20_7_TCPWM1_LINE_COMPL44 = 9, /* Digital Active - tcpwm[1].line_compl[44]:1 */ 2873 P20_7_TCPWM1_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[129]:1 */ 2874 P20_7_TCPWM1_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[133]:1 */ 2875 P20_7_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:1 */ 2876 P20_7_CANFD1_TTCAN_RX4 = 21, /* Digital Active - canfd[1].ttcan_rx[4]:0 */ 2877 2878 /* P21.0 */ 2879 P21_0_GPIO = 0, /* GPIO controls 'out' */ 2880 P21_0_AMUXA = 4, /* Analog mux bus A */ 2881 P21_0_AMUXB = 5, /* Analog mux bus B */ 2882 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2883 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2884 P21_0_TCPWM1_LINE42 = 8, /* Digital Active - tcpwm[1].line[42]:1 */ 2885 P21_0_TCPWM1_LINE_COMPL43 = 9, /* Digital Active - tcpwm[1].line_compl[43]:1 */ 2886 P21_0_TCPWM1_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[126]:1 */ 2887 P21_0_TCPWM1_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[130]:1 */ 2888 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 2889 2890 /* P21.1 */ 2891 P21_1_GPIO = 0, /* GPIO controls 'out' */ 2892 P21_1_AMUXA = 4, /* Analog mux bus A */ 2893 P21_1_AMUXB = 5, /* Analog mux bus B */ 2894 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2895 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2896 P21_1_TCPWM1_LINE41 = 8, /* Digital Active - tcpwm[1].line[41]:1 */ 2897 P21_1_TCPWM1_LINE_COMPL42 = 9, /* Digital Active - tcpwm[1].line_compl[42]:1 */ 2898 P21_1_TCPWM1_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[123]:1 */ 2899 P21_1_TCPWM1_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[127]:1 */ 2900 2901 /* P21.2 */ 2902 P21_2_GPIO = 0, /* GPIO controls 'out' */ 2903 P21_2_AMUXA = 4, /* Analog mux bus A */ 2904 P21_2_AMUXB = 5, /* Analog mux bus B */ 2905 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2906 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2907 P21_2_TCPWM1_LINE40 = 8, /* Digital Active - tcpwm[1].line[40]:1 */ 2908 P21_2_TCPWM1_LINE_COMPL41 = 9, /* Digital Active - tcpwm[1].line_compl[41]:1 */ 2909 P21_2_TCPWM1_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[120]:1 */ 2910 P21_2_TCPWM1_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[124]:1 */ 2911 P21_2_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:0 */ 2912 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 2913 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 2914 2915 /* P21.3 */ 2916 P21_3_GPIO = 0, /* GPIO controls 'out' */ 2917 P21_3_AMUXA = 4, /* Analog mux bus A */ 2918 P21_3_AMUXB = 5, /* Analog mux bus B */ 2919 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2920 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2921 P21_3_TCPWM1_LINE39 = 8, /* Digital Active - tcpwm[1].line[39]:1 */ 2922 P21_3_TCPWM1_LINE_COMPL40 = 9, /* Digital Active - tcpwm[1].line_compl[40]:1 */ 2923 P21_3_TCPWM1_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[117]:1 */ 2924 P21_3_TCPWM1_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[121]:1 */ 2925 2926 /* P21.4 */ 2927 P21_4_GPIO = 0, /* GPIO controls 'out' */ 2928 P21_4_AMUXA = 4, /* Analog mux bus A */ 2929 P21_4_AMUXB = 5, /* Analog mux bus B */ 2930 P21_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2931 P21_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2932 P21_4_TCPWM1_LINE38 = 8, /* Digital Active - tcpwm[1].line[38]:1 */ 2933 P21_4_TCPWM1_LINE_COMPL39 = 9, /* Digital Active - tcpwm[1].line_compl[39]:1 */ 2934 P21_4_TCPWM1_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[114]:1 */ 2935 P21_4_TCPWM1_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[118]:1 */ 2936 2937 /* P21.5 */ 2938 P21_5_GPIO = 0, /* GPIO controls 'out' */ 2939 P21_5_AMUXA = 4, /* Analog mux bus A */ 2940 P21_5_AMUXB = 5, /* Analog mux bus B */ 2941 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2942 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2943 P21_5_TCPWM1_LINE37 = 8, /* Digital Active - tcpwm[1].line[37]:1 */ 2944 P21_5_TCPWM1_LINE_COMPL38 = 9, /* Digital Active - tcpwm[1].line_compl[38]:1 */ 2945 P21_5_TCPWM1_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[111]:1 */ 2946 P21_5_TCPWM1_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[115]:1 */ 2947 P21_5_TCPWM1_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[1].tr_one_cnt_in[106]:1 */ 2948 P21_5_TCPWM1_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[1].tr_one_cnt_in[102]:1 */ 2949 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 2950 P21_5_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 2951 P21_5_TCPWM1_LINE34 = 22, /* Digital Active - tcpwm[1].line[34]:1 */ 2952 P21_5_TCPWM1_LINE_COMPL35 = 23, /* Digital Active - tcpwm[1].line_compl[35]:1 */ 2953 P21_5_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl:0 */ 2954 P21_5_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 2955 2956 /* P21.6 */ 2957 P21_6_GPIO = 0, /* GPIO controls 'out' */ 2958 P21_6_AMUXA = 4, /* Analog mux bus A */ 2959 P21_6_AMUXB = 5, /* Analog mux bus B */ 2960 P21_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2961 P21_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2962 P21_6_TCPWM1_LINE36 = 8, /* Digital Active - tcpwm[1].line[36]:1 */ 2963 P21_6_TCPWM1_LINE_COMPL37 = 9, /* Digital Active - tcpwm[1].line_compl[37]:1 */ 2964 P21_6_TCPWM1_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[108]:1 */ 2965 P21_6_TCPWM1_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[112]:1 */ 2966 P21_6_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:1 */ 2967 P21_6_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:1 */ 2968 P21_6_CPUSS_CLK_FM_PUMP = 26, /* Digital Active - cpuss.clk_fm_pump */ 2969 2970 /* P21.7 */ 2971 P21_7_GPIO = 0, /* GPIO controls 'out' */ 2972 P21_7_AMUXA = 4, /* Analog mux bus A */ 2973 P21_7_AMUXB = 5, /* Analog mux bus B */ 2974 P21_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2975 P21_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2976 P21_7_TCPWM1_LINE35 = 8, /* Digital Active - tcpwm[1].line[35]:1 */ 2977 P21_7_TCPWM1_LINE_COMPL36 = 9, /* Digital Active - tcpwm[1].line_compl[36]:1 */ 2978 P21_7_TCPWM1_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[105]:1 */ 2979 P21_7_TCPWM1_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[109]:1 */ 2980 P21_7_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 2981 P21_7_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 2982 P21_7_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:1 */ 2983 P21_7_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:1 */ 2984 P21_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:1 */ 2985 P21_7_SRSS_CAL_WAVE = 29, /* Digital Deep Sleep - srss.cal_wave:0 */ 2986 2987 /* P22.1 */ 2988 P22_1_GPIO = 0, /* GPIO controls 'out' */ 2989 P22_1_AMUXA = 4, /* Analog mux bus A */ 2990 P22_1_AMUXB = 5, /* Analog mux bus B */ 2991 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2992 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2993 P22_1_TCPWM1_LINE33 = 8, /* Digital Active - tcpwm[1].line[33]:1 */ 2994 P22_1_TCPWM1_LINE_COMPL34 = 9, /* Digital Active - tcpwm[1].line_compl[34]:1 */ 2995 P22_1_TCPWM1_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[99]:1 */ 2996 P22_1_TCPWM1_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[103]:1 */ 2997 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 2998 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 2999 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 3000 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 3001 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 3002 3003 /* P22.2 */ 3004 P22_2_GPIO = 0, /* GPIO controls 'out' */ 3005 P22_2_AMUXA = 4, /* Analog mux bus A */ 3006 P22_2_AMUXB = 5, /* Analog mux bus B */ 3007 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3008 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3009 P22_2_TCPWM1_LINE32 = 8, /* Digital Active - tcpwm[1].line[32]:1 */ 3010 P22_2_TCPWM1_LINE_COMPL33 = 9, /* Digital Active - tcpwm[1].line_compl[33]:1 */ 3011 P22_2_TCPWM1_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[96]:1 */ 3012 P22_2_TCPWM1_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[100]:1 */ 3013 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 3014 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 3015 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 3016 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 3017 3018 /* P22.3 */ 3019 P22_3_GPIO = 0, /* GPIO controls 'out' */ 3020 P22_3_AMUXA = 4, /* Analog mux bus A */ 3021 P22_3_AMUXB = 5, /* Analog mux bus B */ 3022 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3023 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3024 P22_3_TCPWM1_LINE31 = 8, /* Digital Active - tcpwm[1].line[31]:1 */ 3025 P22_3_TCPWM1_LINE_COMPL32 = 9, /* Digital Active - tcpwm[1].line_compl[32]:1 */ 3026 P22_3_TCPWM1_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[93]:1 */ 3027 P22_3_TCPWM1_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[97]:1 */ 3028 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 3029 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 3030 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 3031 3032 /* P22.4 */ 3033 P22_4_GPIO = 0, /* GPIO controls 'out' */ 3034 P22_4_AMUXA = 4, /* Analog mux bus A */ 3035 P22_4_AMUXB = 5, /* Analog mux bus B */ 3036 P22_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3037 P22_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3038 P22_4_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:1 */ 3039 P22_4_TCPWM1_LINE_COMPL31 = 9, /* Digital Active - tcpwm[1].line_compl[31]:1 */ 3040 P22_4_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:1 */ 3041 P22_4_TCPWM1_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[94]:1 */ 3042 P22_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:1 */ 3043 P22_4_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:1 */ 3044 3045 /* P22.5 */ 3046 P22_5_GPIO = 0, /* GPIO controls 'out' */ 3047 P22_5_AMUXA = 4, /* Analog mux bus A */ 3048 P22_5_AMUXB = 5, /* Analog mux bus B */ 3049 P22_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3050 P22_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3051 P22_5_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:1 */ 3052 P22_5_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:1 */ 3053 P22_5_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:1 */ 3054 P22_5_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:1 */ 3055 P22_5_TCPWM1_LINE520 = 16, /* Digital Active - tcpwm[1].line[520]:0 */ 3056 P22_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:1 */ 3057 P22_5_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:1 */ 3058 3059 /* P22.6 */ 3060 P22_6_GPIO = 0, /* GPIO controls 'out' */ 3061 P22_6_AMUXA = 4, /* Analog mux bus A */ 3062 P22_6_AMUXB = 5, /* Analog mux bus B */ 3063 P22_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3064 P22_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3065 P22_6_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:1 */ 3066 P22_6_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:1 */ 3067 P22_6_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:1 */ 3068 P22_6_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:1 */ 3069 P22_6_TCPWM1_LINE_COMPL520 = 16, /* Digital Active - tcpwm[1].line_compl[520]:0 */ 3070 P22_6_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:1 */ 3071 3072 /* P22.7 */ 3073 P22_7_GPIO = 0, /* GPIO controls 'out' */ 3074 P22_7_AMUXA = 4, /* Analog mux bus A */ 3075 P22_7_AMUXB = 5, /* Analog mux bus B */ 3076 P22_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3077 P22_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3078 P22_7_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:1 */ 3079 P22_7_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:1 */ 3080 P22_7_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:1 */ 3081 P22_7_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:1 */ 3082 P22_7_TCPWM1_TR_ONE_CNT_IN1560 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1560]:0 */ 3083 P22_7_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:1 */ 3084 P22_7_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:1 */ 3085 3086 /* P23.0 */ 3087 P23_0_GPIO = 0, /* GPIO controls 'out' */ 3088 P23_0_AMUXA = 4, /* Analog mux bus A */ 3089 P23_0_AMUXB = 5, /* Analog mux bus B */ 3090 P23_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3091 P23_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3092 P23_0_TCPWM1_LINE264 = 8, /* Digital Active - tcpwm[1].line[264]:1 */ 3093 P23_0_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:1 */ 3094 P23_0_TCPWM1_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[792]:1 */ 3095 P23_0_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:1 */ 3096 P23_0_TCPWM1_TR_ONE_CNT_IN1561 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1561]:0 */ 3097 P23_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:1 */ 3098 P23_0_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:1 */ 3099 P23_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:1 */ 3100 P23_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:1 */ 3101 P23_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:1 */ 3102 3103 /* P23.1 */ 3104 P23_1_GPIO = 0, /* GPIO controls 'out' */ 3105 P23_1_AMUXA = 4, /* Analog mux bus A */ 3106 P23_1_AMUXB = 5, /* Analog mux bus B */ 3107 P23_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3108 P23_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3109 P23_1_TCPWM1_LINE265 = 8, /* Digital Active - tcpwm[1].line[265]:1 */ 3110 P23_1_TCPWM1_LINE_COMPL264 = 9, /* Digital Active - tcpwm[1].line_compl[264]:1 */ 3111 P23_1_TCPWM1_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[795]:1 */ 3112 P23_1_TCPWM1_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[793]:1 */ 3113 P23_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:1 */ 3114 P23_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:1 */ 3115 P23_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:1 */ 3116 P23_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:1 */ 3117 P23_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:1 */ 3118 3119 /* P23.2 */ 3120 P23_2_GPIO = 0, /* GPIO controls 'out' */ 3121 P23_2_AMUXA = 4, /* Analog mux bus A */ 3122 P23_2_AMUXB = 5, /* Analog mux bus B */ 3123 P23_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3124 P23_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3125 P23_2_TCPWM1_LINE266 = 8, /* Digital Active - tcpwm[1].line[266]:1 */ 3126 P23_2_TCPWM1_LINE_COMPL265 = 9, /* Digital Active - tcpwm[1].line_compl[265]:1 */ 3127 P23_2_TCPWM1_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[798]:1 */ 3128 P23_2_TCPWM1_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[796]:1 */ 3129 P23_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:1 */ 3130 P23_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:1 */ 3131 P23_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:1 */ 3132 P23_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:2 */ 3133 P23_2_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:1 */ 3134 3135 /* P23.3 */ 3136 P23_3_GPIO = 0, /* GPIO controls 'out' */ 3137 P23_3_AMUXA = 4, /* Analog mux bus A */ 3138 P23_3_AMUXB = 5, /* Analog mux bus B */ 3139 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3140 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3141 P23_3_TCPWM1_LINE267 = 8, /* Digital Active - tcpwm[1].line[267]:1 */ 3142 P23_3_TCPWM1_LINE_COMPL266 = 9, /* Digital Active - tcpwm[1].line_compl[266]:1 */ 3143 P23_3_TCPWM1_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[801]:1 */ 3144 P23_3_TCPWM1_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[799]:1 */ 3145 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 3146 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 3147 P23_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:2 */ 3148 P23_3_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk:0 */ 3149 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 3150 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 3151 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 3152 3153 /* P23.4 */ 3154 P23_4_GPIO = 0, /* GPIO controls 'out' */ 3155 P23_4_AMUXA = 4, /* Analog mux bus A */ 3156 P23_4_AMUXB = 5, /* Analog mux bus B */ 3157 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3158 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3159 P23_4_TCPWM1_LINE25 = 8, /* Digital Active - tcpwm[1].line[25]:1 */ 3160 P23_4_TCPWM1_LINE_COMPL267 = 9, /* Digital Active - tcpwm[1].line_compl[267]:1 */ 3161 P23_4_TCPWM1_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[75]:1 */ 3162 P23_4_TCPWM1_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[802]:1 */ 3163 P23_4_TCPWM1_LINE521 = 16, /* Digital Active - tcpwm[1].line[521]:0 */ 3164 P23_4_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:2 */ 3165 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 3166 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 3167 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 3168 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 3169 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 3170 3171 /* P23.5 */ 3172 P23_5_GPIO = 0, /* GPIO controls 'out' */ 3173 P23_5_AMUXA = 4, /* Analog mux bus A */ 3174 P23_5_AMUXB = 5, /* Analog mux bus B */ 3175 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3176 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3177 P23_5_TCPWM1_LINE24 = 8, /* Digital Active - tcpwm[1].line[24]:1 */ 3178 P23_5_TCPWM1_LINE_COMPL25 = 9, /* Digital Active - tcpwm[1].line_compl[25]:1 */ 3179 P23_5_TCPWM1_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[72]:1 */ 3180 P23_5_TCPWM1_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[76]:1 */ 3181 P23_5_TCPWM1_LINE_COMPL521 = 16, /* Digital Active - tcpwm[1].line_compl[521]:0 */ 3182 P23_5_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:2 */ 3183 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 3184 P23_5_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:0 */ 3185 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 3186 3187 /* P23.6 */ 3188 P23_6_GPIO = 0, /* GPIO controls 'out' */ 3189 P23_6_AMUXA = 4, /* Analog mux bus A */ 3190 P23_6_AMUXB = 5, /* Analog mux bus B */ 3191 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3192 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3193 P23_6_TCPWM1_LINE23 = 8, /* Digital Active - tcpwm[1].line[23]:1 */ 3194 P23_6_TCPWM1_LINE_COMPL24 = 9, /* Digital Active - tcpwm[1].line_compl[24]:1 */ 3195 P23_6_TCPWM1_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[69]:1 */ 3196 P23_6_TCPWM1_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[73]:1 */ 3197 P23_6_TCPWM1_TR_ONE_CNT_IN1563 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1563]:0 */ 3198 P23_6_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:2 */ 3199 P23_6_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:0 */ 3200 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 3201 3202 /* P23.7 */ 3203 P23_7_GPIO = 0, /* GPIO controls 'out' */ 3204 P23_7_AMUXA = 4, /* Analog mux bus A */ 3205 P23_7_AMUXB = 5, /* Analog mux bus B */ 3206 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3207 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3208 P23_7_TCPWM1_LINE22 = 8, /* Digital Active - tcpwm[1].line[22]:1 */ 3209 P23_7_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:1 */ 3210 P23_7_TCPWM1_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[66]:1 */ 3211 P23_7_TCPWM1_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[70]:1 */ 3212 P23_7_TCPWM1_TR_ONE_CNT_IN1564 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1564]:0 */ 3213 P23_7_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:2 */ 3214 P23_7_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:1 */ 3215 P23_7_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:0 */ 3216 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 3217 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 3218 P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 3219 } en_hsiom_sel_t; 3220 3221 #endif /* _GPIO_XMC7200_176_TEQFP_H_ */ 3222 3223 3224 /* [] END OF FILE */ 3225
