1 /***************************************************************************//** 2 * \file gpio_xmc7100_144_teqfp.h 3 * 4 * \brief 5 * XMC7100 device GPIO header for 144-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_XMC7100_144_TEQFP_H_ 28 #define _GPIO_XMC7100_144_TEQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TEQFP 44 #define CY_GPIO_PIN_COUNT 144u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_MAIN, 50 AMUXBUS_REGHC_ISENSE, 51 AMUXBUS_TEST, 52 AMUXBUS_TESTECT, 53 AMUXBUS_TESTSRSS, 54 }; 55 56 /* AMUX Splitter Controls */ 57 typedef enum 58 { 59 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_REGHC_ISENSE */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (AUTOLVL) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P0_1_PORT GPIO_PRT0 71 #define P0_1_PIN 1u 72 #define P0_1_NUM 1u 73 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 78 #define P0_3_PORT GPIO_PRT0 79 #define P0_3_PIN 3u 80 #define P0_3_NUM 3u 81 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 1 (AUTOLVL) */ 84 #define P1_0_PORT GPIO_PRT1 85 #define P1_0_PIN 0u 86 #define P1_0_NUM 0u 87 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 88 #define P1_1_PORT GPIO_PRT1 89 #define P1_1_PIN 1u 90 #define P1_1_NUM 1u 91 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 92 93 /* PORT 2 (AUTOLVL) */ 94 #define P2_0_PORT GPIO_PRT2 95 #define P2_0_PIN 0u 96 #define P2_0_NUM 0u 97 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 98 #define P2_1_PORT GPIO_PRT2 99 #define P2_1_PIN 1u 100 #define P2_1_NUM 1u 101 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 102 #define P2_2_PORT GPIO_PRT2 103 #define P2_2_PIN 2u 104 #define P2_2_NUM 2u 105 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 106 #define P2_3_PORT GPIO_PRT2 107 #define P2_3_PIN 3u 108 #define P2_3_NUM 3u 109 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 110 #define P2_4_PORT GPIO_PRT2 111 #define P2_4_PIN 4u 112 #define P2_4_NUM 4u 113 #define P2_4_AMUXSEGMENT AMUXBUS_MAIN 114 115 /* PORT 3 (AUTOLVL) */ 116 #define P3_0_PORT GPIO_PRT3 117 #define P3_0_PIN 0u 118 #define P3_0_NUM 0u 119 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 120 #define P3_1_PORT GPIO_PRT3 121 #define P3_1_PIN 1u 122 #define P3_1_NUM 1u 123 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 124 #define P3_2_PORT GPIO_PRT3 125 #define P3_2_PIN 2u 126 #define P3_2_NUM 2u 127 #define P3_2_AMUXSEGMENT AMUXBUS_MAIN 128 #define P3_3_PORT GPIO_PRT3 129 #define P3_3_PIN 3u 130 #define P3_3_NUM 3u 131 #define P3_3_AMUXSEGMENT AMUXBUS_MAIN 132 #define P3_4_PORT GPIO_PRT3 133 #define P3_4_PIN 4u 134 #define P3_4_NUM 4u 135 #define P3_4_AMUXSEGMENT AMUXBUS_MAIN 136 137 /* PORT 4 (AUTOLVL) */ 138 #define P4_0_PORT GPIO_PRT4 139 #define P4_0_PIN 0u 140 #define P4_0_NUM 0u 141 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 142 #define P4_1_PORT GPIO_PRT4 143 #define P4_1_PIN 1u 144 #define P4_1_NUM 1u 145 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 146 147 /* PORT 5 (AUTOLVL) */ 148 #define P5_0_PORT GPIO_PRT5 149 #define P5_0_PIN 0u 150 #define P5_0_NUM 0u 151 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 152 #define P5_1_PORT GPIO_PRT5 153 #define P5_1_PIN 1u 154 #define P5_1_NUM 1u 155 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 156 #define P5_2_PORT GPIO_PRT5 157 #define P5_2_PIN 2u 158 #define P5_2_NUM 2u 159 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 160 #define P5_3_PORT GPIO_PRT5 161 #define P5_3_PIN 3u 162 #define P5_3_NUM 3u 163 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 164 #define P5_4_PORT GPIO_PRT5 165 #define P5_4_PIN 4u 166 #define P5_4_NUM 4u 167 #define P5_4_AMUXSEGMENT AMUXBUS_MAIN 168 169 /* PORT 6 (AUTOLVL) */ 170 #define P6_0_PORT GPIO_PRT6 171 #define P6_0_PIN 0u 172 #define P6_0_NUM 0u 173 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 174 #define P6_1_PORT GPIO_PRT6 175 #define P6_1_PIN 1u 176 #define P6_1_NUM 1u 177 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 178 #define P6_2_PORT GPIO_PRT6 179 #define P6_2_PIN 2u 180 #define P6_2_NUM 2u 181 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 182 #define P6_3_PORT GPIO_PRT6 183 #define P6_3_PIN 3u 184 #define P6_3_NUM 3u 185 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 186 #define P6_4_PORT GPIO_PRT6 187 #define P6_4_PIN 4u 188 #define P6_4_NUM 4u 189 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 190 #define P6_5_PORT GPIO_PRT6 191 #define P6_5_PIN 5u 192 #define P6_5_NUM 5u 193 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 194 #define P6_6_PORT GPIO_PRT6 195 #define P6_6_PIN 6u 196 #define P6_6_NUM 6u 197 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 198 #define P6_7_PORT GPIO_PRT6 199 #define P6_7_PIN 7u 200 #define P6_7_NUM 7u 201 #define P6_7_AMUXSEGMENT AMUXBUS_MAIN 202 203 /* PORT 7 (AUTOLVL) */ 204 #define P7_0_PORT GPIO_PRT7 205 #define P7_0_PIN 0u 206 #define P7_0_NUM 0u 207 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 208 #define P7_1_PORT GPIO_PRT7 209 #define P7_1_PIN 1u 210 #define P7_1_NUM 1u 211 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 212 #define P7_2_PORT GPIO_PRT7 213 #define P7_2_PIN 2u 214 #define P7_2_NUM 2u 215 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 216 #define P7_3_PORT GPIO_PRT7 217 #define P7_3_PIN 3u 218 #define P7_3_NUM 3u 219 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 220 #define P7_4_PORT GPIO_PRT7 221 #define P7_4_PIN 4u 222 #define P7_4_NUM 4u 223 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 224 #define P7_5_PORT GPIO_PRT7 225 #define P7_5_PIN 5u 226 #define P7_5_NUM 5u 227 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 228 #define P7_6_PORT GPIO_PRT7 229 #define P7_6_PIN 6u 230 #define P7_6_NUM 6u 231 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 232 #define P7_7_PORT GPIO_PRT7 233 #define P7_7_PIN 7u 234 #define P7_7_NUM 7u 235 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 236 237 /* PORT 8 (AUTOLVL) */ 238 #define P8_0_PORT GPIO_PRT8 239 #define P8_0_PIN 0u 240 #define P8_0_NUM 0u 241 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 242 #define P8_1_PORT GPIO_PRT8 243 #define P8_1_PIN 1u 244 #define P8_1_NUM 1u 245 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 246 #define P8_2_PORT GPIO_PRT8 247 #define P8_2_PIN 2u 248 #define P8_2_NUM 2u 249 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 250 #define P8_3_PORT GPIO_PRT8 251 #define P8_3_PIN 3u 252 #define P8_3_NUM 3u 253 #define P8_3_AMUXSEGMENT AMUXBUS_MAIN 254 255 /* PORT 9 (AUTOLVL) */ 256 #define P9_0_PORT GPIO_PRT9 257 #define P9_0_PIN 0u 258 #define P9_0_NUM 0u 259 #define P9_0_AMUXSEGMENT AMUXBUS_MAIN 260 #define P9_1_PORT GPIO_PRT9 261 #define P9_1_PIN 1u 262 #define P9_1_NUM 1u 263 #define P9_1_AMUXSEGMENT AMUXBUS_MAIN 264 265 /* PORT 10 (AUTOLVL) */ 266 #define P10_0_PORT GPIO_PRT10 267 #define P10_0_PIN 0u 268 #define P10_0_NUM 0u 269 #define P10_0_AMUXSEGMENT AMUXBUS_MAIN 270 #define P10_1_PORT GPIO_PRT10 271 #define P10_1_PIN 1u 272 #define P10_1_NUM 1u 273 #define P10_1_AMUXSEGMENT AMUXBUS_MAIN 274 #define P10_2_PORT GPIO_PRT10 275 #define P10_2_PIN 2u 276 #define P10_2_NUM 2u 277 #define P10_2_AMUXSEGMENT AMUXBUS_MAIN 278 #define P10_3_PORT GPIO_PRT10 279 #define P10_3_PIN 3u 280 #define P10_3_NUM 3u 281 #define P10_3_AMUXSEGMENT AMUXBUS_MAIN 282 #define P10_4_PORT GPIO_PRT10 283 #define P10_4_PIN 4u 284 #define P10_4_NUM 4u 285 #define P10_4_AMUXSEGMENT AMUXBUS_MAIN 286 287 /* PORT 11 (AUTOLVL) */ 288 #define P11_0_PORT GPIO_PRT11 289 #define P11_0_PIN 0u 290 #define P11_0_NUM 0u 291 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 292 #define P11_1_PORT GPIO_PRT11 293 #define P11_1_PIN 1u 294 #define P11_1_NUM 1u 295 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 296 #define P11_2_PORT GPIO_PRT11 297 #define P11_2_PIN 2u 298 #define P11_2_NUM 2u 299 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 300 301 /* PORT 12 (AUTOLVL) */ 302 #define P12_0_PORT GPIO_PRT12 303 #define P12_0_PIN 0u 304 #define P12_0_NUM 0u 305 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 306 #define P12_1_PORT GPIO_PRT12 307 #define P12_1_PIN 1u 308 #define P12_1_NUM 1u 309 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 310 #define P12_2_PORT GPIO_PRT12 311 #define P12_2_PIN 2u 312 #define P12_2_NUM 2u 313 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 314 #define P12_3_PORT GPIO_PRT12 315 #define P12_3_PIN 3u 316 #define P12_3_NUM 3u 317 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 318 #define P12_4_PORT GPIO_PRT12 319 #define P12_4_PIN 4u 320 #define P12_4_NUM 4u 321 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 322 #define P12_5_PORT GPIO_PRT12 323 #define P12_5_PIN 5u 324 #define P12_5_NUM 5u 325 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 326 327 /* PORT 13 (AUTOLVL) */ 328 #define P13_0_PORT GPIO_PRT13 329 #define P13_0_PIN 0u 330 #define P13_0_NUM 0u 331 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 332 #define P13_1_PORT GPIO_PRT13 333 #define P13_1_PIN 1u 334 #define P13_1_NUM 1u 335 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 336 #define P13_2_PORT GPIO_PRT13 337 #define P13_2_PIN 2u 338 #define P13_2_NUM 2u 339 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 340 #define P13_3_PORT GPIO_PRT13 341 #define P13_3_PIN 3u 342 #define P13_3_NUM 3u 343 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 344 #define P13_4_PORT GPIO_PRT13 345 #define P13_4_PIN 4u 346 #define P13_4_NUM 4u 347 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 348 #define P13_5_PORT GPIO_PRT13 349 #define P13_5_PIN 5u 350 #define P13_5_NUM 5u 351 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 352 #define P13_6_PORT GPIO_PRT13 353 #define P13_6_PIN 6u 354 #define P13_6_NUM 6u 355 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 356 #define P13_7_PORT GPIO_PRT13 357 #define P13_7_PIN 7u 358 #define P13_7_NUM 7u 359 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 360 361 /* PORT 14 (AUTOLVL) */ 362 #define P14_0_PORT GPIO_PRT14 363 #define P14_0_PIN 0u 364 #define P14_0_NUM 0u 365 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 366 #define P14_1_PORT GPIO_PRT14 367 #define P14_1_PIN 1u 368 #define P14_1_NUM 1u 369 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 370 #define P14_4_PORT GPIO_PRT14 371 #define P14_4_PIN 4u 372 #define P14_4_NUM 4u 373 #define P14_4_AMUXSEGMENT AMUXBUS_MAIN 374 #define P14_5_PORT GPIO_PRT14 375 #define P14_5_PIN 5u 376 #define P14_5_NUM 5u 377 #define P14_5_AMUXSEGMENT AMUXBUS_MAIN 378 379 /* PORT 15 (AUTOLVL) */ 380 #define P15_0_PORT GPIO_PRT15 381 #define P15_0_PIN 0u 382 #define P15_0_NUM 0u 383 #define P15_0_AMUXSEGMENT AMUXBUS_MAIN 384 #define P15_1_PORT GPIO_PRT15 385 #define P15_1_PIN 1u 386 #define P15_1_NUM 1u 387 #define P15_1_AMUXSEGMENT AMUXBUS_MAIN 388 #define P15_2_PORT GPIO_PRT15 389 #define P15_2_PIN 2u 390 #define P15_2_NUM 2u 391 #define P15_2_AMUXSEGMENT AMUXBUS_MAIN 392 #define P15_3_PORT GPIO_PRT15 393 #define P15_3_PIN 3u 394 #define P15_3_NUM 3u 395 #define P15_3_AMUXSEGMENT AMUXBUS_MAIN 396 397 /* PORT 17 (AUTOLVL) */ 398 #define P17_0_PORT GPIO_PRT17 399 #define P17_0_PIN 0u 400 #define P17_0_NUM 0u 401 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 402 #define P17_1_PORT GPIO_PRT17 403 #define P17_1_PIN 1u 404 #define P17_1_NUM 1u 405 #define P17_1_AMUXSEGMENT AMUXBUS_MAIN 406 #define P17_2_PORT GPIO_PRT17 407 #define P17_2_PIN 2u 408 #define P17_2_NUM 2u 409 #define P17_2_AMUXSEGMENT AMUXBUS_MAIN 410 #define P17_3_PORT GPIO_PRT17 411 #define P17_3_PIN 3u 412 #define P17_3_NUM 3u 413 #define P17_3_AMUXSEGMENT AMUXBUS_MAIN 414 #define P17_4_PORT GPIO_PRT17 415 #define P17_4_PIN 4u 416 #define P17_4_NUM 4u 417 #define P17_4_AMUXSEGMENT AMUXBUS_MAIN 418 419 /* PORT 18 (AUTOLVL) */ 420 #define P18_0_PORT GPIO_PRT18 421 #define P18_0_PIN 0u 422 #define P18_0_NUM 0u 423 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 424 #define P18_1_PORT GPIO_PRT18 425 #define P18_1_PIN 1u 426 #define P18_1_NUM 1u 427 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 428 #define P18_2_PORT GPIO_PRT18 429 #define P18_2_PIN 2u 430 #define P18_2_NUM 2u 431 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 432 #define P18_3_PORT GPIO_PRT18 433 #define P18_3_PIN 3u 434 #define P18_3_NUM 3u 435 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 436 #define P18_4_PORT GPIO_PRT18 437 #define P18_4_PIN 4u 438 #define P18_4_NUM 4u 439 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 440 #define P18_5_PORT GPIO_PRT18 441 #define P18_5_PIN 5u 442 #define P18_5_NUM 5u 443 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 444 #define P18_6_PORT GPIO_PRT18 445 #define P18_6_PIN 6u 446 #define P18_6_NUM 6u 447 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 448 #define P18_7_PORT GPIO_PRT18 449 #define P18_7_PIN 7u 450 #define P18_7_NUM 7u 451 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 452 453 /* PORT 19 (AUTOLVL) */ 454 #define P19_0_PORT GPIO_PRT19 455 #define P19_0_PIN 0u 456 #define P19_0_NUM 0u 457 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 458 #define P19_1_PORT GPIO_PRT19 459 #define P19_1_PIN 1u 460 #define P19_1_NUM 1u 461 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 462 #define P19_2_PORT GPIO_PRT19 463 #define P19_2_PIN 2u 464 #define P19_2_NUM 2u 465 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 466 #define P19_3_PORT GPIO_PRT19 467 #define P19_3_PIN 3u 468 #define P19_3_NUM 3u 469 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 470 #define P19_4_PORT GPIO_PRT19 471 #define P19_4_PIN 4u 472 #define P19_4_NUM 4u 473 #define P19_4_AMUXSEGMENT AMUXBUS_MAIN 474 475 /* PORT 20 (AUTOLVL) */ 476 #define P20_0_PORT GPIO_PRT20 477 #define P20_0_PIN 0u 478 #define P20_0_NUM 0u 479 #define P20_0_AMUXSEGMENT AMUXBUS_MAIN 480 #define P20_1_PORT GPIO_PRT20 481 #define P20_1_PIN 1u 482 #define P20_1_NUM 1u 483 #define P20_1_AMUXSEGMENT AMUXBUS_MAIN 484 #define P20_2_PORT GPIO_PRT20 485 #define P20_2_PIN 2u 486 #define P20_2_NUM 2u 487 #define P20_2_AMUXSEGMENT AMUXBUS_MAIN 488 #define P20_3_PORT GPIO_PRT20 489 #define P20_3_PIN 3u 490 #define P20_3_NUM 3u 491 #define P20_3_AMUXSEGMENT AMUXBUS_MAIN 492 493 /* PORT 21 (AUTOLVL) */ 494 #define P21_0_PORT GPIO_PRT21 495 #define P21_0_PIN 0u 496 #define P21_0_NUM 0u 497 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 498 #define P21_1_PORT GPIO_PRT21 499 #define P21_1_PIN 1u 500 #define P21_1_NUM 1u 501 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 502 #define P21_2_PORT GPIO_PRT21 503 #define P21_2_PIN 2u 504 #define P21_2_NUM 2u 505 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 506 #define P21_3_PORT GPIO_PRT21 507 #define P21_3_PIN 3u 508 #define P21_3_NUM 3u 509 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 510 #define P21_5_PORT GPIO_PRT21 511 #define P21_5_PIN 5u 512 #define P21_5_NUM 5u 513 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 514 #define P21_6_PORT GPIO_PRT21 515 #define P21_6_PIN 6u 516 #define P21_6_NUM 6u 517 #define P21_6_AMUXSEGMENT AMUXBUS_MAIN 518 519 /* PORT 22 (AUTOLVL) */ 520 #define P22_1_PORT GPIO_PRT22 521 #define P22_1_PIN 1u 522 #define P22_1_NUM 1u 523 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 524 #define P22_2_PORT GPIO_PRT22 525 #define P22_2_PIN 2u 526 #define P22_2_NUM 2u 527 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 528 #define P22_3_PORT GPIO_PRT22 529 #define P22_3_PIN 3u 530 #define P22_3_NUM 3u 531 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 532 #define P22_4_PORT GPIO_PRT22 533 #define P22_4_PIN 4u 534 #define P22_4_NUM 4u 535 #define P22_4_AMUXSEGMENT AMUXBUS_MAIN 536 #define P22_5_PORT GPIO_PRT22 537 #define P22_5_PIN 5u 538 #define P22_5_NUM 5u 539 #define P22_5_AMUXSEGMENT AMUXBUS_MAIN 540 #define P22_6_PORT GPIO_PRT22 541 #define P22_6_PIN 6u 542 #define P22_6_NUM 6u 543 #define P22_6_AMUXSEGMENT AMUXBUS_MAIN 544 545 /* PORT 23 (AUTOLVL) */ 546 #define P23_0_PORT GPIO_PRT23 547 #define P23_0_PIN 0u 548 #define P23_0_NUM 0u 549 #define P23_0_AMUXSEGMENT AMUXBUS_MAIN 550 #define P23_1_PORT GPIO_PRT23 551 #define P23_1_PIN 1u 552 #define P23_1_NUM 1u 553 #define P23_1_AMUXSEGMENT AMUXBUS_MAIN 554 #define P23_3_PORT GPIO_PRT23 555 #define P23_3_PIN 3u 556 #define P23_3_NUM 3u 557 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 558 #define P23_4_PORT GPIO_PRT23 559 #define P23_4_PIN 4u 560 #define P23_4_NUM 4u 561 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 562 #define P23_5_PORT GPIO_PRT23 563 #define P23_5_PIN 5u 564 #define P23_5_NUM 5u 565 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 566 #define P23_6_PORT GPIO_PRT23 567 #define P23_6_PIN 6u 568 #define P23_6_NUM 6u 569 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 570 #define P23_7_PORT GPIO_PRT23 571 #define P23_7_PIN 7u 572 #define P23_7_NUM 7u 573 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 574 575 /* Analog Connections */ 576 #define PASS0_I_TEMP_KELVIN_PORT 21u 577 #define PASS0_I_TEMP_KELVIN_PIN 2u 578 #define PASS0_SARMUX_MOTOR0_PORT 11u 579 #define PASS0_SARMUX_MOTOR0_PIN 0u 580 #define PASS0_SARMUX_MOTOR1_PORT 11u 581 #define PASS0_SARMUX_MOTOR1_PIN 1u 582 #define PASS0_SARMUX_MOTOR2_PORT 11u 583 #define PASS0_SARMUX_MOTOR2_PIN 2u 584 #define PASS0_SARMUX_PADS0_PORT 6u 585 #define PASS0_SARMUX_PADS0_PIN 0u 586 #define PASS0_SARMUX_PADS1_PORT 6u 587 #define PASS0_SARMUX_PADS1_PIN 1u 588 #define PASS0_SARMUX_PADS16_PORT 7u 589 #define PASS0_SARMUX_PADS16_PIN 0u 590 #define PASS0_SARMUX_PADS17_PORT 7u 591 #define PASS0_SARMUX_PADS17_PIN 1u 592 #define PASS0_SARMUX_PADS18_PORT 7u 593 #define PASS0_SARMUX_PADS18_PIN 2u 594 #define PASS0_SARMUX_PADS19_PORT 7u 595 #define PASS0_SARMUX_PADS19_PIN 3u 596 #define PASS0_SARMUX_PADS2_PORT 6u 597 #define PASS0_SARMUX_PADS2_PIN 2u 598 #define PASS0_SARMUX_PADS20_PORT 7u 599 #define PASS0_SARMUX_PADS20_PIN 4u 600 #define PASS0_SARMUX_PADS21_PORT 7u 601 #define PASS0_SARMUX_PADS21_PIN 5u 602 #define PASS0_SARMUX_PADS22_PORT 7u 603 #define PASS0_SARMUX_PADS22_PIN 6u 604 #define PASS0_SARMUX_PADS23_PORT 7u 605 #define PASS0_SARMUX_PADS23_PIN 7u 606 #define PASS0_SARMUX_PADS24_PORT 8u 607 #define PASS0_SARMUX_PADS24_PIN 1u 608 #define PASS0_SARMUX_PADS25_PORT 8u 609 #define PASS0_SARMUX_PADS25_PIN 2u 610 #define PASS0_SARMUX_PADS26_PORT 8u 611 #define PASS0_SARMUX_PADS26_PIN 3u 612 #define PASS0_SARMUX_PADS28_PORT 9u 613 #define PASS0_SARMUX_PADS28_PIN 0u 614 #define PASS0_SARMUX_PADS29_PORT 9u 615 #define PASS0_SARMUX_PADS29_PIN 1u 616 #define PASS0_SARMUX_PADS3_PORT 6u 617 #define PASS0_SARMUX_PADS3_PIN 3u 618 #define PASS0_SARMUX_PADS32_PORT 10u 619 #define PASS0_SARMUX_PADS32_PIN 4u 620 #define PASS0_SARMUX_PADS36_PORT 12u 621 #define PASS0_SARMUX_PADS36_PIN 0u 622 #define PASS0_SARMUX_PADS37_PORT 12u 623 #define PASS0_SARMUX_PADS37_PIN 1u 624 #define PASS0_SARMUX_PADS38_PORT 12u 625 #define PASS0_SARMUX_PADS38_PIN 2u 626 #define PASS0_SARMUX_PADS39_PORT 12u 627 #define PASS0_SARMUX_PADS39_PIN 3u 628 #define PASS0_SARMUX_PADS4_PORT 6u 629 #define PASS0_SARMUX_PADS4_PIN 4u 630 #define PASS0_SARMUX_PADS40_PORT 12u 631 #define PASS0_SARMUX_PADS40_PIN 4u 632 #define PASS0_SARMUX_PADS41_PORT 12u 633 #define PASS0_SARMUX_PADS41_PIN 5u 634 #define PASS0_SARMUX_PADS44_PORT 13u 635 #define PASS0_SARMUX_PADS44_PIN 0u 636 #define PASS0_SARMUX_PADS45_PORT 13u 637 #define PASS0_SARMUX_PADS45_PIN 1u 638 #define PASS0_SARMUX_PADS46_PORT 13u 639 #define PASS0_SARMUX_PADS46_PIN 2u 640 #define PASS0_SARMUX_PADS47_PORT 13u 641 #define PASS0_SARMUX_PADS47_PIN 3u 642 #define PASS0_SARMUX_PADS48_PORT 13u 643 #define PASS0_SARMUX_PADS48_PIN 4u 644 #define PASS0_SARMUX_PADS49_PORT 13u 645 #define PASS0_SARMUX_PADS49_PIN 5u 646 #define PASS0_SARMUX_PADS5_PORT 6u 647 #define PASS0_SARMUX_PADS5_PIN 5u 648 #define PASS0_SARMUX_PADS50_PORT 13u 649 #define PASS0_SARMUX_PADS50_PIN 6u 650 #define PASS0_SARMUX_PADS51_PORT 13u 651 #define PASS0_SARMUX_PADS51_PIN 7u 652 #define PASS0_SARMUX_PADS52_PORT 14u 653 #define PASS0_SARMUX_PADS52_PIN 0u 654 #define PASS0_SARMUX_PADS53_PORT 14u 655 #define PASS0_SARMUX_PADS53_PIN 1u 656 #define PASS0_SARMUX_PADS56_PORT 14u 657 #define PASS0_SARMUX_PADS56_PIN 4u 658 #define PASS0_SARMUX_PADS57_PORT 14u 659 #define PASS0_SARMUX_PADS57_PIN 5u 660 #define PASS0_SARMUX_PADS6_PORT 6u 661 #define PASS0_SARMUX_PADS6_PIN 6u 662 #define PASS0_SARMUX_PADS60_PORT 15u 663 #define PASS0_SARMUX_PADS60_PIN 0u 664 #define PASS0_SARMUX_PADS61_PORT 15u 665 #define PASS0_SARMUX_PADS61_PIN 1u 666 #define PASS0_SARMUX_PADS62_PORT 15u 667 #define PASS0_SARMUX_PADS62_PIN 2u 668 #define PASS0_SARMUX_PADS63_PORT 15u 669 #define PASS0_SARMUX_PADS63_PIN 3u 670 #define PASS0_SARMUX_PADS64_PORT 18u 671 #define PASS0_SARMUX_PADS64_PIN 0u 672 #define PASS0_SARMUX_PADS65_PORT 18u 673 #define PASS0_SARMUX_PADS65_PIN 1u 674 #define PASS0_SARMUX_PADS66_PORT 18u 675 #define PASS0_SARMUX_PADS66_PIN 2u 676 #define PASS0_SARMUX_PADS67_PORT 18u 677 #define PASS0_SARMUX_PADS67_PIN 3u 678 #define PASS0_SARMUX_PADS68_PORT 18u 679 #define PASS0_SARMUX_PADS68_PIN 4u 680 #define PASS0_SARMUX_PADS69_PORT 18u 681 #define PASS0_SARMUX_PADS69_PIN 5u 682 #define PASS0_SARMUX_PADS7_PORT 6u 683 #define PASS0_SARMUX_PADS7_PIN 7u 684 #define PASS0_SARMUX_PADS70_PORT 18u 685 #define PASS0_SARMUX_PADS70_PIN 6u 686 #define PASS0_SARMUX_PADS71_PORT 18u 687 #define PASS0_SARMUX_PADS71_PIN 7u 688 #define PASS0_VB_TEMP_KELVIN_PORT 10u 689 #define PASS0_VB_TEMP_KELVIN_PIN 4u 690 #define PASS0_VE_TEMP_KELVIN_PORT 23u 691 #define PASS0_VE_TEMP_KELVIN_PIN 4u 692 #define SRSS_ADFT_PIN0_PORT 23u 693 #define SRSS_ADFT_PIN0_PIN 4u 694 #define SRSS_ADFT_PIN1_PORT 23u 695 #define SRSS_ADFT_PIN1_PIN 3u 696 #define SRSS_ECO_IN_PORT 21u 697 #define SRSS_ECO_IN_PIN 2u 698 #define SRSS_ECO_OUT_PORT 21u 699 #define SRSS_ECO_OUT_PIN 3u 700 #define SRSS_REGHC_ISENSE_INM_PORT 22u 701 #define SRSS_REGHC_ISENSE_INM_PIN 2u 702 #define SRSS_REGHC_ISENSE_INP_PORT 22u 703 #define SRSS_REGHC_ISENSE_INP_PIN 1u 704 #define SRSS_REGHC_RST_VOUT_PORT 22u 705 #define SRSS_REGHC_RST_VOUT_PIN 3u 706 #define SRSS_VEXT_REF_REG_PORT 21u 707 #define SRSS_VEXT_REF_REG_PIN 3u 708 #define SRSS_WCO_IN_PORT 21u 709 #define SRSS_WCO_IN_PIN 0u 710 #define SRSS_WCO_OUT_PORT 21u 711 #define SRSS_WCO_OUT_PIN 1u 712 713 /* HSIOM Connections */ 714 typedef enum 715 { 716 /* Generic HSIOM connections */ 717 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 718 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 719 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 720 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 721 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 722 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 723 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 724 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 725 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 726 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 727 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 728 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 729 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 730 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 731 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 732 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 733 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 734 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 735 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 736 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 737 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 738 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 739 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 740 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 741 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 742 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 743 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 744 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 745 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 746 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 747 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 748 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 749 750 /* P0.0 */ 751 P0_0_GPIO = 0, /* GPIO controls 'out' */ 752 P0_0_AMUXA = 4, /* Analog mux bus A */ 753 P0_0_AMUXB = 5, /* Analog mux bus B */ 754 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 755 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 756 P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ 757 P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 758 P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ 759 P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ 760 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 761 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 762 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 763 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 764 765 /* P0.1 */ 766 P0_1_GPIO = 0, /* GPIO controls 'out' */ 767 P0_1_AMUXA = 4, /* Analog mux bus A */ 768 P0_1_AMUXB = 5, /* Analog mux bus B */ 769 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 770 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 771 P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ 772 P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ 773 P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ 774 P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ 775 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 776 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 777 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 778 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 779 780 /* P0.2 */ 781 P0_2_GPIO = 0, /* GPIO controls 'out' */ 782 P0_2_AMUXA = 4, /* Analog mux bus A */ 783 P0_2_AMUXB = 5, /* Analog mux bus B */ 784 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 785 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 786 P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ 787 P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ 788 P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ 789 P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ 790 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 791 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 792 P0_2_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:2 */ 793 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 794 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 795 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 796 797 /* P0.3 */ 798 P0_3_GPIO = 0, /* GPIO controls 'out' */ 799 P0_3_AMUXA = 4, /* Analog mux bus A */ 800 P0_3_AMUXB = 5, /* Analog mux bus B */ 801 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 802 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 803 P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ 804 P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ 805 P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ 806 P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ 807 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 808 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 809 P0_3_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:2 */ 810 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 811 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 812 813 /* P1.0 */ 814 P1_0_GPIO = 0, /* GPIO controls 'out' */ 815 P1_0_AMUXA = 4, /* Analog mux bus A */ 816 P1_0_AMUXB = 5, /* Analog mux bus B */ 817 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 818 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 819 P1_0_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:1 */ 820 P1_0_TCPWM0_LINE_COMPL13 = 9, /* Digital Active - tcpwm[0].line_compl[13]:1 */ 821 P1_0_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:1 */ 822 P1_0_TCPWM0_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[40]:1 */ 823 P1_0_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 824 P1_0_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:0 */ 825 P1_0_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:2 */ 826 P1_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 827 828 /* P1.1 */ 829 P1_1_GPIO = 0, /* GPIO controls 'out' */ 830 P1_1_AMUXA = 4, /* Analog mux bus A */ 831 P1_1_AMUXB = 5, /* Analog mux bus B */ 832 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 833 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 834 P1_1_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:1 */ 835 P1_1_TCPWM0_LINE_COMPL12 = 9, /* Digital Active - tcpwm[0].line_compl[12]:1 */ 836 P1_1_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:1 */ 837 P1_1_TCPWM0_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:1 */ 838 P1_1_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 839 P1_1_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:0 */ 840 P1_1_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:2 */ 841 P1_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 842 843 /* P2.0 */ 844 P2_0_GPIO = 0, /* GPIO controls 'out' */ 845 P2_0_AMUXA = 4, /* Analog mux bus A */ 846 P2_0_AMUXB = 5, /* Analog mux bus B */ 847 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 848 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 849 P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 850 P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ 851 P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 852 P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 853 P2_0_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:0 */ 854 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 855 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 856 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 857 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 858 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 859 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 860 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 861 862 /* P2.1 */ 863 P2_1_GPIO = 0, /* GPIO controls 'out' */ 864 P2_1_AMUXA = 4, /* Analog mux bus A */ 865 P2_1_AMUXB = 5, /* Analog mux bus B */ 866 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 867 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 868 P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 869 P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 870 P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ 871 P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 872 P2_1_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:0 */ 873 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 874 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 875 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 876 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 877 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 878 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 879 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 880 881 /* P2.2 */ 882 P2_2_GPIO = 0, /* GPIO controls 'out' */ 883 P2_2_AMUXA = 4, /* Analog mux bus A */ 884 P2_2_AMUXB = 5, /* Analog mux bus B */ 885 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 886 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 887 P2_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 888 P2_2_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 889 P2_2_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:1 */ 890 P2_2_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:1 */ 891 P2_2_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:0 */ 892 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 893 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 894 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 895 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 896 P2_2_ETH0_RX_ER = 24, /* Digital Active - eth[0].rx_er:0 */ 897 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 898 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 899 900 /* P2.3 */ 901 P2_3_GPIO = 0, /* GPIO controls 'out' */ 902 P2_3_AMUXA = 4, /* Analog mux bus A */ 903 P2_3_AMUXB = 5, /* Analog mux bus B */ 904 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 905 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 906 P2_3_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 907 P2_3_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 908 P2_3_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:1 */ 909 P2_3_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:1 */ 910 P2_3_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:0 */ 911 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 912 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 913 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 914 P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL = 24, /* Digital Active - eth[0].eth_tsu_timer_cmp_val:0 */ 915 P2_3_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:1 */ 916 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 917 918 /* P2.4 */ 919 P2_4_GPIO = 0, /* GPIO controls 'out' */ 920 P2_4_AMUXA = 4, /* Analog mux bus A */ 921 P2_4_AMUXB = 5, /* Analog mux bus B */ 922 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 923 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 924 P2_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 925 P2_4_TCPWM0_LINE_COMPL4 = 9, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 926 P2_4_TCPWM0_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[9]:1 */ 927 P2_4_TCPWM0_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[13]:1 */ 928 P2_4_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:0 */ 929 P2_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:0 */ 930 P2_4_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:1 */ 931 P2_4_PERI_TR_IO_INPUT6 = 26, /* Digital Active - peri.tr_io_input[6]:0 */ 932 933 /* P3.0 */ 934 P3_0_GPIO = 0, /* GPIO controls 'out' */ 935 P3_0_AMUXA = 4, /* Analog mux bus A */ 936 P3_0_AMUXB = 5, /* Analog mux bus B */ 937 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 938 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 939 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 940 P3_0_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 941 P3_0_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ 942 P3_0_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:1 */ 943 P3_0_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:0 */ 944 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 945 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 946 P3_0_CANFD0_TTCAN_TX3 = 21, /* Digital Active - canfd[0].ttcan_tx[3]:0 */ 947 P3_0_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio:0 */ 948 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 949 950 /* P3.1 */ 951 P3_1_GPIO = 0, /* GPIO controls 'out' */ 952 P3_1_AMUXA = 4, /* Analog mux bus A */ 953 P3_1_AMUXB = 5, /* Analog mux bus B */ 954 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 955 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 956 P3_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 957 P3_1_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 958 P3_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ 959 P3_1_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:1 */ 960 P3_1_TCPWM0_LINE_COMPL519 = 16, /* Digital Active - tcpwm[0].line_compl[519]:0 */ 961 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 962 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 963 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 964 P3_1_CANFD0_TTCAN_RX3 = 21, /* Digital Active - canfd[0].ttcan_rx[3]:0 */ 965 P3_1_ETH0_MDC = 24, /* Digital Active - eth[0].mdc:0 */ 966 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 967 968 /* P3.2 */ 969 P3_2_GPIO = 0, /* GPIO controls 'out' */ 970 P3_2_AMUXA = 4, /* Analog mux bus A */ 971 P3_2_AMUXB = 5, /* Analog mux bus B */ 972 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 973 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 974 P3_2_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:1 */ 975 P3_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 976 P3_2_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:1 */ 977 P3_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ 978 P3_2_TCPWM0_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1549]:0 */ 979 P3_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:0 */ 980 P3_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:0 */ 981 P3_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:0 */ 982 983 /* P3.3 */ 984 P3_3_GPIO = 0, /* GPIO controls 'out' */ 985 P3_3_AMUXA = 4, /* Analog mux bus A */ 986 P3_3_AMUXB = 5, /* Analog mux bus B */ 987 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 988 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 989 P3_3_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:1 */ 990 P3_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 991 P3_3_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:1 */ 992 P3_3_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:1 */ 993 P3_3_TCPWM0_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1552]:0 */ 994 P3_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:0 */ 995 P3_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:0 */ 996 997 /* P3.4 */ 998 P3_4_GPIO = 0, /* GPIO controls 'out' */ 999 P3_4_AMUXA = 4, /* Analog mux bus A */ 1000 P3_4_AMUXB = 5, /* Analog mux bus B */ 1001 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1002 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1003 P3_4_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:1 */ 1004 P3_4_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 1005 P3_4_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:1 */ 1006 P3_4_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:1 */ 1007 P3_4_TCPWM0_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1555]:0 */ 1008 P3_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:0 */ 1009 P3_4_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:2 */ 1010 1011 /* P4.0 */ 1012 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1013 P4_0_AMUXA = 4, /* Analog mux bus A */ 1014 P4_0_AMUXB = 5, /* Analog mux bus B */ 1015 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1016 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1017 P4_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 1018 P4_0_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ 1019 P4_0_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:0 */ 1020 P4_0_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:1 */ 1021 P4_0_PASS0_SAR_EXT_MUX_SEL0 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[0] */ 1022 P4_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:0 */ 1023 P4_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:0 */ 1024 P4_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:1 */ 1025 P4_0_PERI_TR_IO_INPUT10 = 26, /* Digital Active - peri.tr_io_input[10]:0 */ 1026 1027 /* P4.1 */ 1028 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1029 P4_1_AMUXA = 4, /* Analog mux bus A */ 1030 P4_1_AMUXB = 5, /* Analog mux bus B */ 1031 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1032 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1033 P4_1_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 1034 P4_1_TCPWM0_LINE_COMPL4 = 9, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 1035 P4_1_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:0 */ 1036 P4_1_TCPWM0_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[13]:0 */ 1037 P4_1_PASS0_SAR_EXT_MUX_SEL1 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[1] */ 1038 P4_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:0 */ 1039 P4_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:0 */ 1040 P4_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:0 */ 1041 P4_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:1 */ 1042 P4_1_PERI_TR_IO_INPUT11 = 26, /* Digital Active - peri.tr_io_input[11]:0 */ 1043 1044 /* P5.0 */ 1045 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1046 P5_0_AMUXA = 4, /* Analog mux bus A */ 1047 P5_0_AMUXB = 5, /* Analog mux bus B */ 1048 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1049 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1050 P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ 1051 P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ 1052 P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 1053 P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 1054 P5_0_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:1 */ 1055 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 1056 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 1057 1058 /* P5.1 */ 1059 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1060 P5_1_AMUXA = 4, /* Analog mux bus A */ 1061 P5_1_AMUXB = 5, /* Analog mux bus B */ 1062 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1063 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1064 P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ 1065 P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ 1066 P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 1067 P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 1068 P5_1_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:1 */ 1069 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 1070 1071 /* P5.2 */ 1072 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1073 P5_2_AMUXA = 4, /* Analog mux bus A */ 1074 P5_2_AMUXB = 5, /* Analog mux bus B */ 1075 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1076 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1077 P5_2_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:0 */ 1078 P5_2_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:0 */ 1079 P5_2_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ 1080 P5_2_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ 1081 P5_2_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:2 */ 1082 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 1083 1084 /* P5.3 */ 1085 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1086 P5_3_AMUXA = 4, /* Analog mux bus A */ 1087 P5_3_AMUXB = 5, /* Analog mux bus B */ 1088 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1089 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1090 P5_3_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:0 */ 1091 P5_3_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:0 */ 1092 P5_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ 1093 P5_3_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ 1094 P5_3_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:2 */ 1095 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 1096 1097 /* P5.4 */ 1098 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1099 P5_4_AMUXA = 4, /* Analog mux bus A */ 1100 P5_4_AMUXB = 5, /* Analog mux bus B */ 1101 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1102 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1103 P5_4_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:0 */ 1104 P5_4_TCPWM0_LINE_COMPL12 = 9, /* Digital Active - tcpwm[0].line_compl[12]:0 */ 1105 P5_4_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:0 */ 1106 P5_4_TCPWM0_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:0 */ 1107 P5_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:0 */ 1108 P5_4_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:1 */ 1109 1110 /* P6.0 */ 1111 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1112 P6_0_AMUXA = 4, /* Analog mux bus A */ 1113 P6_0_AMUXB = 5, /* Analog mux bus B */ 1114 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1115 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1116 P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 1117 P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ 1118 P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ 1119 P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ 1120 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 1121 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 1122 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 1123 P6_0_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:1 */ 1124 1125 /* P6.1 */ 1126 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1127 P6_1_AMUXA = 4, /* Analog mux bus A */ 1128 P6_1_AMUXB = 5, /* Analog mux bus B */ 1129 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1130 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1131 P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 1132 P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 1133 P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 1134 P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ 1135 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 1136 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 1137 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 1138 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 1139 1140 /* P6.2 */ 1141 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1142 P6_2_AMUXA = 4, /* Analog mux bus A */ 1143 P6_2_AMUXB = 5, /* Analog mux bus B */ 1144 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1145 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1146 P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 1147 P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 1148 P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ 1149 P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 1150 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 1151 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 1152 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 1153 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 1154 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 1155 P6_2_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:0 */ 1156 1157 /* P6.3 */ 1158 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1159 P6_3_AMUXA = 4, /* Analog mux bus A */ 1160 P6_3_AMUXB = 5, /* Analog mux bus B */ 1161 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1162 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1163 P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 1164 P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 1165 P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 1166 P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ 1167 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 1168 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 1169 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 1170 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 1171 P6_3_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:0 */ 1172 P6_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:0 */ 1173 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 1174 1175 /* P6.4 */ 1176 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1177 P6_4_AMUXA = 4, /* Analog mux bus A */ 1178 P6_4_AMUXB = 5, /* Analog mux bus B */ 1179 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1180 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1181 P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 1182 P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 1183 P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ 1184 P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ 1185 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 1186 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 1187 P6_4_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:0 */ 1188 P6_4_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:0 */ 1189 1190 /* P6.5 */ 1191 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1192 P6_5_AMUXA = 4, /* Analog mux bus A */ 1193 P6_5_AMUXB = 5, /* Analog mux bus B */ 1194 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1195 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1196 P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 1197 P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 1198 P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ 1199 P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ 1200 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 1201 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 1202 P6_5_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:0 */ 1203 P6_5_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:0 */ 1204 1205 /* P6.6 */ 1206 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1207 P6_6_AMUXA = 4, /* Analog mux bus A */ 1208 P6_6_AMUXB = 5, /* Analog mux bus B */ 1209 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1210 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1211 P6_6_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:0 */ 1212 P6_6_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 1213 P6_6_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:0 */ 1214 P6_6_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:0 */ 1215 P6_6_SCB4_SPI_SELECT3 = 19, /* Digital Active - scb[4].spi_select3:0 */ 1216 P6_6_PERI_TR_IO_INPUT8 = 26, /* Digital Active - peri.tr_io_input[8]:0 */ 1217 1218 /* P6.7 */ 1219 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1220 P6_7_AMUXA = 4, /* Analog mux bus A */ 1221 P6_7_AMUXB = 5, /* Analog mux bus B */ 1222 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1223 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1224 P6_7_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 1225 P6_7_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 1226 P6_7_TCPWM0_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[9]:0 */ 1227 P6_7_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:0 */ 1228 P6_7_PERI_TR_IO_INPUT9 = 26, /* Digital Active - peri.tr_io_input[9]:0 */ 1229 1230 /* P7.0 */ 1231 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1232 P7_0_AMUXA = 4, /* Analog mux bus A */ 1233 P7_0_AMUXB = 5, /* Analog mux bus B */ 1234 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1235 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1236 P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 1237 P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 1238 P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ 1239 P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ 1240 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 1241 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 1242 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 1243 P7_0_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:0 */ 1244 P7_0_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:0 */ 1245 1246 /* P7.1 */ 1247 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1248 P7_1_AMUXA = 4, /* Analog mux bus A */ 1249 P7_1_AMUXB = 5, /* Analog mux bus B */ 1250 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1251 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1252 P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ 1253 P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 1254 P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ 1255 P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ 1256 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 1257 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 1258 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 1259 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 1260 P7_1_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:0 */ 1261 P7_1_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:0 */ 1262 1263 /* P7.2 */ 1264 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1265 P7_2_AMUXA = 4, /* Analog mux bus A */ 1266 P7_2_AMUXB = 5, /* Analog mux bus B */ 1267 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1268 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1269 P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 1270 P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ 1271 P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ 1272 P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ 1273 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 1274 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 1275 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 1276 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 1277 P7_2_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:0 */ 1278 P7_2_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:0 */ 1279 1280 /* P7.3 */ 1281 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1282 P7_3_AMUXA = 4, /* Analog mux bus A */ 1283 P7_3_AMUXB = 5, /* Analog mux bus B */ 1284 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1285 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1286 P7_3_TCPWM0_LINE16 = 8, /* Digital Active - tcpwm[0].line[16]:0 */ 1287 P7_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 1288 P7_3_TCPWM0_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[48]:0 */ 1289 P7_3_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:0 */ 1290 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 1291 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 1292 P7_3_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:0 */ 1293 P7_3_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:0 */ 1294 1295 /* P7.4 */ 1296 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1297 P7_4_AMUXA = 4, /* Analog mux bus A */ 1298 P7_4_AMUXB = 5, /* Analog mux bus B */ 1299 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1300 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1301 P7_4_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:0 */ 1302 P7_4_TCPWM0_LINE_COMPL16 = 9, /* Digital Active - tcpwm[0].line_compl[16]:0 */ 1303 P7_4_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:0 */ 1304 P7_4_TCPWM0_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[49]:0 */ 1305 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 1306 P7_4_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:0 */ 1307 P7_4_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:0 */ 1308 1309 /* P7.5 */ 1310 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1311 P7_5_AMUXA = 4, /* Analog mux bus A */ 1312 P7_5_AMUXB = 5, /* Analog mux bus B */ 1313 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1314 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1315 P7_5_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:0 */ 1316 P7_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 1317 P7_5_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:0 */ 1318 P7_5_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:0 */ 1319 P7_5_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:0 */ 1320 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 1321 P7_5_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:0 */ 1322 P7_5_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:0 */ 1323 1324 /* P7.6 */ 1325 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1326 P7_6_AMUXA = 4, /* Analog mux bus A */ 1327 P7_6_AMUXB = 5, /* Analog mux bus B */ 1328 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1329 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1330 P7_6_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:0 */ 1331 P7_6_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:0 */ 1332 P7_6_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:0 */ 1333 P7_6_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:0 */ 1334 P7_6_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:0 */ 1335 P7_6_PERI_TR_IO_INPUT16 = 26, /* Digital Active - peri.tr_io_input[16]:0 */ 1336 1337 /* P7.7 */ 1338 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1339 P7_7_AMUXA = 4, /* Analog mux bus A */ 1340 P7_7_AMUXB = 5, /* Analog mux bus B */ 1341 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1342 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1343 P7_7_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:0 */ 1344 P7_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ 1345 P7_7_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:0 */ 1346 P7_7_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:0 */ 1347 P7_7_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:0 */ 1348 P7_7_PERI_TR_IO_INPUT17 = 26, /* Digital Active - peri.tr_io_input[17]:0 */ 1349 1350 /* P8.0 */ 1351 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1352 P8_0_AMUXA = 4, /* Analog mux bus A */ 1353 P8_0_AMUXB = 5, /* Analog mux bus B */ 1354 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1355 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1356 P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ 1357 P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ 1358 P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ 1359 P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ 1360 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 1361 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 1362 P8_0_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:0 */ 1363 P8_0_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:0 */ 1364 1365 /* P8.1 */ 1366 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1367 P8_1_AMUXA = 4, /* Analog mux bus A */ 1368 P8_1_AMUXB = 5, /* Analog mux bus B */ 1369 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1370 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1371 P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 1372 P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ 1373 P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ 1374 P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ 1375 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 1376 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 1377 P8_1_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:0 */ 1378 P8_1_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:0 */ 1379 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 1380 1381 /* P8.2 */ 1382 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1383 P8_2_AMUXA = 4, /* Analog mux bus A */ 1384 P8_2_AMUXB = 5, /* Analog mux bus B */ 1385 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1386 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1387 P8_2_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ 1388 P8_2_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ 1389 P8_2_TCPWM0_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[63]:0 */ 1390 P8_2_TCPWM0_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[61]:0 */ 1391 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 1392 P8_2_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:0 */ 1393 P8_2_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:0 */ 1394 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 1395 1396 /* P8.3 */ 1397 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1398 P8_3_AMUXA = 4, /* Analog mux bus A */ 1399 P8_3_AMUXB = 5, /* Analog mux bus B */ 1400 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1401 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1402 P8_3_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:0 */ 1403 P8_3_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:0 */ 1404 P8_3_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:0 */ 1405 P8_3_TCPWM0_TR_ONE_CNT_IN64 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[64]:0 */ 1406 P8_3_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:1 */ 1407 1408 /* P9.0 */ 1409 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1410 P9_0_AMUXA = 4, /* Analog mux bus A */ 1411 P9_0_AMUXB = 5, /* Analog mux bus B */ 1412 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1413 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1414 P9_0_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:0 */ 1415 P9_0_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:0 */ 1416 P9_0_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:0 */ 1417 P9_0_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:0 */ 1418 1419 /* P9.1 */ 1420 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1421 P9_1_AMUXA = 4, /* Analog mux bus A */ 1422 P9_1_AMUXB = 5, /* Analog mux bus B */ 1423 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1424 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1425 P9_1_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:0 */ 1426 P9_1_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:0 */ 1427 P9_1_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:0 */ 1428 P9_1_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:0 */ 1429 P9_1_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:0 */ 1430 1431 /* P10.0 */ 1432 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1433 P10_0_AMUXA = 4, /* Analog mux bus A */ 1434 P10_0_AMUXB = 5, /* Analog mux bus B */ 1435 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1436 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1437 P10_0_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:0 */ 1438 P10_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:0 */ 1439 P10_0_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:0 */ 1440 P10_0_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:0 */ 1441 P10_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:1 */ 1442 P10_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:1 */ 1443 P10_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:2 */ 1444 P10_0_PERI_TR_IO_INPUT18 = 26, /* Digital Active - peri.tr_io_input[18]:0 */ 1445 1446 /* P10.1 */ 1447 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1448 P10_1_AMUXA = 4, /* Analog mux bus A */ 1449 P10_1_AMUXB = 5, /* Analog mux bus B */ 1450 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1451 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1452 P10_1_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:0 */ 1453 P10_1_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:0 */ 1454 P10_1_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:0 */ 1455 P10_1_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:0 */ 1456 P10_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:1 */ 1457 P10_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:1 */ 1458 P10_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:1 */ 1459 P10_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:2 */ 1460 P10_1_PERI_TR_IO_INPUT19 = 26, /* Digital Active - peri.tr_io_input[19]:0 */ 1461 1462 /* P10.2 */ 1463 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1464 P10_2_AMUXA = 4, /* Analog mux bus A */ 1465 P10_2_AMUXB = 5, /* Analog mux bus B */ 1466 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1467 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1468 P10_2_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:0 */ 1469 P10_2_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:0 */ 1470 P10_2_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:0 */ 1471 P10_2_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:0 */ 1472 P10_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:1 */ 1473 P10_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:1 */ 1474 P10_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:1 */ 1475 P10_2_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:1 */ 1476 1477 /* P10.3 */ 1478 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1479 P10_3_AMUXA = 4, /* Analog mux bus A */ 1480 P10_3_AMUXB = 5, /* Analog mux bus B */ 1481 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1482 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1483 P10_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:0 */ 1484 P10_3_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:0 */ 1485 P10_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:0 */ 1486 P10_3_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:0 */ 1487 P10_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:1 */ 1488 P10_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:1 */ 1489 P10_3_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:1 */ 1490 1491 /* P10.4 */ 1492 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1493 P10_4_AMUXA = 4, /* Analog mux bus A */ 1494 P10_4_AMUXB = 5, /* Analog mux bus B */ 1495 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1496 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1497 P10_4_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:0 */ 1498 P10_4_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:0 */ 1499 P10_4_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:0 */ 1500 P10_4_TCPWM0_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[94]:0 */ 1501 P10_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:1 */ 1502 P10_4_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:1 */ 1503 1504 /* P11.0 */ 1505 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1506 P11_0_AMUXA = 4, /* Analog mux bus A */ 1507 P11_0_AMUXB = 5, /* Analog mux bus B */ 1508 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1509 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1510 P11_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:2 */ 1511 P11_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:2 */ 1512 P11_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:2 */ 1513 P11_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:2 */ 1514 P11_0_AUDIOSS0_MCLK = 25, /* Digital Active - audioss[0].mclk:0 */ 1515 1516 /* P11.1 */ 1517 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1518 P11_1_AMUXA = 4, /* Analog mux bus A */ 1519 P11_1_AMUXB = 5, /* Analog mux bus B */ 1520 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1521 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1522 P11_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:2 */ 1523 P11_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:2 */ 1524 P11_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:2 */ 1525 P11_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:2 */ 1526 P11_1_AUDIOSS0_TX_SCK = 25, /* Digital Active - audioss[0].tx_sck:0 */ 1527 1528 /* P11.2 */ 1529 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1530 P11_2_AMUXA = 4, /* Analog mux bus A */ 1531 P11_2_AMUXB = 5, /* Analog mux bus B */ 1532 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1533 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1534 P11_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:2 */ 1535 P11_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:2 */ 1536 P11_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:2 */ 1537 P11_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:2 */ 1538 P11_2_AUDIOSS0_TX_WS = 25, /* Digital Active - audioss[0].tx_ws:0 */ 1539 1540 /* P12.0 */ 1541 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1542 P12_0_AMUXA = 4, /* Analog mux bus A */ 1543 P12_0_AMUXB = 5, /* Analog mux bus B */ 1544 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1545 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1546 P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 1547 P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ 1548 P12_0_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:0 */ 1549 P12_0_TCPWM0_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ 1550 P12_0_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:0 */ 1551 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 1552 P12_0_TCPWM0_LINE_COMPL35 = 23, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 1553 P12_0_AUDIOSS0_TX_SDO = 25, /* Digital Active - audioss[0].tx_sdo:0 */ 1554 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 1555 1556 /* P12.1 */ 1557 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1558 P12_1_AMUXA = 4, /* Analog mux bus A */ 1559 P12_1_AMUXB = 5, /* Analog mux bus B */ 1560 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1561 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1562 P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 1563 P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 1564 P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ 1565 P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ 1566 P12_1_SCB8_UART_TX = 17, /* Digital Active - scb[8].uart_tx:0 */ 1567 P12_1_SCB8_I2C_SDA = 18, /* Digital Active - scb[8].i2c_sda:0 */ 1568 P12_1_SCB8_SPI_MOSI = 19, /* Digital Active - scb[8].spi_mosi:0 */ 1569 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 1570 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 1571 P12_1_AUDIOSS0_CLK_I2S_IF = 25, /* Digital Active - audioss[0].clk_i2s_if:0 */ 1572 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 1573 1574 /* P12.2 */ 1575 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1576 P12_2_AMUXA = 4, /* Analog mux bus A */ 1577 P12_2_AMUXB = 5, /* Analog mux bus B */ 1578 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1579 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1580 P12_2_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:0 */ 1581 P12_2_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ 1582 P12_2_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:0 */ 1583 P12_2_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:0 */ 1584 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 1585 P12_2_SCB8_UART_RTS = 17, /* Digital Active - scb[8].uart_rts:0 */ 1586 P12_2_SCB8_I2C_SCL = 18, /* Digital Active - scb[8].i2c_scl:0 */ 1587 P12_2_SCB8_SPI_CLK = 19, /* Digital Active - scb[8].spi_clk:0 */ 1588 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 1589 P12_2_AUDIOSS0_RX_SCK = 25, /* Digital Active - audioss[0].rx_sck:0 */ 1590 1591 /* P12.3 */ 1592 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1593 P12_3_AMUXA = 4, /* Analog mux bus A */ 1594 P12_3_AMUXB = 5, /* Analog mux bus B */ 1595 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1596 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1597 P12_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:0 */ 1598 P12_3_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:0 */ 1599 P12_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:0 */ 1600 P12_3_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:0 */ 1601 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 1602 P12_3_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:0 */ 1603 P12_3_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:0 */ 1604 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 1605 P12_3_AUDIOSS0_RX_WS = 25, /* Digital Active - audioss[0].rx_ws:0 */ 1606 1607 /* P12.4 */ 1608 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1609 P12_4_AMUXA = 4, /* Analog mux bus A */ 1610 P12_4_AMUXB = 5, /* Analog mux bus B */ 1611 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1612 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1613 P12_4_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:0 */ 1614 P12_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:0 */ 1615 P12_4_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:0 */ 1616 P12_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:0 */ 1617 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 1618 P12_4_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:0 */ 1619 P12_4_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:2 */ 1620 P12_4_AUDIOSS0_RX_SDI = 25, /* Digital Active - audioss[0].rx_sdi:0 */ 1621 1622 /* P12.5 */ 1623 P12_5_GPIO = 0, /* GPIO controls 'out' */ 1624 P12_5_AMUXA = 4, /* Analog mux bus A */ 1625 P12_5_AMUXB = 5, /* Analog mux bus B */ 1626 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1627 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1628 P12_5_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:0 */ 1629 P12_5_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:0 */ 1630 P12_5_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:0 */ 1631 P12_5_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:0 */ 1632 P12_5_PASS0_SAR_EXT_MUX_SEL5 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[5] */ 1633 P12_5_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:2 */ 1634 1635 /* P13.0 */ 1636 P13_0_GPIO = 0, /* GPIO controls 'out' */ 1637 P13_0_AMUXA = 4, /* Analog mux bus A */ 1638 P13_0_AMUXB = 5, /* Analog mux bus B */ 1639 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1640 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1641 P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 1642 P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ 1643 P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ 1644 P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ 1645 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 1646 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 1647 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 1648 P13_0_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:0 */ 1649 P13_0_AUDIOSS1_MCLK = 25, /* Digital Active - audioss[1].mclk:0 */ 1650 1651 /* P13.1 */ 1652 P13_1_GPIO = 0, /* GPIO controls 'out' */ 1653 P13_1_AMUXA = 4, /* Analog mux bus A */ 1654 P13_1_AMUXB = 5, /* Analog mux bus B */ 1655 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1656 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1657 P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ 1658 P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 1659 P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ 1660 P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ 1661 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 1662 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 1663 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 1664 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 1665 P13_1_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:0 */ 1666 P13_1_AUDIOSS1_TX_SCK = 25, /* Digital Active - audioss[1].tx_sck:0 */ 1667 1668 /* P13.2 */ 1669 P13_2_GPIO = 0, /* GPIO controls 'out' */ 1670 P13_2_AMUXA = 4, /* Analog mux bus A */ 1671 P13_2_AMUXB = 5, /* Analog mux bus B */ 1672 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1673 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1674 P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 1675 P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ 1676 P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ 1677 P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ 1678 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 1679 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 1680 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 1681 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 1682 P13_2_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:0 */ 1683 P13_2_AUDIOSS1_TX_WS = 25, /* Digital Active - audioss[1].tx_ws:0 */ 1684 1685 /* P13.3 */ 1686 P13_3_GPIO = 0, /* GPIO controls 'out' */ 1687 P13_3_AMUXA = 4, /* Analog mux bus A */ 1688 P13_3_AMUXB = 5, /* Analog mux bus B */ 1689 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1690 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1691 P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ 1692 P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 1693 P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ 1694 P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ 1695 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 1696 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 1697 P13_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:2 */ 1698 P13_3_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:0 */ 1699 P13_3_AUDIOSS1_TX_SDO = 25, /* Digital Active - audioss[1].tx_sdo:0 */ 1700 1701 /* P13.4 */ 1702 P13_4_GPIO = 0, /* GPIO controls 'out' */ 1703 P13_4_AMUXA = 4, /* Analog mux bus A */ 1704 P13_4_AMUXB = 5, /* Analog mux bus B */ 1705 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1706 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1707 P13_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ 1708 P13_4_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:0 */ 1709 P13_4_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:0 */ 1710 P13_4_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:0 */ 1711 P13_4_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:1 */ 1712 P13_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:2 */ 1713 P13_4_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:0 */ 1714 P13_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:0 */ 1715 P13_4_AUDIOSS1_CLK_I2S_IF = 25, /* Digital Active - audioss[1].clk_i2s_if:0 */ 1716 1717 /* P13.5 */ 1718 P13_5_GPIO = 0, /* GPIO controls 'out' */ 1719 P13_5_AMUXA = 4, /* Analog mux bus A */ 1720 P13_5_AMUXB = 5, /* Analog mux bus B */ 1721 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1722 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1723 P13_5_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:0 */ 1724 P13_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ 1725 P13_5_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:0 */ 1726 P13_5_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:0 */ 1727 P13_5_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:1 */ 1728 P13_5_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:0 */ 1729 P13_5_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:0 */ 1730 P13_5_AUDIOSS1_RX_SCK = 25, /* Digital Active - audioss[1].rx_sck:0 */ 1731 1732 /* P13.6 */ 1733 P13_6_GPIO = 0, /* GPIO controls 'out' */ 1734 P13_6_AMUXA = 4, /* Analog mux bus A */ 1735 P13_6_AMUXB = 5, /* Analog mux bus B */ 1736 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1737 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1738 P13_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ 1739 P13_6_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:0 */ 1740 P13_6_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:0 */ 1741 P13_6_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:0 */ 1742 P13_6_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:1 */ 1743 P13_6_SCB3_SPI_SELECT3 = 21, /* Digital Active - scb[3].spi_select3:0 */ 1744 P13_6_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:0 */ 1745 P13_6_AUDIOSS1_RX_WS = 25, /* Digital Active - audioss[1].rx_ws:0 */ 1746 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 1747 1748 /* P13.7 */ 1749 P13_7_GPIO = 0, /* GPIO controls 'out' */ 1750 P13_7_AMUXA = 4, /* Analog mux bus A */ 1751 P13_7_AMUXB = 5, /* Analog mux bus B */ 1752 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1753 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1754 P13_7_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:0 */ 1755 P13_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ 1756 P13_7_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:0 */ 1757 P13_7_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:0 */ 1758 P13_7_TCPWM0_LINE_COMPL517 = 16, /* Digital Active - tcpwm[0].line_compl[517]:1 */ 1759 P13_7_AUDIOSS1_RX_SDI = 25, /* Digital Active - audioss[1].rx_sdi:0 */ 1760 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 1761 1762 /* P14.0 */ 1763 P14_0_GPIO = 0, /* GPIO controls 'out' */ 1764 P14_0_AMUXA = 4, /* Analog mux bus A */ 1765 P14_0_AMUXB = 5, /* Analog mux bus B */ 1766 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1767 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1768 P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ 1769 P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ 1770 P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ 1771 P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ 1772 P14_0_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:1 */ 1773 P14_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:0 */ 1774 P14_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:0 */ 1775 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 1776 P14_0_AUDIOSS2_MCLK = 25, /* Digital Active - audioss[2].mclk:0 */ 1777 1778 /* P14.1 */ 1779 P14_1_GPIO = 0, /* GPIO controls 'out' */ 1780 P14_1_AMUXA = 4, /* Analog mux bus A */ 1781 P14_1_AMUXB = 5, /* Analog mux bus B */ 1782 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1783 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1784 P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ 1785 P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ 1786 P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ 1787 P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ 1788 P14_1_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:1 */ 1789 P14_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:0 */ 1790 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 1791 P14_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:0 */ 1792 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 1793 P14_1_AUDIOSS2_TX_SCK = 25, /* Digital Active - audioss[2].tx_sck:0 */ 1794 1795 /* P14.4 */ 1796 P14_4_GPIO = 0, /* GPIO controls 'out' */ 1797 P14_4_AMUXA = 4, /* Analog mux bus A */ 1798 P14_4_AMUXB = 5, /* Analog mux bus B */ 1799 P14_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1800 P14_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1801 P14_4_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:0 */ 1802 P14_4_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:0 */ 1803 P14_4_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:0 */ 1804 P14_4_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:0 */ 1805 P14_4_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:1 */ 1806 P14_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:0 */ 1807 P14_4_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:1 */ 1808 P14_4_AUDIOSS2_TX_WS = 25, /* Digital Active - audioss[2].tx_ws:0 */ 1809 1810 /* P14.5 */ 1811 P14_5_GPIO = 0, /* GPIO controls 'out' */ 1812 P14_5_AMUXA = 4, /* Analog mux bus A */ 1813 P14_5_AMUXB = 5, /* Analog mux bus B */ 1814 P14_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1815 P14_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1816 P14_5_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:0 */ 1817 P14_5_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:0 */ 1818 P14_5_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:0 */ 1819 P14_5_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:0 */ 1820 P14_5_TCPWM0_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1549]:1 */ 1821 P14_5_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:0 */ 1822 P14_5_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:0 */ 1823 P14_5_AUDIOSS2_TX_SDO = 25, /* Digital Active - audioss[2].tx_sdo:0 */ 1824 1825 /* P15.0 */ 1826 P15_0_GPIO = 0, /* GPIO controls 'out' */ 1827 P15_0_AMUXA = 4, /* Analog mux bus A */ 1828 P15_0_AMUXB = 5, /* Analog mux bus B */ 1829 P15_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1830 P15_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1831 P15_0_TCPWM0_LINE56 = 8, /* Digital Active - tcpwm[0].line[56]:0 */ 1832 P15_0_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:0 */ 1833 P15_0_TCPWM0_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[168]:0 */ 1834 P15_0_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:0 */ 1835 P15_0_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:1 */ 1836 P15_0_SCB9_UART_RX = 17, /* Digital Active - scb[9].uart_rx:0 */ 1837 P15_0_SCB9_SPI_MISO = 19, /* Digital Active - scb[9].spi_miso:0 */ 1838 P15_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:1 */ 1839 P15_0_AUDIOSS2_CLK_I2S_IF = 25, /* Digital Active - audioss[2].clk_i2s_if:0 */ 1840 1841 /* P15.1 */ 1842 P15_1_GPIO = 0, /* GPIO controls 'out' */ 1843 P15_1_AMUXA = 4, /* Analog mux bus A */ 1844 P15_1_AMUXB = 5, /* Analog mux bus B */ 1845 P15_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1846 P15_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1847 P15_1_TCPWM0_LINE57 = 8, /* Digital Active - tcpwm[0].line[57]:0 */ 1848 P15_1_TCPWM0_LINE_COMPL56 = 9, /* Digital Active - tcpwm[0].line_compl[56]:0 */ 1849 P15_1_TCPWM0_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[171]:0 */ 1850 P15_1_TCPWM0_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[169]:0 */ 1851 P15_1_TCPWM0_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1555]:1 */ 1852 P15_1_SCB9_UART_TX = 17, /* Digital Active - scb[9].uart_tx:0 */ 1853 P15_1_SCB9_I2C_SDA = 18, /* Digital Active - scb[9].i2c_sda:0 */ 1854 P15_1_SCB9_SPI_MOSI = 19, /* Digital Active - scb[9].spi_mosi:0 */ 1855 P15_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:1 */ 1856 P15_1_AUDIOSS2_RX_SCK = 25, /* Digital Active - audioss[2].rx_sck:0 */ 1857 1858 /* P15.2 */ 1859 P15_2_GPIO = 0, /* GPIO controls 'out' */ 1860 P15_2_AMUXA = 4, /* Analog mux bus A */ 1861 P15_2_AMUXB = 5, /* Analog mux bus B */ 1862 P15_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1863 P15_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1864 P15_2_TCPWM0_LINE58 = 8, /* Digital Active - tcpwm[0].line[58]:0 */ 1865 P15_2_TCPWM0_LINE_COMPL57 = 9, /* Digital Active - tcpwm[0].line_compl[57]:0 */ 1866 P15_2_TCPWM0_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[174]:0 */ 1867 P15_2_TCPWM0_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[172]:0 */ 1868 P15_2_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:1 */ 1869 P15_2_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:0 */ 1870 P15_2_SCB9_I2C_SCL = 18, /* Digital Active - scb[9].i2c_scl:0 */ 1871 P15_2_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:0 */ 1872 P15_2_AUDIOSS2_RX_WS = 25, /* Digital Active - audioss[2].rx_ws:0 */ 1873 1874 /* P15.3 */ 1875 P15_3_GPIO = 0, /* GPIO controls 'out' */ 1876 P15_3_AMUXA = 4, /* Analog mux bus A */ 1877 P15_3_AMUXB = 5, /* Analog mux bus B */ 1878 P15_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1879 P15_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1880 P15_3_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:0 */ 1881 P15_3_TCPWM0_LINE_COMPL58 = 9, /* Digital Active - tcpwm[0].line_compl[58]:0 */ 1882 P15_3_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:0 */ 1883 P15_3_TCPWM0_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[175]:0 */ 1884 P15_3_TCPWM0_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1558]:1 */ 1885 P15_3_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:0 */ 1886 P15_3_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:0 */ 1887 P15_3_AUDIOSS2_RX_SDI = 25, /* Digital Active - audioss[2].rx_sdi:0 */ 1888 1889 /* P17.0 */ 1890 P17_0_GPIO = 0, /* GPIO controls 'out' */ 1891 P17_0_AMUXA = 4, /* Analog mux bus A */ 1892 P17_0_AMUXB = 5, /* Analog mux bus B */ 1893 P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1894 P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1895 P17_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:1 */ 1896 P17_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:1 */ 1897 P17_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:1 */ 1898 P17_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:1 */ 1899 P17_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:2 */ 1900 P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ 1901 1902 /* P17.1 */ 1903 P17_1_GPIO = 0, /* GPIO controls 'out' */ 1904 P17_1_AMUXA = 4, /* Analog mux bus A */ 1905 P17_1_AMUXB = 5, /* Analog mux bus B */ 1906 P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1907 P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1908 P17_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:1 */ 1909 P17_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:1 */ 1910 P17_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:1 */ 1911 P17_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:1 */ 1912 P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ 1913 P17_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:2 */ 1914 P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ 1915 1916 /* P17.2 */ 1917 P17_2_GPIO = 0, /* GPIO controls 'out' */ 1918 P17_2_AMUXA = 4, /* Analog mux bus A */ 1919 P17_2_AMUXB = 5, /* Analog mux bus B */ 1920 P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1921 P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1922 P17_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:1 */ 1923 P17_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:1 */ 1924 P17_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:1 */ 1925 P17_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:1 */ 1926 P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ 1927 P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ 1928 P17_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:2 */ 1929 1930 /* P17.3 */ 1931 P17_3_GPIO = 0, /* GPIO controls 'out' */ 1932 P17_3_AMUXA = 4, /* Analog mux bus A */ 1933 P17_3_AMUXB = 5, /* Analog mux bus B */ 1934 P17_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1935 P17_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1936 P17_3_TCPWM0_LINE58 = 8, /* Digital Active - tcpwm[0].line[58]:1 */ 1937 P17_3_TCPWM0_LINE_COMPL59 = 9, /* Digital Active - tcpwm[0].line_compl[59]:1 */ 1938 P17_3_TCPWM0_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[174]:1 */ 1939 P17_3_TCPWM0_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[178]:1 */ 1940 P17_3_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:1 */ 1941 P17_3_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:1 */ 1942 P17_3_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:1 */ 1943 P17_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:1 */ 1944 P17_3_PERI_TR_IO_INPUT26 = 26, /* Digital Active - peri.tr_io_input[26]:0 */ 1945 1946 /* P17.4 */ 1947 P17_4_GPIO = 0, /* GPIO controls 'out' */ 1948 P17_4_AMUXA = 4, /* Analog mux bus A */ 1949 P17_4_AMUXB = 5, /* Analog mux bus B */ 1950 P17_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1951 P17_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1952 P17_4_TCPWM0_LINE57 = 8, /* Digital Active - tcpwm[0].line[57]:1 */ 1953 P17_4_TCPWM0_LINE_COMPL58 = 9, /* Digital Active - tcpwm[0].line_compl[58]:1 */ 1954 P17_4_TCPWM0_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[171]:1 */ 1955 P17_4_TCPWM0_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[175]:1 */ 1956 P17_4_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:1 */ 1957 P17_4_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:1 */ 1958 P17_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:1 */ 1959 P17_4_PERI_TR_IO_INPUT27 = 26, /* Digital Active - peri.tr_io_input[27]:0 */ 1960 1961 /* P18.0 */ 1962 P18_0_GPIO = 0, /* GPIO controls 'out' */ 1963 P18_0_AMUXA = 4, /* Analog mux bus A */ 1964 P18_0_AMUXB = 5, /* Analog mux bus B */ 1965 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1966 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1967 P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ 1968 P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 1969 P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ 1970 P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ 1971 P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ 1972 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 1973 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 1974 P18_0_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:1 */ 1975 P18_0_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk:0 */ 1976 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 1977 1978 /* P18.1 */ 1979 P18_1_GPIO = 0, /* GPIO controls 'out' */ 1980 P18_1_AMUXA = 4, /* Analog mux bus A */ 1981 P18_1_AMUXB = 5, /* Analog mux bus B */ 1982 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1983 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1984 P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ 1985 P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 1986 P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ 1987 P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ 1988 P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ 1989 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 1990 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 1991 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 1992 P18_1_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:1 */ 1993 P18_1_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl:0 */ 1994 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 1995 1996 /* P18.2 */ 1997 P18_2_GPIO = 0, /* GPIO controls 'out' */ 1998 P18_2_AMUXA = 4, /* Analog mux bus A */ 1999 P18_2_AMUXB = 5, /* Analog mux bus B */ 2000 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2001 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2002 P18_2_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:1 */ 2003 P18_2_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 2004 P18_2_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:1 */ 2005 P18_2_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:1 */ 2006 P18_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:0 */ 2007 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 2008 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 2009 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 2010 P18_2_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:1 */ 2011 P18_2_ETH0_TX_ER = 24, /* Digital Active - eth[0].tx_er:0 */ 2012 2013 /* P18.3 */ 2014 P18_3_GPIO = 0, /* GPIO controls 'out' */ 2015 P18_3_AMUXA = 4, /* Analog mux bus A */ 2016 P18_3_AMUXB = 5, /* Analog mux bus B */ 2017 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2018 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2019 P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ 2020 P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ 2021 P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ 2022 P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ 2023 P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ 2024 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 2025 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 2026 P18_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:2 */ 2027 P18_3_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk:0 */ 2028 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 2029 2030 /* P18.4 */ 2031 P18_4_GPIO = 0, /* GPIO controls 'out' */ 2032 P18_4_AMUXA = 4, /* Analog mux bus A */ 2033 P18_4_AMUXB = 5, /* Analog mux bus B */ 2034 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2035 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2036 P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ 2037 P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ 2038 P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ 2039 P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ 2040 P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ 2041 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 2042 P18_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:2 */ 2043 P18_4_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0]:0 */ 2044 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 2045 2046 /* P18.5 */ 2047 P18_5_GPIO = 0, /* GPIO controls 'out' */ 2048 P18_5_AMUXA = 4, /* Analog mux bus A */ 2049 P18_5_AMUXB = 5, /* Analog mux bus B */ 2050 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2051 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2052 P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ 2053 P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ 2054 P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ 2055 P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ 2056 P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ 2057 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 2058 P18_5_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1]:0 */ 2059 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 2060 2061 /* P18.6 */ 2062 P18_6_GPIO = 0, /* GPIO controls 'out' */ 2063 P18_6_AMUXA = 4, /* Analog mux bus A */ 2064 P18_6_AMUXB = 5, /* Analog mux bus B */ 2065 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2066 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2067 P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ 2068 P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ 2069 P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ 2070 P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ 2071 P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ 2072 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 2073 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 2074 P18_6_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2]:0 */ 2075 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 2076 2077 /* P18.7 */ 2078 P18_7_GPIO = 0, /* GPIO controls 'out' */ 2079 P18_7_AMUXA = 4, /* Analog mux bus A */ 2080 P18_7_AMUXB = 5, /* Analog mux bus B */ 2081 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2082 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2083 P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ 2084 P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ 2085 P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ 2086 P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ 2087 P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ 2088 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 2089 P18_7_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3]:0 */ 2090 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 2091 2092 /* P19.0 */ 2093 P19_0_GPIO = 0, /* GPIO controls 'out' */ 2094 P19_0_AMUXA = 4, /* Analog mux bus A */ 2095 P19_0_AMUXB = 5, /* Analog mux bus B */ 2096 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2097 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2098 P19_0_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:2 */ 2099 P19_0_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:1 */ 2100 P19_0_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:2 */ 2101 P19_0_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:1 */ 2102 P19_0_TCPWM0_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536]:0 */ 2103 P19_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:1 */ 2104 P19_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:1 */ 2105 P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ 2106 P19_0_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0]:0 */ 2107 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 2108 2109 /* P19.1 */ 2110 P19_1_GPIO = 0, /* GPIO controls 'out' */ 2111 P19_1_AMUXA = 4, /* Analog mux bus A */ 2112 P19_1_AMUXB = 5, /* Analog mux bus B */ 2113 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2114 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2115 P19_1_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ 2116 P19_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 2117 P19_1_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:1 */ 2118 P19_1_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:2 */ 2119 P19_1_TCPWM0_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537]:0 */ 2120 P19_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:1 */ 2121 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 2122 P19_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:1 */ 2123 P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ 2124 P19_1_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1]:0 */ 2125 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 2126 2127 /* P19.2 */ 2128 P19_2_GPIO = 0, /* GPIO controls 'out' */ 2129 P19_2_AMUXA = 4, /* Analog mux bus A */ 2130 P19_2_AMUXB = 5, /* Analog mux bus B */ 2131 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2132 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2133 P19_2_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:2 */ 2134 P19_2_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:1 */ 2135 P19_2_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:2 */ 2136 P19_2_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:1 */ 2137 P19_2_TCPWM0_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539]:0 */ 2138 P19_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:1 */ 2139 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 2140 P19_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:1 */ 2141 P19_2_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2]:0 */ 2142 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 2143 2144 /* P19.3 */ 2145 P19_3_GPIO = 0, /* GPIO controls 'out' */ 2146 P19_3_AMUXA = 4, /* Analog mux bus A */ 2147 P19_3_AMUXB = 5, /* Analog mux bus B */ 2148 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2149 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2150 P19_3_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:2 */ 2151 P19_3_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:2 */ 2152 P19_3_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:2 */ 2153 P19_3_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:2 */ 2154 P19_3_TCPWM0_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540]:0 */ 2155 P19_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:1 */ 2156 P19_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:1 */ 2157 P19_3_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3]:0 */ 2158 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 2159 2160 /* P19.4 */ 2161 P19_4_GPIO = 0, /* GPIO controls 'out' */ 2162 P19_4_AMUXA = 4, /* Analog mux bus A */ 2163 P19_4_AMUXB = 5, /* Analog mux bus B */ 2164 P19_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2165 P19_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2166 P19_4_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:2 */ 2167 P19_4_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:2 */ 2168 P19_4_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:2 */ 2169 P19_4_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:2 */ 2170 P19_4_TCPWM0_TR_ONE_CNT_IN1542 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1542]:0 */ 2171 P19_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:1 */ 2172 2173 /* P20.0 */ 2174 P20_0_GPIO = 0, /* GPIO controls 'out' */ 2175 P20_0_AMUXA = 4, /* Analog mux bus A */ 2176 P20_0_AMUXB = 5, /* Analog mux bus B */ 2177 P20_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2178 P20_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2179 P20_0_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:2 */ 2180 P20_0_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:2 */ 2181 P20_0_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:2 */ 2182 P20_0_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:2 */ 2183 P20_0_TCPWM0_TR_ONE_CNT_IN1543 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1543]:0 */ 2184 P20_0_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:1 */ 2185 P20_0_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:0 */ 2186 2187 /* P20.1 */ 2188 P20_1_GPIO = 0, /* GPIO controls 'out' */ 2189 P20_1_AMUXA = 4, /* Analog mux bus A */ 2190 P20_1_AMUXB = 5, /* Analog mux bus B */ 2191 P20_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2192 P20_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2193 P20_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:1 */ 2194 P20_1_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:2 */ 2195 P20_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:1 */ 2196 P20_1_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:2 */ 2197 P20_1_TCPWM0_TR_ONE_CNT_IN1545 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1545]:0 */ 2198 P20_1_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:0 */ 2199 2200 /* P20.2 */ 2201 P20_2_GPIO = 0, /* GPIO controls 'out' */ 2202 P20_2_AMUXA = 4, /* Analog mux bus A */ 2203 P20_2_AMUXB = 5, /* Analog mux bus B */ 2204 P20_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2205 P20_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2206 P20_2_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:1 */ 2207 P20_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:1 */ 2208 P20_2_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:1 */ 2209 P20_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:1 */ 2210 P20_2_TCPWM0_TR_ONE_CNT_IN1546 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1546]:0 */ 2211 P20_2_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:0 */ 2212 2213 /* P20.3 */ 2214 P20_3_GPIO = 0, /* GPIO controls 'out' */ 2215 P20_3_AMUXA = 4, /* Analog mux bus A */ 2216 P20_3_AMUXB = 5, /* Analog mux bus B */ 2217 P20_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2218 P20_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2219 P20_3_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:1 */ 2220 P20_3_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:1 */ 2221 P20_3_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:1 */ 2222 P20_3_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:1 */ 2223 P20_3_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:1 */ 2224 P20_3_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:1 */ 2225 P20_3_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:1 */ 2226 2227 /* P21.0 */ 2228 P21_0_GPIO = 0, /* GPIO controls 'out' */ 2229 P21_0_AMUXA = 4, /* Analog mux bus A */ 2230 P21_0_AMUXB = 5, /* Analog mux bus B */ 2231 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2232 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2233 P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ 2234 P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ 2235 P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ 2236 P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ 2237 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 2238 2239 /* P21.1 */ 2240 P21_1_GPIO = 0, /* GPIO controls 'out' */ 2241 P21_1_AMUXA = 4, /* Analog mux bus A */ 2242 P21_1_AMUXB = 5, /* Analog mux bus B */ 2243 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2244 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2245 P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ 2246 P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ 2247 P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ 2248 P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ 2249 2250 /* P21.2 */ 2251 P21_2_GPIO = 0, /* GPIO controls 'out' */ 2252 P21_2_AMUXA = 4, /* Analog mux bus A */ 2253 P21_2_AMUXB = 5, /* Analog mux bus B */ 2254 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2255 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2256 P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ 2257 P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ 2258 P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ 2259 P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ 2260 P21_2_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:0 */ 2261 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 2262 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 2263 2264 /* P21.3 */ 2265 P21_3_GPIO = 0, /* GPIO controls 'out' */ 2266 P21_3_AMUXA = 4, /* Analog mux bus A */ 2267 P21_3_AMUXB = 5, /* Analog mux bus B */ 2268 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2269 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2270 P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ 2271 P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ 2272 P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ 2273 P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ 2274 2275 /* P21.5 */ 2276 P21_5_GPIO = 0, /* GPIO controls 'out' */ 2277 P21_5_AMUXA = 4, /* Analog mux bus A */ 2278 P21_5_AMUXB = 5, /* Analog mux bus B */ 2279 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2280 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2281 P21_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:1 */ 2282 P21_5_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:1 */ 2283 P21_5_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:1 */ 2284 P21_5_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:1 */ 2285 P21_5_TCPWM0_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ 2286 P21_5_TCPWM0_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ 2287 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 2288 P21_5_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 2289 P21_5_TCPWM0_LINE34 = 22, /* Digital Active - tcpwm[0].line[34]:1 */ 2290 P21_5_TCPWM0_LINE_COMPL35 = 23, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 2291 P21_5_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl:0 */ 2292 P21_5_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 2293 2294 /* P21.6 */ 2295 P21_6_GPIO = 0, /* GPIO controls 'out' */ 2296 P21_6_AMUXA = 4, /* Analog mux bus A */ 2297 P21_6_AMUXB = 5, /* Analog mux bus B */ 2298 P21_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2299 P21_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2300 P21_6_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:1 */ 2301 P21_6_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:1 */ 2302 P21_6_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:1 */ 2303 P21_6_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:1 */ 2304 P21_6_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:1 */ 2305 P21_6_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:1 */ 2306 P21_6_CPUSS_CLK_FM_PUMP = 26, /* Digital Active - cpuss.clk_fm_pump */ 2307 2308 /* P22.1 */ 2309 P22_1_GPIO = 0, /* GPIO controls 'out' */ 2310 P22_1_AMUXA = 4, /* Analog mux bus A */ 2311 P22_1_AMUXB = 5, /* Analog mux bus B */ 2312 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2313 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2314 P22_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ 2315 P22_1_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ 2316 P22_1_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:1 */ 2317 P22_1_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:1 */ 2318 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 2319 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 2320 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 2321 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 2322 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 2323 2324 /* P22.2 */ 2325 P22_2_GPIO = 0, /* GPIO controls 'out' */ 2326 P22_2_AMUXA = 4, /* Analog mux bus A */ 2327 P22_2_AMUXB = 5, /* Analog mux bus B */ 2328 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2329 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2330 P22_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:1 */ 2331 P22_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:1 */ 2332 P22_2_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:1 */ 2333 P22_2_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:1 */ 2334 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 2335 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 2336 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 2337 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 2338 2339 /* P22.3 */ 2340 P22_3_GPIO = 0, /* GPIO controls 'out' */ 2341 P22_3_AMUXA = 4, /* Analog mux bus A */ 2342 P22_3_AMUXB = 5, /* Analog mux bus B */ 2343 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2344 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2345 P22_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:1 */ 2346 P22_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:1 */ 2347 P22_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:1 */ 2348 P22_3_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:1 */ 2349 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 2350 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 2351 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 2352 2353 /* P22.4 */ 2354 P22_4_GPIO = 0, /* GPIO controls 'out' */ 2355 P22_4_AMUXA = 4, /* Analog mux bus A */ 2356 P22_4_AMUXB = 5, /* Analog mux bus B */ 2357 P22_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2358 P22_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2359 P22_4_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:1 */ 2360 P22_4_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:1 */ 2361 P22_4_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:1 */ 2362 P22_4_TCPWM0_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[94]:1 */ 2363 P22_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:1 */ 2364 P22_4_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:1 */ 2365 2366 /* P22.5 */ 2367 P22_5_GPIO = 0, /* GPIO controls 'out' */ 2368 P22_5_AMUXA = 4, /* Analog mux bus A */ 2369 P22_5_AMUXB = 5, /* Analog mux bus B */ 2370 P22_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2371 P22_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2372 P22_5_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:1 */ 2373 P22_5_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:1 */ 2374 P22_5_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:1 */ 2375 P22_5_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:1 */ 2376 P22_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:1 */ 2377 P22_5_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:1 */ 2378 2379 /* P22.6 */ 2380 P22_6_GPIO = 0, /* GPIO controls 'out' */ 2381 P22_6_AMUXA = 4, /* Analog mux bus A */ 2382 P22_6_AMUXB = 5, /* Analog mux bus B */ 2383 P22_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2384 P22_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2385 P22_6_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:1 */ 2386 P22_6_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:1 */ 2387 P22_6_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:1 */ 2388 P22_6_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:1 */ 2389 P22_6_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:1 */ 2390 2391 /* P23.0 */ 2392 P23_0_GPIO = 0, /* GPIO controls 'out' */ 2393 P23_0_AMUXA = 4, /* Analog mux bus A */ 2394 P23_0_AMUXB = 5, /* Analog mux bus B */ 2395 P23_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2396 P23_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2397 P23_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:1 */ 2398 P23_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:1 */ 2399 P23_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:1 */ 2400 P23_0_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:1 */ 2401 P23_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:1 */ 2402 P23_0_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:1 */ 2403 P23_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:1 */ 2404 P23_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:1 */ 2405 P23_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:1 */ 2406 2407 /* P23.1 */ 2408 P23_1_GPIO = 0, /* GPIO controls 'out' */ 2409 P23_1_AMUXA = 4, /* Analog mux bus A */ 2410 P23_1_AMUXB = 5, /* Analog mux bus B */ 2411 P23_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2412 P23_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2413 P23_1_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:1 */ 2414 P23_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:1 */ 2415 P23_1_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:1 */ 2416 P23_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:1 */ 2417 P23_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:1 */ 2418 P23_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:1 */ 2419 P23_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:1 */ 2420 P23_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:1 */ 2421 P23_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:1 */ 2422 2423 /* P23.3 */ 2424 P23_3_GPIO = 0, /* GPIO controls 'out' */ 2425 P23_3_AMUXA = 4, /* Analog mux bus A */ 2426 P23_3_AMUXB = 5, /* Analog mux bus B */ 2427 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2428 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2429 P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ 2430 P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ 2431 P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ 2432 P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ 2433 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 2434 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 2435 P23_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:2 */ 2436 P23_3_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk:0 */ 2437 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 2438 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 2439 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 2440 2441 /* P23.4 */ 2442 P23_4_GPIO = 0, /* GPIO controls 'out' */ 2443 P23_4_AMUXA = 4, /* Analog mux bus A */ 2444 P23_4_AMUXB = 5, /* Analog mux bus B */ 2445 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2446 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2447 P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 2448 P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ 2449 P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ 2450 P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ 2451 P23_4_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:2 */ 2452 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 2453 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 2454 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 2455 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 2456 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 2457 2458 /* P23.5 */ 2459 P23_5_GPIO = 0, /* GPIO controls 'out' */ 2460 P23_5_AMUXA = 4, /* Analog mux bus A */ 2461 P23_5_AMUXB = 5, /* Analog mux bus B */ 2462 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2463 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2464 P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 2465 P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 2466 P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ 2467 P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ 2468 P23_5_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:2 */ 2469 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 2470 P23_5_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:0 */ 2471 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 2472 2473 /* P23.6 */ 2474 P23_6_GPIO = 0, /* GPIO controls 'out' */ 2475 P23_6_AMUXA = 4, /* Analog mux bus A */ 2476 P23_6_AMUXB = 5, /* Analog mux bus B */ 2477 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2478 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2479 P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 2480 P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 2481 P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ 2482 P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ 2483 P23_6_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:2 */ 2484 P23_6_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:0 */ 2485 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 2486 2487 /* P23.7 */ 2488 P23_7_GPIO = 0, /* GPIO controls 'out' */ 2489 P23_7_AMUXA = 4, /* Analog mux bus A */ 2490 P23_7_AMUXB = 5, /* Analog mux bus B */ 2491 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2492 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2493 P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 2494 P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 2495 P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ 2496 P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ 2497 P23_7_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:2 */ 2498 P23_7_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:1 */ 2499 P23_7_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:0 */ 2500 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 2501 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 2502 P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 2503 } en_hsiom_sel_t; 2504 2505 #endif /* _GPIO_XMC7100_144_TEQFP_H_ */ 2506 2507 2508 /* [] END OF FILE */ 2509
