1 /***************************************************************************//** 2 * \file cyip_fault.h 3 * 4 * \brief 5 * FAULT IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_FAULT_H_ 28 #define _CYIP_FAULT_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * FAULT 34 *******************************************************************************/ 35 36 #define FAULT_STRUCT_SECTION_SIZE 0x00000100UL 37 #define FAULT_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Fault structure (FAULT_STRUCT) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Fault control */ 44 __IM uint32_t RESERVED[2]; 45 __IOM uint32_t STATUS; /*!< 0x0000000C Fault status */ 46 __IM uint32_t DATA[4]; /*!< 0x00000010 Fault data */ 47 __IM uint32_t RESERVED1[8]; 48 __IM uint32_t PENDING0; /*!< 0x00000040 Fault pending 0 */ 49 __IM uint32_t PENDING1; /*!< 0x00000044 Fault pending 1 */ 50 __IM uint32_t PENDING2; /*!< 0x00000048 Fault pending 2 */ 51 __IM uint32_t RESERVED2; 52 __IOM uint32_t MASK0; /*!< 0x00000050 Fault mask 0 */ 53 __IOM uint32_t MASK1; /*!< 0x00000054 Fault mask 1 */ 54 __IOM uint32_t MASK2; /*!< 0x00000058 Fault mask 2 */ 55 __IM uint32_t RESERVED3[25]; 56 __IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */ 57 __IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */ 58 __IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */ 59 __IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */ 60 __IM uint32_t RESERVED4[12]; 61 } FAULT_STRUCT_V1_Type; /*!< Size = 256 (0x100) */ 62 63 /** 64 * \brief Fault structures (FAULT) 65 */ 66 typedef struct { 67 FAULT_STRUCT_V1_Type STRUCT[4]; /*!< 0x00000000 Fault structure */ 68 } FAULT_V1_Type; /*!< Size = 1024 (0x400) */ 69 70 71 /* FAULT_STRUCT.CTL */ 72 #define FAULT_STRUCT_CTL_TR_EN_Pos 0UL 73 #define FAULT_STRUCT_CTL_TR_EN_Msk 0x1UL 74 #define FAULT_STRUCT_CTL_OUT_EN_Pos 1UL 75 #define FAULT_STRUCT_CTL_OUT_EN_Msk 0x2UL 76 #define FAULT_STRUCT_CTL_RESET_REQ_EN_Pos 2UL 77 #define FAULT_STRUCT_CTL_RESET_REQ_EN_Msk 0x4UL 78 /* FAULT_STRUCT.STATUS */ 79 #define FAULT_STRUCT_STATUS_IDX_Pos 0UL 80 #define FAULT_STRUCT_STATUS_IDX_Msk 0x7FUL 81 #define FAULT_STRUCT_STATUS_VALID_Pos 31UL 82 #define FAULT_STRUCT_STATUS_VALID_Msk 0x80000000UL 83 /* FAULT_STRUCT.DATA */ 84 #define FAULT_STRUCT_DATA_DATA_Pos 0UL 85 #define FAULT_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL 86 /* FAULT_STRUCT.PENDING0 */ 87 #define FAULT_STRUCT_PENDING0_SOURCE_Pos 0UL 88 #define FAULT_STRUCT_PENDING0_SOURCE_Msk 0xFFFFFFFFUL 89 /* FAULT_STRUCT.PENDING1 */ 90 #define FAULT_STRUCT_PENDING1_SOURCE_Pos 0UL 91 #define FAULT_STRUCT_PENDING1_SOURCE_Msk 0xFFFFFFFFUL 92 /* FAULT_STRUCT.PENDING2 */ 93 #define FAULT_STRUCT_PENDING2_SOURCE_Pos 0UL 94 #define FAULT_STRUCT_PENDING2_SOURCE_Msk 0xFFFFFFFFUL 95 /* FAULT_STRUCT.MASK0 */ 96 #define FAULT_STRUCT_MASK0_SOURCE_Pos 0UL 97 #define FAULT_STRUCT_MASK0_SOURCE_Msk 0xFFFFFFFFUL 98 /* FAULT_STRUCT.MASK1 */ 99 #define FAULT_STRUCT_MASK1_SOURCE_Pos 0UL 100 #define FAULT_STRUCT_MASK1_SOURCE_Msk 0xFFFFFFFFUL 101 /* FAULT_STRUCT.MASK2 */ 102 #define FAULT_STRUCT_MASK2_SOURCE_Pos 0UL 103 #define FAULT_STRUCT_MASK2_SOURCE_Msk 0xFFFFFFFFUL 104 /* FAULT_STRUCT.INTR */ 105 #define FAULT_STRUCT_INTR_FAULT_Pos 0UL 106 #define FAULT_STRUCT_INTR_FAULT_Msk 0x1UL 107 /* FAULT_STRUCT.INTR_SET */ 108 #define FAULT_STRUCT_INTR_SET_FAULT_Pos 0UL 109 #define FAULT_STRUCT_INTR_SET_FAULT_Msk 0x1UL 110 /* FAULT_STRUCT.INTR_MASK */ 111 #define FAULT_STRUCT_INTR_MASK_FAULT_Pos 0UL 112 #define FAULT_STRUCT_INTR_MASK_FAULT_Msk 0x1UL 113 /* FAULT_STRUCT.INTR_MASKED */ 114 #define FAULT_STRUCT_INTR_MASKED_FAULT_Pos 0UL 115 #define FAULT_STRUCT_INTR_MASKED_FAULT_Msk 0x1UL 116 117 118 #endif /* _CYIP_FAULT_H_ */ 119 120 121 /* [] END OF FILE */ 122
