1 /***************************************************************************//** 2 * \file gpio_psoc6_03_68_qfn.h 3 * 4 * \brief 5 * PSoC6_03 device GPIO header for 68-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_03_68_QFN_H_ 28 #define _GPIO_PSOC6_03_68_QFN_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN 44 #define CY_GPIO_PIN_COUNT 68u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ANALOG_VDDD, 50 AMUXBUS_CSD0, 51 AMUXBUS_CSD1, 52 AMUXBUS_SAR, 53 AMUXBUS_VDDIO_1, 54 AMUXBUS_VSSA, 55 AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, 56 AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, 57 }; 58 59 /* AMUX Splitter Controls */ 60 typedef enum 61 { 62 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 63 AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 64 } cy_en_amux_split_t; 65 66 /* Port List */ 67 /* PORT 0 (GPIO) */ 68 #define P0_0_PORT GPIO_PRT0 69 #define P0_0_PIN 0u 70 #define P0_0_NUM 0u 71 #define P0_1_PORT GPIO_PRT0 72 #define P0_1_PIN 1u 73 #define P0_1_NUM 1u 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_3_PORT GPIO_PRT0 78 #define P0_3_PIN 3u 79 #define P0_3_NUM 3u 80 #define P0_4_PORT GPIO_PRT0 81 #define P0_4_PIN 4u 82 #define P0_4_NUM 4u 83 #define P0_5_PORT GPIO_PRT0 84 #define P0_5_PIN 5u 85 #define P0_5_NUM 5u 86 87 /* PORT 2 (GPIO) */ 88 #define P2_0_PORT GPIO_PRT2 89 #define P2_0_PIN 0u 90 #define P2_0_NUM 0u 91 #define P2_1_PORT GPIO_PRT2 92 #define P2_1_PIN 1u 93 #define P2_1_NUM 1u 94 #define P2_2_PORT GPIO_PRT2 95 #define P2_2_PIN 2u 96 #define P2_2_NUM 2u 97 #define P2_3_PORT GPIO_PRT2 98 #define P2_3_PIN 3u 99 #define P2_3_NUM 3u 100 #define P2_4_PORT GPIO_PRT2 101 #define P2_4_PIN 4u 102 #define P2_4_NUM 4u 103 #define P2_5_PORT GPIO_PRT2 104 #define P2_5_PIN 5u 105 #define P2_5_NUM 5u 106 #define P2_6_PORT GPIO_PRT2 107 #define P2_6_PIN 6u 108 #define P2_6_NUM 6u 109 #define P2_7_PORT GPIO_PRT2 110 #define P2_7_PIN 7u 111 #define P2_7_NUM 7u 112 113 /* PORT 3 (GPIO_OVT) */ 114 #define P3_0_PORT GPIO_PRT3 115 #define P3_0_PIN 0u 116 #define P3_0_NUM 0u 117 #define P3_0_AMUXSEGMENT AMUXBUS_VSSA 118 #define P3_1_PORT GPIO_PRT3 119 #define P3_1_PIN 1u 120 #define P3_1_NUM 1u 121 #define P3_1_AMUXSEGMENT AMUXBUS_VSSA 122 123 /* PORT 5 (GPIO) */ 124 #define P5_0_PORT GPIO_PRT5 125 #define P5_0_PIN 0u 126 #define P5_0_NUM 0u 127 #define P5_1_PORT GPIO_PRT5 128 #define P5_1_PIN 1u 129 #define P5_1_NUM 1u 130 #define P5_6_PORT GPIO_PRT5 131 #define P5_6_PIN 6u 132 #define P5_6_NUM 6u 133 #define P5_7_PORT GPIO_PRT5 134 #define P5_7_PIN 7u 135 #define P5_7_NUM 7u 136 137 /* PORT 6 (GPIO) */ 138 #define P6_2_PORT GPIO_PRT6 139 #define P6_2_PIN 2u 140 #define P6_2_NUM 2u 141 #define P6_3_PORT GPIO_PRT6 142 #define P6_3_PIN 3u 143 #define P6_3_NUM 3u 144 #define P6_4_PORT GPIO_PRT6 145 #define P6_4_PIN 4u 146 #define P6_4_NUM 4u 147 #define P6_5_PORT GPIO_PRT6 148 #define P6_5_PIN 5u 149 #define P6_5_NUM 5u 150 #define P6_6_PORT GPIO_PRT6 151 #define P6_6_PIN 6u 152 #define P6_6_NUM 6u 153 #define P6_7_PORT GPIO_PRT6 154 #define P6_7_PIN 7u 155 #define P6_7_NUM 7u 156 157 /* PORT 7 (GPIO) */ 158 #define P7_0_PORT GPIO_PRT7 159 #define P7_0_PIN 0u 160 #define P7_0_NUM 0u 161 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 162 #define P7_1_PORT GPIO_PRT7 163 #define P7_1_PIN 1u 164 #define P7_1_NUM 1u 165 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 166 #define P7_2_PORT GPIO_PRT7 167 #define P7_2_PIN 2u 168 #define P7_2_NUM 2u 169 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 170 #define P7_3_PORT GPIO_PRT7 171 #define P7_3_PIN 3u 172 #define P7_3_NUM 3u 173 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 174 #define P7_7_PORT GPIO_PRT7 175 #define P7_7_PIN 7u 176 #define P7_7_NUM 7u 177 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 178 179 /* PORT 8 (GPIO) */ 180 #define P8_0_PORT GPIO_PRT8 181 #define P8_0_PIN 0u 182 #define P8_0_NUM 0u 183 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 184 #define P8_1_PORT GPIO_PRT8 185 #define P8_1_PIN 1u 186 #define P8_1_NUM 1u 187 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 188 189 /* PORT 9 (GPIO) */ 190 #define P9_0_PORT GPIO_PRT9 191 #define P9_0_PIN 0u 192 #define P9_0_NUM 0u 193 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 194 #define P9_1_PORT GPIO_PRT9 195 #define P9_1_PIN 1u 196 #define P9_1_NUM 1u 197 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 198 #define P9_2_PORT GPIO_PRT9 199 #define P9_2_PIN 2u 200 #define P9_2_NUM 2u 201 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 202 #define P9_3_PORT GPIO_PRT9 203 #define P9_3_PIN 3u 204 #define P9_3_NUM 3u 205 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 206 207 /* PORT 10 (GPIO) */ 208 #define P10_0_PORT GPIO_PRT10 209 #define P10_0_PIN 0u 210 #define P10_0_NUM 0u 211 #define P10_1_PORT GPIO_PRT10 212 #define P10_1_PIN 1u 213 #define P10_1_NUM 1u 214 #define P10_2_PORT GPIO_PRT10 215 #define P10_2_PIN 2u 216 #define P10_2_NUM 2u 217 #define P10_3_PORT GPIO_PRT10 218 #define P10_3_PIN 3u 219 #define P10_3_NUM 3u 220 #define P10_4_PORT GPIO_PRT10 221 #define P10_4_PIN 4u 222 #define P10_4_NUM 4u 223 #define P10_5_PORT GPIO_PRT10 224 #define P10_5_PIN 5u 225 #define P10_5_NUM 5u 226 227 /* PORT 11 (GPIO) */ 228 #define P11_0_PORT GPIO_PRT11 229 #define P11_0_PIN 0u 230 #define P11_0_NUM 0u 231 #define P11_1_PORT GPIO_PRT11 232 #define P11_1_PIN 1u 233 #define P11_1_NUM 1u 234 #define P11_2_PORT GPIO_PRT11 235 #define P11_2_PIN 2u 236 #define P11_2_NUM 2u 237 #define P11_3_PORT GPIO_PRT11 238 #define P11_3_PIN 3u 239 #define P11_3_NUM 3u 240 #define P11_4_PORT GPIO_PRT11 241 #define P11_4_PIN 4u 242 #define P11_4_NUM 4u 243 #define P11_5_PORT GPIO_PRT11 244 #define P11_5_PIN 5u 245 #define P11_5_NUM 5u 246 #define P11_6_PORT GPIO_PRT11 247 #define P11_6_PIN 6u 248 #define P11_6_NUM 6u 249 #define P11_7_PORT GPIO_PRT11 250 #define P11_7_PIN 7u 251 #define P11_7_NUM 7u 252 253 /* PORT 12 (GPIO) */ 254 #define P12_6_PORT GPIO_PRT12 255 #define P12_6_PIN 6u 256 #define P12_6_NUM 6u 257 #define P12_7_PORT GPIO_PRT12 258 #define P12_7_PIN 7u 259 #define P12_7_NUM 7u 260 261 /* PORT 14 (AUX) */ 262 #define USBDP_PORT GPIO_PRT14 263 #define USBDP_PIN 0u 264 #define USBDP_NUM 0u 265 #define P14_0_PORT GPIO_PRT14 266 #define P14_0_PIN 0u 267 #define P14_0_NUM 0u 268 #define USBDM_PORT GPIO_PRT14 269 #define USBDM_PIN 1u 270 #define USBDM_NUM 1u 271 #define P14_1_PORT GPIO_PRT14 272 #define P14_1_PIN 1u 273 #define P14_1_NUM 1u 274 275 /* Analog Connections */ 276 #define CSD_CMODPADD_PORT 7u 277 #define CSD_CMODPADD_PIN 1u 278 #define CSD_CMODPADS_PORT 7u 279 #define CSD_CMODPADS_PIN 1u 280 #define CSD_CSH_TANKPADD_PORT 7u 281 #define CSD_CSH_TANKPADD_PIN 2u 282 #define CSD_CSH_TANKPADS_PORT 7u 283 #define CSD_CSH_TANKPADS_PIN 2u 284 #define CSD_CSHIELDPADS_PORT 7u 285 #define CSD_CSHIELDPADS_PIN 7u 286 #define CSD_VREF_EXT_PORT 7u 287 #define CSD_VREF_EXT_PIN 3u 288 #define IOSS_ADFT0_NET_PORT 10u 289 #define IOSS_ADFT0_NET_PIN 0u 290 #define IOSS_ADFT1_NET_PORT 10u 291 #define IOSS_ADFT1_NET_PIN 1u 292 #define LPCOMP_INN_COMP0_PORT 5u 293 #define LPCOMP_INN_COMP0_PIN 7u 294 #define LPCOMP_INN_COMP1_PORT 6u 295 #define LPCOMP_INN_COMP1_PIN 3u 296 #define LPCOMP_INP_COMP0_PORT 5u 297 #define LPCOMP_INP_COMP0_PIN 6u 298 #define LPCOMP_INP_COMP1_PORT 6u 299 #define LPCOMP_INP_COMP1_PIN 2u 300 #define PASS_AREF_EXT_VREF_PORT 9u 301 #define PASS_AREF_EXT_VREF_PIN 3u 302 #define PASS_SARMUX_PADS0_PORT 10u 303 #define PASS_SARMUX_PADS0_PIN 0u 304 #define PASS_SARMUX_PADS1_PORT 10u 305 #define PASS_SARMUX_PADS1_PIN 1u 306 #define PASS_SARMUX_PADS2_PORT 10u 307 #define PASS_SARMUX_PADS2_PIN 2u 308 #define PASS_SARMUX_PADS3_PORT 10u 309 #define PASS_SARMUX_PADS3_PIN 3u 310 #define PASS_SARMUX_PADS4_PORT 10u 311 #define PASS_SARMUX_PADS4_PIN 4u 312 #define PASS_SARMUX_PADS5_PORT 10u 313 #define PASS_SARMUX_PADS5_PIN 5u 314 #define SRSS_ADFT_PIN0_PORT 10u 315 #define SRSS_ADFT_PIN0_PIN 0u 316 #define SRSS_ADFT_PIN1_PORT 10u 317 #define SRSS_ADFT_PIN1_PIN 1u 318 #define SRSS_ECO_IN_PORT 12u 319 #define SRSS_ECO_IN_PIN 6u 320 #define SRSS_ECO_OUT_PORT 12u 321 #define SRSS_ECO_OUT_PIN 7u 322 #define SRSS_WCO_IN_PORT 0u 323 #define SRSS_WCO_IN_PIN 0u 324 #define SRSS_WCO_OUT_PORT 0u 325 #define SRSS_WCO_OUT_PIN 1u 326 327 /* HSIOM Connections */ 328 typedef enum 329 { 330 /* Generic HSIOM connections */ 331 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 332 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 333 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 334 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 335 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 336 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 337 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 338 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 339 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 340 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 341 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 342 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 343 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 344 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 345 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 346 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 347 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 348 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 349 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 350 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 351 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 352 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 353 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 354 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 355 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 356 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 357 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 358 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 359 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 360 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 361 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 362 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 363 364 /* P0.0 */ 365 P0_0_GPIO = 0, /* GPIO controls 'out' */ 366 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 367 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 368 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 369 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 370 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 371 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 372 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 373 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 374 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 375 376 /* P0.1 */ 377 P0_1_GPIO = 0, /* GPIO controls 'out' */ 378 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 379 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 380 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 381 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 382 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 383 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 384 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 385 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 386 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 387 388 /* P0.2 */ 389 P0_2_GPIO = 0, /* GPIO controls 'out' */ 390 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 391 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 392 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 393 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 394 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 395 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 396 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 397 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 398 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 399 400 /* P0.3 */ 401 P0_3_GPIO = 0, /* GPIO controls 'out' */ 402 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 403 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 404 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 405 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 406 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 407 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 408 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 409 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 410 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 411 412 /* P0.4 */ 413 P0_4_GPIO = 0, /* GPIO controls 'out' */ 414 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 415 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 416 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 417 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 418 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 419 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 420 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 421 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 422 P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 423 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 424 425 /* P0.5 */ 426 P0_5_GPIO = 0, /* GPIO controls 'out' */ 427 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 428 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 429 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 430 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 431 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 432 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 433 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 434 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 435 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 436 P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 437 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 438 439 /* P2.0 */ 440 P2_0_GPIO = 0, /* GPIO controls 'out' */ 441 P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 442 P2_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 443 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 444 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 445 P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 446 P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 447 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 448 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 449 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 450 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 451 P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ 452 453 /* P2.1 */ 454 P2_1_GPIO = 0, /* GPIO controls 'out' */ 455 P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 456 P2_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 457 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 458 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 459 P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 460 P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 461 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 462 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 463 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 464 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 465 P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ 466 467 /* P2.2 */ 468 P2_2_GPIO = 0, /* GPIO controls 'out' */ 469 P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 470 P2_2_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 471 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 472 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 473 P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 474 P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 475 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 476 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 477 P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ 478 479 /* P2.3 */ 480 P2_3_GPIO = 0, /* GPIO controls 'out' */ 481 P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 482 P2_3_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 483 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 484 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 485 P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 486 P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 487 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 488 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 489 P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ 490 491 /* P2.4 */ 492 P2_4_GPIO = 0, /* GPIO controls 'out' */ 493 P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 494 P2_4_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 495 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 496 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 497 P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 498 P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 499 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 500 P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ 501 502 /* P2.5 */ 503 P2_5_GPIO = 0, /* GPIO controls 'out' */ 504 P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 505 P2_5_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 506 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 507 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 508 P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 509 P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 510 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 511 P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ 512 513 /* P2.6 */ 514 P2_6_GPIO = 0, /* GPIO controls 'out' */ 515 P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 516 P2_6_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 517 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 518 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 519 P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 520 P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 521 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 522 P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 523 P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ 524 525 /* P2.7 */ 526 P2_7_GPIO = 0, /* GPIO controls 'out' */ 527 P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 528 P2_7_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 529 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 530 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 531 P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 532 P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 533 P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 534 P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ 535 536 /* P3.0 */ 537 P3_0_GPIO = 0, /* GPIO controls 'out' */ 538 P3_0_AMUXA = 4, /* Analog mux bus A */ 539 P3_0_AMUXB = 5, /* Analog mux bus B */ 540 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 541 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 542 P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 543 P3_0_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 544 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 545 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 546 P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 547 P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 548 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 549 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 550 P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ 551 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 552 P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ 553 554 /* P3.1 */ 555 P3_1_GPIO = 0, /* GPIO controls 'out' */ 556 P3_1_AMUXA = 4, /* Analog mux bus A */ 557 P3_1_AMUXB = 5, /* Analog mux bus B */ 558 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 559 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 560 P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 561 P3_1_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 562 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 563 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 564 P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 565 P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 566 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 567 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 568 P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ 569 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 570 P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ 571 572 /* P5.0 */ 573 P5_0_GPIO = 0, /* GPIO controls 'out' */ 574 P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 575 P5_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 576 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 577 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 578 P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 579 P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 580 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 581 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 582 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 583 P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ 584 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 585 586 /* P5.1 */ 587 P5_1_GPIO = 0, /* GPIO controls 'out' */ 588 P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 589 P5_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 590 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 591 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 592 P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 593 P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 594 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 595 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 596 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 597 P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ 598 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 599 600 /* P5.6 */ 601 P5_6_GPIO = 0, /* GPIO controls 'out' */ 602 P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 603 P5_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 604 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 605 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 606 P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 607 P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 608 609 /* P5.7 */ 610 P5_7_GPIO = 0, /* GPIO controls 'out' */ 611 P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 612 P5_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 613 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 614 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 615 P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 616 P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 617 618 /* P6.2 */ 619 P6_2_GPIO = 0, /* GPIO controls 'out' */ 620 P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 621 P6_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 622 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 623 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 624 P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 625 P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 626 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 627 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 628 629 /* P6.3 */ 630 P6_3_GPIO = 0, /* GPIO controls 'out' */ 631 P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 632 P6_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 633 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 634 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 635 P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 636 P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 637 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 638 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 639 640 /* P6.4 */ 641 P6_4_GPIO = 0, /* GPIO controls 'out' */ 642 P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 643 P6_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 644 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 645 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 646 P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 647 P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 648 P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ 649 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 650 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 651 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 652 P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ 653 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 654 655 /* P6.5 */ 656 P6_5_GPIO = 0, /* GPIO controls 'out' */ 657 P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 658 P6_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 659 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 660 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 661 P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 662 P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 663 P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ 664 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 665 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 666 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 667 P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ 668 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 669 670 /* P6.6 */ 671 P6_6_GPIO = 0, /* GPIO controls 'out' */ 672 P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 673 P6_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 674 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 675 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 676 P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 677 P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 678 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 679 P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ 680 681 /* P6.7 */ 682 P6_7_GPIO = 0, /* GPIO controls 'out' */ 683 P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 684 P6_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 685 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 686 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 687 P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 688 P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 689 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 690 P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ 691 692 /* P7.0 */ 693 P7_0_GPIO = 0, /* GPIO controls 'out' */ 694 P7_0_AMUXA = 4, /* Analog mux bus A */ 695 P7_0_AMUXB = 5, /* Analog mux bus B */ 696 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 697 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 698 P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 699 P7_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 700 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ 701 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ 702 P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ 703 P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ 704 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 705 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 706 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 707 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 708 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 709 710 /* P7.1 */ 711 P7_1_GPIO = 0, /* GPIO controls 'out' */ 712 P7_1_AMUXA = 4, /* Analog mux bus A */ 713 P7_1_AMUXB = 5, /* Analog mux bus B */ 714 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 715 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 716 P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 717 P7_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 718 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ 719 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ 720 P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ 721 P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ 722 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 723 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 724 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 725 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 726 727 /* P7.2 */ 728 P7_2_GPIO = 0, /* GPIO controls 'out' */ 729 P7_2_AMUXA = 4, /* Analog mux bus A */ 730 P7_2_AMUXB = 5, /* Analog mux bus B */ 731 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 732 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 733 P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 734 P7_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 735 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 736 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 737 P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 738 P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 739 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 740 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 741 742 /* P7.3 */ 743 P7_3_GPIO = 0, /* GPIO controls 'out' */ 744 P7_3_AMUXA = 4, /* Analog mux bus A */ 745 P7_3_AMUXB = 5, /* Analog mux bus B */ 746 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 747 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 748 P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 749 P7_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 750 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 751 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 752 P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 753 P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 754 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 755 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 756 757 /* P7.7 */ 758 P7_7_GPIO = 0, /* GPIO controls 'out' */ 759 P7_7_AMUXA = 4, /* Analog mux bus A */ 760 P7_7_AMUXB = 5, /* Analog mux bus B */ 761 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 762 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 763 P7_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 764 P7_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 765 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 766 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 767 P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 768 P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 769 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 770 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 771 772 /* P8.0 */ 773 P8_0_GPIO = 0, /* GPIO controls 'out' */ 774 P8_0_AMUXA = 4, /* Analog mux bus A */ 775 P8_0_AMUXB = 5, /* Analog mux bus B */ 776 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 777 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 778 P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 779 P8_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 780 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 781 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 782 P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 783 P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 784 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 785 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 786 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 787 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 788 789 /* P8.1 */ 790 P8_1_GPIO = 0, /* GPIO controls 'out' */ 791 P8_1_AMUXA = 4, /* Analog mux bus A */ 792 P8_1_AMUXB = 5, /* Analog mux bus B */ 793 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 794 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 795 P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 796 P8_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ 797 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 798 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 799 P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 800 P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 801 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 802 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 803 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 804 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 805 806 /* P9.0 */ 807 P9_0_GPIO = 0, /* GPIO controls 'out' */ 808 P9_0_AMUXA = 4, /* Analog mux bus A */ 809 P9_0_AMUXB = 5, /* Analog mux bus B */ 810 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 811 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 812 P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 813 P9_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:2 */ 814 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 815 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 816 P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 817 P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 818 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 819 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 820 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 821 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 822 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 823 824 /* P9.1 */ 825 P9_1_GPIO = 0, /* GPIO controls 'out' */ 826 P9_1_AMUXA = 4, /* Analog mux bus A */ 827 P9_1_AMUXB = 5, /* Analog mux bus B */ 828 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 829 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 830 P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 831 P9_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:2 */ 832 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 833 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 834 P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 835 P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 836 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 837 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 838 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 839 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 840 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 841 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 842 843 /* P9.2 */ 844 P9_2_GPIO = 0, /* GPIO controls 'out' */ 845 P9_2_AMUXA = 4, /* Analog mux bus A */ 846 P9_2_AMUXB = 5, /* Analog mux bus B */ 847 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 848 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 849 P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 850 P9_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:2 */ 851 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 852 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 853 P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 854 P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 855 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 856 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 857 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 858 859 /* P9.3 */ 860 P9_3_GPIO = 0, /* GPIO controls 'out' */ 861 P9_3_AMUXA = 4, /* Analog mux bus A */ 862 P9_3_AMUXB = 5, /* Analog mux bus B */ 863 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 864 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 865 P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 866 P9_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:2 */ 867 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 868 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 869 P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 870 P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 871 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 872 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 873 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 874 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 875 876 /* P10.0 */ 877 P10_0_GPIO = 0, /* GPIO controls 'out' */ 878 P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ 879 P10_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:2 */ 880 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 881 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 882 P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 883 P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 884 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 885 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 886 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 887 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 888 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 889 890 /* P10.1 */ 891 P10_1_GPIO = 0, /* GPIO controls 'out' */ 892 P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ 893 P10_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:2 */ 894 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 895 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 896 P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 897 P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 898 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 899 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 900 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 901 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 902 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 903 904 /* P10.2 */ 905 P10_2_GPIO = 0, /* GPIO controls 'out' */ 906 P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 907 P10_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:2 */ 908 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 909 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 910 P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 911 P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 912 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 913 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 914 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 915 916 /* P10.3 */ 917 P10_3_GPIO = 0, /* GPIO controls 'out' */ 918 P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 919 P10_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:2 */ 920 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 921 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 922 P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 923 P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 924 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 925 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 926 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 927 928 /* P10.4 */ 929 P10_4_GPIO = 0, /* GPIO controls 'out' */ 930 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 931 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:3 */ 932 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 933 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 934 P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 935 P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 936 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 937 938 /* P10.5 */ 939 P10_5_GPIO = 0, /* GPIO controls 'out' */ 940 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 941 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:3 */ 942 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 943 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 944 P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 945 P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 946 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 947 948 /* P11.0 */ 949 P11_0_GPIO = 0, /* GPIO controls 'out' */ 950 P11_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:6 */ 951 P11_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:3 */ 952 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 953 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 954 P11_0_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 955 P11_0_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 956 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 957 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 958 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 959 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 960 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 961 962 /* P11.1 */ 963 P11_1_GPIO = 0, /* GPIO controls 'out' */ 964 P11_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:6 */ 965 P11_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:3 */ 966 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 967 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 968 P11_1_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 969 P11_1_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 970 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 971 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 972 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 973 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 974 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 975 976 /* P11.2 */ 977 P11_2_GPIO = 0, /* GPIO controls 'out' */ 978 P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ 979 P11_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:3 */ 980 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 981 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 982 P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 983 P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 984 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 985 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 986 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 987 988 /* P11.3 */ 989 P11_3_GPIO = 0, /* GPIO controls 'out' */ 990 P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ 991 P11_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:3 */ 992 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 993 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 994 P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 995 P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 996 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 997 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 998 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 999 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1000 1001 /* P11.4 */ 1002 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1003 P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:7 */ 1004 P11_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:3 */ 1005 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1006 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1007 P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1008 P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1009 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1010 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 1011 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1012 1013 /* P11.5 */ 1014 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1015 P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:7 */ 1016 P11_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:3 */ 1017 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1018 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1019 P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1020 P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1021 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1022 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 1023 1024 /* P11.6 */ 1025 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1026 P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:7 */ 1027 P11_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:3 */ 1028 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1029 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1030 P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1031 P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1032 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1033 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 1034 1035 /* P11.7 */ 1036 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1037 P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:7 */ 1038 P11_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:3 */ 1039 P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1040 P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1041 P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1042 P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1043 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1044 1045 /* P12.6 */ 1046 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1047 P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:7 */ 1048 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:3 */ 1049 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1050 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1051 P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1052 P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1053 1054 /* P12.7 */ 1055 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1056 P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:7 */ 1057 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:3 */ 1058 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1059 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1060 P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1061 P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1062 1063 /* USBDP */ 1064 USBDP_GPIO = 0, /* GPIO controls 'out' */ 1065 1066 /* USBDM */ 1067 USBDM_GPIO = 0 /* GPIO controls 'out' */ 1068 } en_hsiom_sel_t; 1069 1070 #endif /* _GPIO_PSOC6_03_68_QFN_H_ */ 1071 1072 1073 /* [] END OF FILE */ 1074
