1 /***************************************************************************//** 2 * \file gpio_psoc6_01_124_bga.h 3 * 4 * \brief 5 * PSoC6_01 device GPIO header for 124-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_01_124_BGA_H_ 28 #define _GPIO_PSOC6_01_124_BGA_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA 44 #define CY_GPIO_PIN_COUNT 124u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ADFT0_VDDD, 50 AMUXBUS_ADFT1_VDDD, 51 AMUXBUS_ANALOG_VDDA, 52 AMUXBUS_ANALOG_VDDD, 53 AMUXBUS_CSD0, 54 AMUXBUS_CSD1, 55 AMUXBUS_MAIN, 56 AMUXBUS_NOISY, 57 AMUXBUS_SAR, 58 AMUXBUS_VDDIO_1, 59 }; 60 61 /* AMUX Splitter Controls */ 62 typedef enum 63 { 64 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 65 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 66 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ 67 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 69 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 70 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 71 AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ 72 AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 73 } cy_en_amux_split_t; 74 75 /* Port List */ 76 /* PORT 0 (GPIO) */ 77 #define P0_0_PORT GPIO_PRT0 78 #define P0_0_PIN 0u 79 #define P0_0_NUM 0u 80 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 81 #define P0_1_PORT GPIO_PRT0 82 #define P0_1_PIN 1u 83 #define P0_1_NUM 1u 84 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 85 #define P0_2_PORT GPIO_PRT0 86 #define P0_2_PIN 2u 87 #define P0_2_NUM 2u 88 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 89 #define P0_3_PORT GPIO_PRT0 90 #define P0_3_PIN 3u 91 #define P0_3_NUM 3u 92 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 93 #define P0_4_PORT GPIO_PRT0 94 #define P0_4_PIN 4u 95 #define P0_4_NUM 4u 96 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 97 #define P0_5_PORT GPIO_PRT0 98 #define P0_5_PIN 5u 99 #define P0_5_NUM 5u 100 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 101 102 /* PORT 1 (GPIO_OVT) */ 103 #define P1_0_PORT GPIO_PRT1 104 #define P1_0_PIN 0u 105 #define P1_0_NUM 0u 106 #define P1_0_AMUXSEGMENT AMUXBUS_NOISY 107 #define P1_1_PORT GPIO_PRT1 108 #define P1_1_PIN 1u 109 #define P1_1_NUM 1u 110 #define P1_1_AMUXSEGMENT AMUXBUS_NOISY 111 #define P1_2_PORT GPIO_PRT1 112 #define P1_2_PIN 2u 113 #define P1_2_NUM 2u 114 #define P1_2_AMUXSEGMENT AMUXBUS_NOISY 115 #define P1_3_PORT GPIO_PRT1 116 #define P1_3_PIN 3u 117 #define P1_3_NUM 3u 118 #define P1_3_AMUXSEGMENT AMUXBUS_NOISY 119 #define P1_4_PORT GPIO_PRT1 120 #define P1_4_PIN 4u 121 #define P1_4_NUM 4u 122 #define P1_4_AMUXSEGMENT AMUXBUS_NOISY 123 #define P1_5_PORT GPIO_PRT1 124 #define P1_5_PIN 5u 125 #define P1_5_NUM 5u 126 #define P1_5_AMUXSEGMENT AMUXBUS_NOISY 127 128 /* PORT 2 (GPIO) */ 129 #define P2_0_PORT GPIO_PRT2 130 #define P2_0_PIN 0u 131 #define P2_0_NUM 0u 132 #define P2_0_AMUXSEGMENT AMUXBUS_NOISY 133 #define P2_1_PORT GPIO_PRT2 134 #define P2_1_PIN 1u 135 #define P2_1_NUM 1u 136 #define P2_1_AMUXSEGMENT AMUXBUS_NOISY 137 #define P2_2_PORT GPIO_PRT2 138 #define P2_2_PIN 2u 139 #define P2_2_NUM 2u 140 #define P2_2_AMUXSEGMENT AMUXBUS_NOISY 141 #define P2_3_PORT GPIO_PRT2 142 #define P2_3_PIN 3u 143 #define P2_3_NUM 3u 144 #define P2_3_AMUXSEGMENT AMUXBUS_NOISY 145 #define P2_4_PORT GPIO_PRT2 146 #define P2_4_PIN 4u 147 #define P2_4_NUM 4u 148 #define P2_4_AMUXSEGMENT AMUXBUS_NOISY 149 #define P2_5_PORT GPIO_PRT2 150 #define P2_5_PIN 5u 151 #define P2_5_NUM 5u 152 #define P2_5_AMUXSEGMENT AMUXBUS_NOISY 153 #define P2_6_PORT GPIO_PRT2 154 #define P2_6_PIN 6u 155 #define P2_6_NUM 6u 156 #define P2_6_AMUXSEGMENT AMUXBUS_NOISY 157 #define P2_7_PORT GPIO_PRT2 158 #define P2_7_PIN 7u 159 #define P2_7_NUM 7u 160 #define P2_7_AMUXSEGMENT AMUXBUS_NOISY 161 162 /* PORT 3 (GPIO) */ 163 #define P3_0_PORT GPIO_PRT3 164 #define P3_0_PIN 0u 165 #define P3_0_NUM 0u 166 #define P3_0_AMUXSEGMENT AMUXBUS_NOISY 167 #define P3_1_PORT GPIO_PRT3 168 #define P3_1_PIN 1u 169 #define P3_1_NUM 1u 170 #define P3_1_AMUXSEGMENT AMUXBUS_NOISY 171 #define P3_2_PORT GPIO_PRT3 172 #define P3_2_PIN 2u 173 #define P3_2_NUM 2u 174 #define P3_2_AMUXSEGMENT AMUXBUS_NOISY 175 #define P3_3_PORT GPIO_PRT3 176 #define P3_3_PIN 3u 177 #define P3_3_NUM 3u 178 #define P3_3_AMUXSEGMENT AMUXBUS_NOISY 179 #define P3_4_PORT GPIO_PRT3 180 #define P3_4_PIN 4u 181 #define P3_4_NUM 4u 182 #define P3_4_AMUXSEGMENT AMUXBUS_NOISY 183 #define P3_5_PORT GPIO_PRT3 184 #define P3_5_PIN 5u 185 #define P3_5_NUM 5u 186 #define P3_5_AMUXSEGMENT AMUXBUS_NOISY 187 188 /* PORT 4 (GPIO) */ 189 #define P4_0_PORT GPIO_PRT4 190 #define P4_0_PIN 0u 191 #define P4_0_NUM 0u 192 #define P4_0_AMUXSEGMENT AMUXBUS_NOISY 193 #define P4_1_PORT GPIO_PRT4 194 #define P4_1_PIN 1u 195 #define P4_1_NUM 1u 196 #define P4_1_AMUXSEGMENT AMUXBUS_NOISY 197 198 /* PORT 5 (GPIO) */ 199 #define P5_0_PORT GPIO_PRT5 200 #define P5_0_PIN 0u 201 #define P5_0_NUM 0u 202 #define P5_0_AMUXSEGMENT AMUXBUS_CSD0 203 #define P5_1_PORT GPIO_PRT5 204 #define P5_1_PIN 1u 205 #define P5_1_NUM 1u 206 #define P5_1_AMUXSEGMENT AMUXBUS_CSD0 207 #define P5_2_PORT GPIO_PRT5 208 #define P5_2_PIN 2u 209 #define P5_2_NUM 2u 210 #define P5_2_AMUXSEGMENT AMUXBUS_CSD0 211 #define P5_3_PORT GPIO_PRT5 212 #define P5_3_PIN 3u 213 #define P5_3_NUM 3u 214 #define P5_3_AMUXSEGMENT AMUXBUS_CSD0 215 #define P5_4_PORT GPIO_PRT5 216 #define P5_4_PIN 4u 217 #define P5_4_NUM 4u 218 #define P5_4_AMUXSEGMENT AMUXBUS_CSD0 219 #define P5_5_PORT GPIO_PRT5 220 #define P5_5_PIN 5u 221 #define P5_5_NUM 5u 222 #define P5_5_AMUXSEGMENT AMUXBUS_CSD0 223 #define P5_6_PORT GPIO_PRT5 224 #define P5_6_PIN 6u 225 #define P5_6_NUM 6u 226 #define P5_6_AMUXSEGMENT AMUXBUS_CSD0 227 #define P5_7_PORT GPIO_PRT5 228 #define P5_7_PIN 7u 229 #define P5_7_NUM 7u 230 #define P5_7_AMUXSEGMENT AMUXBUS_CSD0 231 232 /* PORT 6 (GPIO) */ 233 #define P6_0_PORT GPIO_PRT6 234 #define P6_0_PIN 0u 235 #define P6_0_NUM 0u 236 #define P6_0_AMUXSEGMENT AMUXBUS_CSD0 237 #define P6_1_PORT GPIO_PRT6 238 #define P6_1_PIN 1u 239 #define P6_1_NUM 1u 240 #define P6_1_AMUXSEGMENT AMUXBUS_CSD0 241 #define P6_2_PORT GPIO_PRT6 242 #define P6_2_PIN 2u 243 #define P6_2_NUM 2u 244 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 245 #define P6_3_PORT GPIO_PRT6 246 #define P6_3_PIN 3u 247 #define P6_3_NUM 3u 248 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 249 #define P6_4_PORT GPIO_PRT6 250 #define P6_4_PIN 4u 251 #define P6_4_NUM 4u 252 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 253 #define P6_5_PORT GPIO_PRT6 254 #define P6_5_PIN 5u 255 #define P6_5_NUM 5u 256 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 257 #define P6_6_PORT GPIO_PRT6 258 #define P6_6_PIN 6u 259 #define P6_6_NUM 6u 260 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 261 #define P6_7_PORT GPIO_PRT6 262 #define P6_7_PIN 7u 263 #define P6_7_NUM 7u 264 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 265 266 /* PORT 7 (GPIO) */ 267 #define P7_0_PORT GPIO_PRT7 268 #define P7_0_PIN 0u 269 #define P7_0_NUM 0u 270 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 271 #define P7_1_PORT GPIO_PRT7 272 #define P7_1_PIN 1u 273 #define P7_1_NUM 1u 274 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 275 #define P7_2_PORT GPIO_PRT7 276 #define P7_2_PIN 2u 277 #define P7_2_NUM 2u 278 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 279 #define P7_3_PORT GPIO_PRT7 280 #define P7_3_PIN 3u 281 #define P7_3_NUM 3u 282 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 283 #define P7_4_PORT GPIO_PRT7 284 #define P7_4_PIN 4u 285 #define P7_4_NUM 4u 286 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 287 #define P7_5_PORT GPIO_PRT7 288 #define P7_5_PIN 5u 289 #define P7_5_NUM 5u 290 #define P7_5_AMUXSEGMENT AMUXBUS_CSD0 291 #define P7_6_PORT GPIO_PRT7 292 #define P7_6_PIN 6u 293 #define P7_6_NUM 6u 294 #define P7_6_AMUXSEGMENT AMUXBUS_CSD0 295 #define P7_7_PORT GPIO_PRT7 296 #define P7_7_PIN 7u 297 #define P7_7_NUM 7u 298 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 299 300 /* PORT 8 (GPIO) */ 301 #define P8_0_PORT GPIO_PRT8 302 #define P8_0_PIN 0u 303 #define P8_0_NUM 0u 304 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 305 #define P8_1_PORT GPIO_PRT8 306 #define P8_1_PIN 1u 307 #define P8_1_NUM 1u 308 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 309 #define P8_2_PORT GPIO_PRT8 310 #define P8_2_PIN 2u 311 #define P8_2_NUM 2u 312 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 313 #define P8_3_PORT GPIO_PRT8 314 #define P8_3_PIN 3u 315 #define P8_3_NUM 3u 316 #define P8_3_AMUXSEGMENT AMUXBUS_CSD0 317 #define P8_4_PORT GPIO_PRT8 318 #define P8_4_PIN 4u 319 #define P8_4_NUM 4u 320 #define P8_4_AMUXSEGMENT AMUXBUS_CSD0 321 #define P8_5_PORT GPIO_PRT8 322 #define P8_5_PIN 5u 323 #define P8_5_NUM 5u 324 #define P8_5_AMUXSEGMENT AMUXBUS_CSD0 325 #define P8_6_PORT GPIO_PRT8 326 #define P8_6_PIN 6u 327 #define P8_6_NUM 6u 328 #define P8_6_AMUXSEGMENT AMUXBUS_CSD0 329 #define P8_7_PORT GPIO_PRT8 330 #define P8_7_PIN 7u 331 #define P8_7_NUM 7u 332 #define P8_7_AMUXSEGMENT AMUXBUS_CSD0 333 334 /* PORT 9 (GPIO) */ 335 #define P9_0_PORT GPIO_PRT9 336 #define P9_0_PIN 0u 337 #define P9_0_NUM 0u 338 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 339 #define P9_1_PORT GPIO_PRT9 340 #define P9_1_PIN 1u 341 #define P9_1_NUM 1u 342 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 343 #define P9_2_PORT GPIO_PRT9 344 #define P9_2_PIN 2u 345 #define P9_2_NUM 2u 346 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 347 #define P9_3_PORT GPIO_PRT9 348 #define P9_3_PIN 3u 349 #define P9_3_NUM 3u 350 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 351 #define P9_4_PORT GPIO_PRT9 352 #define P9_4_PIN 4u 353 #define P9_4_NUM 4u 354 #define P9_4_AMUXSEGMENT AMUXBUS_SAR 355 #define P9_5_PORT GPIO_PRT9 356 #define P9_5_PIN 5u 357 #define P9_5_NUM 5u 358 #define P9_5_AMUXSEGMENT AMUXBUS_SAR 359 #define P9_6_PORT GPIO_PRT9 360 #define P9_6_PIN 6u 361 #define P9_6_NUM 6u 362 #define P9_6_AMUXSEGMENT AMUXBUS_SAR 363 #define P9_7_PORT GPIO_PRT9 364 #define P9_7_PIN 7u 365 #define P9_7_NUM 7u 366 #define P9_7_AMUXSEGMENT AMUXBUS_SAR 367 368 /* PORT 10 (GPIO) */ 369 #define P10_0_PORT GPIO_PRT10 370 #define P10_0_PIN 0u 371 #define P10_0_NUM 0u 372 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 373 #define P10_1_PORT GPIO_PRT10 374 #define P10_1_PIN 1u 375 #define P10_1_NUM 1u 376 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 377 #define P10_2_PORT GPIO_PRT10 378 #define P10_2_PIN 2u 379 #define P10_2_NUM 2u 380 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 381 #define P10_3_PORT GPIO_PRT10 382 #define P10_3_PIN 3u 383 #define P10_3_NUM 3u 384 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 385 #define P10_4_PORT GPIO_PRT10 386 #define P10_4_PIN 4u 387 #define P10_4_NUM 4u 388 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 389 #define P10_5_PORT GPIO_PRT10 390 #define P10_5_PIN 5u 391 #define P10_5_NUM 5u 392 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 393 #define P10_6_PORT GPIO_PRT10 394 #define P10_6_PIN 6u 395 #define P10_6_NUM 6u 396 #define P10_6_AMUXSEGMENT AMUXBUS_SAR 397 #define P10_7_PORT GPIO_PRT10 398 #define P10_7_PIN 7u 399 #define P10_7_NUM 7u 400 #define P10_7_AMUXSEGMENT AMUXBUS_SAR 401 402 /* PORT 11 (GPIO) */ 403 #define P11_0_PORT GPIO_PRT11 404 #define P11_0_PIN 0u 405 #define P11_0_NUM 0u 406 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 407 #define P11_1_PORT GPIO_PRT11 408 #define P11_1_PIN 1u 409 #define P11_1_NUM 1u 410 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 411 #define P11_2_PORT GPIO_PRT11 412 #define P11_2_PIN 2u 413 #define P11_2_NUM 2u 414 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 415 #define P11_3_PORT GPIO_PRT11 416 #define P11_3_PIN 3u 417 #define P11_3_NUM 3u 418 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 419 #define P11_4_PORT GPIO_PRT11 420 #define P11_4_PIN 4u 421 #define P11_4_NUM 4u 422 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 423 #define P11_5_PORT GPIO_PRT11 424 #define P11_5_PIN 5u 425 #define P11_5_NUM 5u 426 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 427 #define P11_6_PORT GPIO_PRT11 428 #define P11_6_PIN 6u 429 #define P11_6_NUM 6u 430 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 431 #define P11_7_PORT GPIO_PRT11 432 #define P11_7_PIN 7u 433 #define P11_7_NUM 7u 434 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 435 436 /* PORT 12 (GPIO) */ 437 #define P12_0_PORT GPIO_PRT12 438 #define P12_0_PIN 0u 439 #define P12_0_NUM 0u 440 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 441 #define P12_1_PORT GPIO_PRT12 442 #define P12_1_PIN 1u 443 #define P12_1_NUM 1u 444 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 445 #define P12_2_PORT GPIO_PRT12 446 #define P12_2_PIN 2u 447 #define P12_2_NUM 2u 448 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 449 #define P12_3_PORT GPIO_PRT12 450 #define P12_3_PIN 3u 451 #define P12_3_NUM 3u 452 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 453 #define P12_4_PORT GPIO_PRT12 454 #define P12_4_PIN 4u 455 #define P12_4_NUM 4u 456 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 457 #define P12_5_PORT GPIO_PRT12 458 #define P12_5_PIN 5u 459 #define P12_5_NUM 5u 460 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 461 #define P12_6_PORT GPIO_PRT12 462 #define P12_6_PIN 6u 463 #define P12_6_NUM 6u 464 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 465 #define P12_7_PORT GPIO_PRT12 466 #define P12_7_PIN 7u 467 #define P12_7_NUM 7u 468 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 469 470 /* PORT 13 (GPIO) */ 471 #define P13_0_PORT GPIO_PRT13 472 #define P13_0_PIN 0u 473 #define P13_0_NUM 0u 474 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 475 #define P13_1_PORT GPIO_PRT13 476 #define P13_1_PIN 1u 477 #define P13_1_NUM 1u 478 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 479 #define P13_2_PORT GPIO_PRT13 480 #define P13_2_PIN 2u 481 #define P13_2_NUM 2u 482 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 483 #define P13_3_PORT GPIO_PRT13 484 #define P13_3_PIN 3u 485 #define P13_3_NUM 3u 486 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 487 #define P13_4_PORT GPIO_PRT13 488 #define P13_4_PIN 4u 489 #define P13_4_NUM 4u 490 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 491 #define P13_5_PORT GPIO_PRT13 492 #define P13_5_PIN 5u 493 #define P13_5_NUM 5u 494 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 495 #define P13_6_PORT GPIO_PRT13 496 #define P13_6_PIN 6u 497 #define P13_6_NUM 6u 498 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 499 #define P13_7_PORT GPIO_PRT13 500 #define P13_7_PIN 7u 501 #define P13_7_NUM 7u 502 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 503 504 /* PORT 14 (AUX) */ 505 #define USBDP_PORT GPIO_PRT14 506 #define USBDP_PIN 0u 507 #define USBDP_NUM 0u 508 #define USBDP_AMUXSEGMENT AMUXBUS_NOISY 509 #define P14_0_PORT GPIO_PRT14 510 #define P14_0_PIN 0u 511 #define P14_0_NUM 0u 512 #define P14_0_AMUXSEGMENT AMUXBUS_NOISY 513 #define USBDM_PORT GPIO_PRT14 514 #define USBDM_PIN 1u 515 #define USBDM_NUM 1u 516 #define USBDM_AMUXSEGMENT AMUXBUS_NOISY 517 #define P14_1_PORT GPIO_PRT14 518 #define P14_1_PIN 1u 519 #define P14_1_NUM 1u 520 #define P14_1_AMUXSEGMENT AMUXBUS_NOISY 521 522 /* Analog Connections */ 523 #define CSD_CMODPADD_PORT 7u 524 #define CSD_CMODPADD_PIN 1u 525 #define CSD_CMODPADS_PORT 7u 526 #define CSD_CMODPADS_PIN 1u 527 #define CSD_CSH_TANKPADD_PORT 7u 528 #define CSD_CSH_TANKPADD_PIN 2u 529 #define CSD_CSH_TANKPADS_PORT 7u 530 #define CSD_CSH_TANKPADS_PIN 2u 531 #define CSD_CSHIELDPADS_PORT 7u 532 #define CSD_CSHIELDPADS_PIN 7u 533 #define CSD_VREF_EXT_PORT 7u 534 #define CSD_VREF_EXT_PIN 3u 535 #define IOSS_ADFT0_NET_PORT 10u 536 #define IOSS_ADFT0_NET_PIN 0u 537 #define IOSS_ADFT1_NET_PORT 10u 538 #define IOSS_ADFT1_NET_PIN 1u 539 #define LPCOMP_INN_COMP0_PORT 5u 540 #define LPCOMP_INN_COMP0_PIN 7u 541 #define LPCOMP_INN_COMP1_PORT 6u 542 #define LPCOMP_INN_COMP1_PIN 3u 543 #define LPCOMP_INP_COMP0_PORT 5u 544 #define LPCOMP_INP_COMP0_PIN 6u 545 #define LPCOMP_INP_COMP1_PORT 6u 546 #define LPCOMP_INP_COMP1_PIN 2u 547 #define PASS_AREF_EXT_VREF_PORT 9u 548 #define PASS_AREF_EXT_VREF_PIN 7u 549 #define PASS_CTB_OA0_OUT_10X_PORT 9u 550 #define PASS_CTB_OA0_OUT_10X_PIN 2u 551 #define PASS_CTB_OA1_OUT_10X_PORT 9u 552 #define PASS_CTB_OA1_OUT_10X_PIN 3u 553 #define PASS_CTB_PADS0_PORT 9u 554 #define PASS_CTB_PADS0_PIN 0u 555 #define PASS_CTB_PADS1_PORT 9u 556 #define PASS_CTB_PADS1_PIN 1u 557 #define PASS_CTB_PADS2_PORT 9u 558 #define PASS_CTB_PADS2_PIN 2u 559 #define PASS_CTB_PADS3_PORT 9u 560 #define PASS_CTB_PADS3_PIN 3u 561 #define PASS_CTB_PADS4_PORT 9u 562 #define PASS_CTB_PADS4_PIN 4u 563 #define PASS_CTB_PADS5_PORT 9u 564 #define PASS_CTB_PADS5_PIN 5u 565 #define PASS_CTB_PADS6_PORT 9u 566 #define PASS_CTB_PADS6_PIN 6u 567 #define PASS_CTB_PADS7_PORT 9u 568 #define PASS_CTB_PADS7_PIN 7u 569 #define PASS_SARMUX_PADS0_PORT 10u 570 #define PASS_SARMUX_PADS0_PIN 0u 571 #define PASS_SARMUX_PADS1_PORT 10u 572 #define PASS_SARMUX_PADS1_PIN 1u 573 #define PASS_SARMUX_PADS2_PORT 10u 574 #define PASS_SARMUX_PADS2_PIN 2u 575 #define PASS_SARMUX_PADS3_PORT 10u 576 #define PASS_SARMUX_PADS3_PIN 3u 577 #define PASS_SARMUX_PADS4_PORT 10u 578 #define PASS_SARMUX_PADS4_PIN 4u 579 #define PASS_SARMUX_PADS5_PORT 10u 580 #define PASS_SARMUX_PADS5_PIN 5u 581 #define PASS_SARMUX_PADS6_PORT 10u 582 #define PASS_SARMUX_PADS6_PIN 6u 583 #define PASS_SARMUX_PADS7_PORT 10u 584 #define PASS_SARMUX_PADS7_PIN 7u 585 #define SRSS_ADFT_PIN0_PORT 10u 586 #define SRSS_ADFT_PIN0_PIN 0u 587 #define SRSS_ADFT_PIN1_PORT 10u 588 #define SRSS_ADFT_PIN1_PIN 1u 589 #define SRSS_ECO_IN_PORT 12u 590 #define SRSS_ECO_IN_PIN 6u 591 #define SRSS_ECO_OUT_PORT 12u 592 #define SRSS_ECO_OUT_PIN 7u 593 #define SRSS_WCO_IN_PORT 0u 594 #define SRSS_WCO_IN_PIN 0u 595 #define SRSS_WCO_OUT_PORT 0u 596 #define SRSS_WCO_OUT_PIN 1u 597 598 /* HSIOM Connections */ 599 typedef enum 600 { 601 /* Generic HSIOM connections */ 602 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 603 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 604 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 605 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 606 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 607 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 608 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 609 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 610 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 611 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 612 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 613 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 614 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 615 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 616 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 617 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 618 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 619 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 620 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 621 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 622 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 623 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 624 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 625 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 626 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 627 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 628 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 629 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 630 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 631 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 632 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 633 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 634 635 /* P0.0 */ 636 P0_0_GPIO = 0, /* GPIO controls 'out' */ 637 P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 638 P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 639 P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 640 P0_0_AMUXA = 4, /* Analog mux bus A */ 641 P0_0_AMUXB = 5, /* Analog mux bus B */ 642 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 643 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 644 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 645 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 646 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 647 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 648 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 649 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 650 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 651 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 652 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 653 654 /* P0.1 */ 655 P0_1_GPIO = 0, /* GPIO controls 'out' */ 656 P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 657 P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 658 P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 659 P0_1_AMUXA = 4, /* Analog mux bus A */ 660 P0_1_AMUXB = 5, /* Analog mux bus B */ 661 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 662 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 663 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 664 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 665 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 666 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 667 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 668 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 669 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 670 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 671 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 672 673 /* P0.2 */ 674 P0_2_GPIO = 0, /* GPIO controls 'out' */ 675 P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 676 P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 677 P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 678 P0_2_AMUXA = 4, /* Analog mux bus A */ 679 P0_2_AMUXB = 5, /* Analog mux bus B */ 680 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 681 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 682 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 683 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 684 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 685 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 686 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 687 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 688 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 689 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 690 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 691 692 /* P0.3 */ 693 P0_3_GPIO = 0, /* GPIO controls 'out' */ 694 P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 695 P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 696 P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 697 P0_3_AMUXA = 4, /* Analog mux bus A */ 698 P0_3_AMUXB = 5, /* Analog mux bus B */ 699 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 700 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 701 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 702 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 703 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 704 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 705 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 706 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 707 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 708 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 709 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 710 711 /* P0.4 */ 712 P0_4_GPIO = 0, /* GPIO controls 'out' */ 713 P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 714 P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 715 P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 716 P0_4_AMUXA = 4, /* Analog mux bus A */ 717 P0_4_AMUXB = 5, /* Analog mux bus B */ 718 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 719 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 720 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 721 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 722 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 723 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 724 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 725 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 726 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 727 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 728 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 729 730 /* P0.5 */ 731 P0_5_GPIO = 0, /* GPIO controls 'out' */ 732 P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 733 P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 734 P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 735 P0_5_AMUXA = 4, /* Analog mux bus A */ 736 P0_5_AMUXB = 5, /* Analog mux bus B */ 737 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 738 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 739 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 740 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 741 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 742 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 743 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 744 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 745 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 746 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 747 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 748 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 749 750 /* P1.0 */ 751 P1_0_GPIO = 0, /* GPIO controls 'out' */ 752 P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 753 P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 754 P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 755 P1_0_AMUXA = 4, /* Analog mux bus A */ 756 P1_0_AMUXB = 5, /* Analog mux bus B */ 757 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 758 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 759 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 760 P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 761 P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 762 P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 763 P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 764 P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 765 P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ 766 P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ 767 P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ 768 P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 769 770 /* P1.1 */ 771 P1_1_GPIO = 0, /* GPIO controls 'out' */ 772 P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 773 P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 774 P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 775 P1_1_AMUXA = 4, /* Analog mux bus A */ 776 P1_1_AMUXB = 5, /* Analog mux bus B */ 777 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 778 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 779 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 780 P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 781 P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 782 P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 783 P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 784 P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 785 P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ 786 P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ 787 P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ 788 P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 789 790 /* P1.2 */ 791 P1_2_GPIO = 0, /* GPIO controls 'out' */ 792 P1_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 793 P1_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 794 P1_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 795 P1_2_AMUXA = 4, /* Analog mux bus A */ 796 P1_2_AMUXB = 5, /* Analog mux bus B */ 797 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 798 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 799 P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */ 800 P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */ 801 P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 802 P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 803 P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 804 P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 805 P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ 806 P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ 807 808 /* P1.3 */ 809 P1_3_GPIO = 0, /* GPIO controls 'out' */ 810 P1_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 811 P1_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 812 P1_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 813 P1_3_AMUXA = 4, /* Analog mux bus A */ 814 P1_3_AMUXB = 5, /* Analog mux bus B */ 815 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 816 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 817 P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */ 818 P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ 819 P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 820 P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 821 P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 822 P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 823 P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */ 824 P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */ 825 826 /* P1.4 */ 827 P1_4_GPIO = 0, /* GPIO controls 'out' */ 828 P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 829 P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 830 P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 831 P1_4_AMUXA = 4, /* Analog mux bus A */ 832 P1_4_AMUXB = 5, /* Analog mux bus B */ 833 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 834 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 835 P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ 836 P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ 837 P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 838 P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 839 P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 840 P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 841 P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ 842 843 /* P1.5 */ 844 P1_5_GPIO = 0, /* GPIO controls 'out' */ 845 P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 846 P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 847 P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 848 P1_5_AMUXA = 4, /* Analog mux bus A */ 849 P1_5_AMUXB = 5, /* Analog mux bus B */ 850 P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 851 P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 852 P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ 853 P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 854 P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 855 P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 856 P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 857 P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 858 P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ 859 860 /* P2.0 */ 861 P2_0_GPIO = 0, /* GPIO controls 'out' */ 862 P2_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 863 P2_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 864 P2_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 865 P2_0_AMUXA = 4, /* Analog mux bus A */ 866 P2_0_AMUXB = 5, /* Analog mux bus B */ 867 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 868 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 869 P2_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:4 */ 870 P2_0_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:1 */ 871 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 872 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 873 P2_0_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 874 P2_0_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 875 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 876 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 877 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 878 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 879 P2_0_BLESS_MXD_DPSLP_RET_SWITCH_HV = 28, /* Digital Deep Sleep - bless.mxd_dpslp_ret_switch_hv */ 880 881 /* P2.1 */ 882 P2_1_GPIO = 0, /* GPIO controls 'out' */ 883 P2_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 884 P2_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 885 P2_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 886 P2_1_AMUXA = 4, /* Analog mux bus A */ 887 P2_1_AMUXB = 5, /* Analog mux bus B */ 888 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 889 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 890 P2_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:4 */ 891 P2_1_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:1 */ 892 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 893 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 894 P2_1_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 895 P2_1_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 896 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 897 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 898 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 899 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 900 P2_1_BLESS_MXD_DPSLP_RET_LDO_OL_HV = 28, /* Digital Deep Sleep - bless.mxd_dpslp_ret_ldo_ol_hv */ 901 902 /* P2.2 */ 903 P2_2_GPIO = 0, /* GPIO controls 'out' */ 904 P2_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 905 P2_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 906 P2_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 907 P2_2_AMUXA = 4, /* Analog mux bus A */ 908 P2_2_AMUXB = 5, /* Analog mux bus B */ 909 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 910 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 911 P2_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:4 */ 912 P2_2_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:1 */ 913 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 914 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 915 P2_2_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 916 P2_2_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 917 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 918 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 919 P2_2_BLESS_MXD_DPSLP_BUCK_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_buck_en */ 920 921 /* P2.3 */ 922 P2_3_GPIO = 0, /* GPIO controls 'out' */ 923 P2_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 924 P2_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 925 P2_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 926 P2_3_AMUXA = 4, /* Analog mux bus A */ 927 P2_3_AMUXB = 5, /* Analog mux bus B */ 928 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 929 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 930 P2_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:4 */ 931 P2_3_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:1 */ 932 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 933 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 934 P2_3_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 935 P2_3_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 936 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 937 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 938 P2_3_BLESS_MXD_DPSLP_RESET_N = 28, /* Digital Deep Sleep - bless.mxd_dpslp_reset_n */ 939 940 /* P2.4 */ 941 P2_4_GPIO = 0, /* GPIO controls 'out' */ 942 P2_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 943 P2_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 944 P2_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 945 P2_4_AMUXA = 4, /* Analog mux bus A */ 946 P2_4_AMUXB = 5, /* Analog mux bus B */ 947 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 948 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 949 P2_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 950 P2_4_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:1 */ 951 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 952 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 953 P2_4_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 954 P2_4_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 955 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 956 P2_4_BLESS_MXD_DPSLP_CLK_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_clk_en */ 957 958 /* P2.5 */ 959 P2_5_GPIO = 0, /* GPIO controls 'out' */ 960 P2_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 961 P2_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 962 P2_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 963 P2_5_AMUXA = 4, /* Analog mux bus A */ 964 P2_5_AMUXB = 5, /* Analog mux bus B */ 965 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 966 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 967 P2_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 968 P2_5_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ 969 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 970 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 971 P2_5_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 972 P2_5_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 973 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 974 P2_5_BLESS_MXD_DPSLP_ISOLATE_N = 28, /* Digital Deep Sleep - bless.mxd_dpslp_isolate_n */ 975 976 /* P2.6 */ 977 P2_6_GPIO = 0, /* GPIO controls 'out' */ 978 P2_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 979 P2_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 980 P2_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 981 P2_6_AMUXA = 4, /* Analog mux bus A */ 982 P2_6_AMUXB = 5, /* Analog mux bus B */ 983 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 984 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 985 P2_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 986 P2_6_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:1 */ 987 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 988 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 989 P2_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 990 P2_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 991 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 992 P2_6_BLESS_MXD_DPSLP_ACT_LDO_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_act_ldo_en */ 993 994 /* P2.7 */ 995 P2_7_GPIO = 0, /* GPIO controls 'out' */ 996 P2_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 997 P2_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 998 P2_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 999 P2_7_AMUXA = 4, /* Analog mux bus A */ 1000 P2_7_AMUXB = 5, /* Analog mux bus B */ 1001 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1002 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1003 P2_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 1004 P2_7_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ 1005 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 1006 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 1007 P2_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 1008 P2_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 1009 P2_7_BLESS_MXD_DPSLP_XTAL_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_xtal_en */ 1010 1011 /* P3.0 */ 1012 P3_0_GPIO = 0, /* GPIO controls 'out' */ 1013 P3_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1014 P3_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1015 P3_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1016 P3_0_AMUXA = 4, /* Analog mux bus A */ 1017 P3_0_AMUXB = 5, /* Analog mux bus B */ 1018 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1019 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1020 P3_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ 1021 P3_0_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:1 */ 1022 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ 1023 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ 1024 P3_0_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:0 */ 1025 P3_0_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:0 */ 1026 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 1027 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 1028 P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ 1029 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 1030 P3_0_BLESS_MXD_DPSLP_DIG_LDO_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_dig_ldo_en */ 1031 1032 /* P3.1 */ 1033 P3_1_GPIO = 0, /* GPIO controls 'out' */ 1034 P3_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1035 P3_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1036 P3_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1037 P3_1_AMUXA = 4, /* Analog mux bus A */ 1038 P3_1_AMUXB = 5, /* Analog mux bus B */ 1039 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1040 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1041 P3_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ 1042 P3_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:1 */ 1043 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ 1044 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ 1045 P3_1_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:0 */ 1046 P3_1_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:0 */ 1047 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 1048 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 1049 P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ 1050 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 1051 P3_1_BLESS_MXD_ACT_DBUS_RX_EN = 26, /* Digital Active - bless.mxd_act_dbus_rx_en */ 1052 1053 /* P3.2 */ 1054 P3_2_GPIO = 0, /* GPIO controls 'out' */ 1055 P3_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1056 P3_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1057 P3_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1058 P3_2_AMUXA = 4, /* Analog mux bus A */ 1059 P3_2_AMUXB = 5, /* Analog mux bus B */ 1060 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1061 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1062 P3_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 1063 P3_2_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:1 */ 1064 P3_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 1065 P3_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 1066 P3_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 1067 P3_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 1068 P3_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:1 */ 1069 P3_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:1 */ 1070 P3_2_BLESS_MXD_ACT_DBUS_TX_EN = 26, /* Digital Active - bless.mxd_act_dbus_tx_en */ 1071 1072 /* P3.3 */ 1073 P3_3_GPIO = 0, /* GPIO controls 'out' */ 1074 P3_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1075 P3_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1076 P3_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1077 P3_3_AMUXA = 4, /* Analog mux bus A */ 1078 P3_3_AMUXB = 5, /* Analog mux bus B */ 1079 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1080 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1081 P3_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 1082 P3_3_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:1 */ 1083 P3_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 1084 P3_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 1085 P3_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 1086 P3_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 1087 P3_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:1 */ 1088 P3_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:1 */ 1089 P3_3_BLESS_MXD_ACT_BPKTCTL = 26, /* Digital Active - bless.mxd_act_bpktctl */ 1090 1091 /* P3.4 */ 1092 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1093 P3_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1094 P3_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1095 P3_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1096 P3_4_AMUXA = 4, /* Analog mux bus A */ 1097 P3_4_AMUXB = 5, /* Analog mux bus B */ 1098 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1099 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1100 P3_4_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:5 */ 1101 P3_4_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:1 */ 1102 P3_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 1103 P3_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 1104 P3_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 1105 P3_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 1106 P3_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:1 */ 1107 P3_4_BLESS_MXD_ACT_TXD_RXD = 26, /* Digital Active - bless.mxd_act_txd_rxd */ 1108 1109 /* P3.5 */ 1110 P3_5_GPIO = 0, /* GPIO controls 'out' */ 1111 P3_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1112 P3_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1113 P3_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1114 P3_5_AMUXA = 4, /* Analog mux bus A */ 1115 P3_5_AMUXB = 5, /* Analog mux bus B */ 1116 P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1117 P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1118 P3_5_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:5 */ 1119 P3_5_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:1 */ 1120 P3_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 1121 P3_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 1122 P3_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 1123 P3_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 1124 P3_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:1 */ 1125 P3_5_BLESS_MXD_DPSLP_RCB_DATA = 26, /* Digital Active - bless.mxd_dpslp_rcb_data */ 1126 1127 /* P4.0 */ 1128 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1129 P4_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1130 P4_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1131 P4_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1132 P4_0_AMUXA = 4, /* Analog mux bus A */ 1133 P4_0_AMUXB = 5, /* Analog mux bus B */ 1134 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1135 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1136 P4_0_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:5 */ 1137 P4_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:1 */ 1138 P4_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 1139 P4_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 1140 P4_0_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 1141 P4_0_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 1142 P4_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:1 */ 1143 P4_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:1 */ 1144 P4_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:1 */ 1145 P4_0_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 1146 P4_0_BLESS_MXD_DPSLP_RCB_CLK = 26, /* Digital Active - bless.mxd_dpslp_rcb_clk */ 1147 1148 /* P4.1 */ 1149 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1150 P4_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1151 P4_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1152 P4_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1153 P4_1_AMUXA = 4, /* Analog mux bus A */ 1154 P4_1_AMUXB = 5, /* Analog mux bus B */ 1155 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1156 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1157 P4_1_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:5 */ 1158 P4_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:1 */ 1159 P4_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 1160 P4_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 1161 P4_1_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 1162 P4_1_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 1163 P4_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:1 */ 1164 P4_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:1 */ 1165 P4_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:1 */ 1166 P4_1_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 1167 P4_1_BLESS_MXD_DPSLP_RCB_LE = 26, /* Digital Active - bless.mxd_dpslp_rcb_le */ 1168 1169 /* P5.0 */ 1170 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1171 P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1172 P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1173 P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1174 P5_0_AMUXA = 4, /* Analog mux bus A */ 1175 P5_0_AMUXB = 5, /* Analog mux bus B */ 1176 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1177 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1178 P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 1179 P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 1180 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 1181 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 1182 P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 1183 P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 1184 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 1185 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 1186 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 1187 P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */ 1188 P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ 1189 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 1190 1191 /* P5.1 */ 1192 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1193 P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1194 P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1195 P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1196 P5_1_AMUXA = 4, /* Analog mux bus A */ 1197 P5_1_AMUXB = 5, /* Analog mux bus B */ 1198 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1199 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1200 P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 1201 P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 1202 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 1203 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 1204 P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 1205 P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 1206 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 1207 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 1208 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 1209 P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */ 1210 P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ 1211 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 1212 1213 /* P5.2 */ 1214 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1215 P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1216 P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1217 P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1218 P5_2_AMUXA = 4, /* Analog mux bus A */ 1219 P5_2_AMUXB = 5, /* Analog mux bus B */ 1220 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1221 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1222 P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 1223 P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 1224 P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 1225 P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 1226 P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 1227 P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 1228 P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 1229 P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 1230 P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */ 1231 P5_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:0 */ 1232 1233 /* P5.3 */ 1234 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1235 P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1236 P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1237 P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1238 P5_3_AMUXA = 4, /* Analog mux bus A */ 1239 P5_3_AMUXB = 5, /* Analog mux bus B */ 1240 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1241 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1242 P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 1243 P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 1244 P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 1245 P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 1246 P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 1247 P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 1248 P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 1249 P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 1250 P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */ 1251 P5_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:0 */ 1252 1253 /* P5.4 */ 1254 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1255 P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1256 P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1257 P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1258 P5_4_AMUXA = 4, /* Analog mux bus A */ 1259 P5_4_AMUXB = 5, /* Analog mux bus B */ 1260 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1261 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1262 P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 1263 P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 1264 P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 1265 P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 1266 P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ 1267 P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ 1268 P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 1269 P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */ 1270 P5_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:0 */ 1271 1272 /* P5.5 */ 1273 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1274 P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1275 P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1276 P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1277 P5_5_AMUXA = 4, /* Analog mux bus A */ 1278 P5_5_AMUXB = 5, /* Analog mux bus B */ 1279 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1280 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1281 P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 1282 P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 1283 P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 1284 P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 1285 P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 1286 P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 1287 P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 1288 P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */ 1289 P5_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:0 */ 1290 1291 /* P5.6 */ 1292 P5_6_GPIO = 0, /* GPIO controls 'out' */ 1293 P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1294 P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1295 P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1296 P5_6_AMUXA = 4, /* Analog mux bus A */ 1297 P5_6_AMUXB = 5, /* Analog mux bus B */ 1298 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1299 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1300 P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 1301 P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 1302 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 1303 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 1304 P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 1305 P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 1306 P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 1307 P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */ 1308 P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ 1309 1310 /* P5.7 */ 1311 P5_7_GPIO = 0, /* GPIO controls 'out' */ 1312 P5_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1313 P5_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1314 P5_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1315 P5_7_AMUXA = 4, /* Analog mux bus A */ 1316 P5_7_AMUXB = 5, /* Analog mux bus B */ 1317 P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1318 P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1319 P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 1320 P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 1321 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 1322 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 1323 P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 1324 P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 1325 P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */ 1326 1327 /* P6.0 */ 1328 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1329 P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1330 P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1331 P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1332 P6_0_AMUXA = 4, /* Analog mux bus A */ 1333 P6_0_AMUXB = 5, /* Analog mux bus B */ 1334 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1335 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1336 P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 1337 P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ 1338 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 1339 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 1340 P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 1341 P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 1342 P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ 1343 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 1344 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 1345 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 1346 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 1347 P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ 1348 1349 /* P6.1 */ 1350 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1351 P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1352 P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1353 P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1354 P6_1_AMUXA = 4, /* Analog mux bus A */ 1355 P6_1_AMUXB = 5, /* Analog mux bus B */ 1356 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1357 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1358 P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 1359 P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 1360 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 1361 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 1362 P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 1363 P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 1364 P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ 1365 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 1366 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 1367 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 1368 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 1369 P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ 1370 1371 /* P6.2 */ 1372 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1373 P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1374 P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1375 P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1376 P6_2_AMUXA = 4, /* Analog mux bus A */ 1377 P6_2_AMUXB = 5, /* Analog mux bus B */ 1378 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1379 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1380 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 1381 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 1382 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 1383 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 1384 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 1385 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 1386 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 1387 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 1388 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 1389 1390 /* P6.3 */ 1391 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1392 P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1393 P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1394 P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1395 P6_3_AMUXA = 4, /* Analog mux bus A */ 1396 P6_3_AMUXB = 5, /* Analog mux bus B */ 1397 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1398 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1399 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 1400 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 1401 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 1402 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 1403 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 1404 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 1405 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 1406 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 1407 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 1408 1409 /* P6.4 */ 1410 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1411 P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1412 P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1413 P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1414 P6_4_AMUXA = 4, /* Analog mux bus A */ 1415 P6_4_AMUXB = 5, /* Analog mux bus B */ 1416 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1417 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1418 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 1419 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 1420 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 1421 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 1422 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 1423 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 1424 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 1425 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 1426 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 1427 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 1428 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 1429 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 1430 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 1431 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 1432 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1433 1434 /* P6.5 */ 1435 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1436 P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1437 P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1438 P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1439 P6_5_AMUXA = 4, /* Analog mux bus A */ 1440 P6_5_AMUXB = 5, /* Analog mux bus B */ 1441 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1442 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1443 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 1444 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 1445 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 1446 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 1447 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 1448 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 1449 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 1450 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 1451 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 1452 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 1453 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 1454 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 1455 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 1456 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 1457 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1458 1459 /* P6.6 */ 1460 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1461 P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1462 P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1463 P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1464 P6_6_AMUXA = 4, /* Analog mux bus A */ 1465 P6_6_AMUXB = 5, /* Analog mux bus B */ 1466 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1467 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1468 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 1469 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 1470 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 1471 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 1472 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 1473 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 1474 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 1475 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 1476 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 1477 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 1478 1479 /* P6.7 */ 1480 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1481 P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1482 P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1483 P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1484 P6_7_AMUXA = 4, /* Analog mux bus A */ 1485 P6_7_AMUXB = 5, /* Analog mux bus B */ 1486 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1487 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1488 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 1489 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1490 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 1491 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 1492 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 1493 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 1494 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 1495 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 1496 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 1497 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 1498 1499 /* P7.0 */ 1500 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1501 P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1502 P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1503 P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1504 P7_0_AMUXA = 4, /* Analog mux bus A */ 1505 P7_0_AMUXB = 5, /* Analog mux bus B */ 1506 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1507 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1508 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 1509 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 1510 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1511 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1512 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1513 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1514 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 1515 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 1516 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 1517 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 1518 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 1519 1520 /* P7.1 */ 1521 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1522 P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1523 P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1524 P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1525 P7_1_AMUXA = 4, /* Analog mux bus A */ 1526 P7_1_AMUXB = 5, /* Analog mux bus B */ 1527 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1528 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1529 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1530 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1531 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1532 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1533 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1534 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1535 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 1536 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 1537 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 1538 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 1539 1540 /* P7.2 */ 1541 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1542 P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1543 P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1544 P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1545 P7_2_AMUXA = 4, /* Analog mux bus A */ 1546 P7_2_AMUXB = 5, /* Analog mux bus B */ 1547 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1548 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1549 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1550 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 1551 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1552 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1553 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1554 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1555 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 1556 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 1557 1558 /* P7.3 */ 1559 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1560 P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1561 P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1562 P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1563 P7_3_AMUXA = 4, /* Analog mux bus A */ 1564 P7_3_AMUXB = 5, /* Analog mux bus B */ 1565 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1566 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1567 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1568 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1569 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1570 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1571 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1572 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1573 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 1574 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 1575 1576 /* P7.4 */ 1577 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1578 P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1579 P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1580 P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1581 P7_4_AMUXA = 4, /* Analog mux bus A */ 1582 P7_4_AMUXB = 5, /* Analog mux bus B */ 1583 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1584 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1585 P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 1586 P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ 1587 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 1588 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 1589 P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 1590 P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 1591 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ 1592 P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */ 1593 P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 1594 1595 /* P7.5 */ 1596 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1597 P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1598 P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1599 P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1600 P7_5_AMUXA = 4, /* Analog mux bus A */ 1601 P7_5_AMUXB = 5, /* Analog mux bus B */ 1602 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1603 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1604 P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 1605 P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 1606 P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 1607 P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 1608 P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 1609 P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 1610 P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ 1611 P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */ 1612 P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 1613 1614 /* P7.6 */ 1615 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1616 P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1617 P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1618 P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1619 P7_6_AMUXA = 4, /* Analog mux bus A */ 1620 P7_6_AMUXB = 5, /* Analog mux bus B */ 1621 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1622 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1623 P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 1624 P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ 1625 P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1626 P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1627 P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 1628 P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 1629 P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ 1630 P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */ 1631 P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 1632 1633 /* P7.7 */ 1634 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1635 P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1636 P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1637 P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1638 P7_7_AMUXA = 4, /* Analog mux bus A */ 1639 P7_7_AMUXB = 5, /* Analog mux bus B */ 1640 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1641 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1642 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1643 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 1644 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1645 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1646 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1647 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1648 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 1649 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 1650 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 1651 1652 /* P8.0 */ 1653 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1654 P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1655 P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1656 P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1657 P8_0_AMUXA = 4, /* Analog mux bus A */ 1658 P8_0_AMUXB = 5, /* Analog mux bus B */ 1659 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1660 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1661 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 1662 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 1663 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1664 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1665 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1666 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1667 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 1668 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 1669 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 1670 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 1671 1672 /* P8.1 */ 1673 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1674 P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1675 P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1676 P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1677 P8_1_AMUXA = 4, /* Analog mux bus A */ 1678 P8_1_AMUXB = 5, /* Analog mux bus B */ 1679 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1680 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1681 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 1682 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 1683 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1684 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1685 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1686 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1687 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 1688 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 1689 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 1690 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 1691 1692 /* P8.2 */ 1693 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1694 P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1695 P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1696 P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1697 P8_2_AMUXA = 4, /* Analog mux bus A */ 1698 P8_2_AMUXB = 5, /* Analog mux bus B */ 1699 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1700 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1701 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 1702 P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ 1703 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1704 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1705 P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1706 P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1707 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 1708 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 1709 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 1710 1711 /* P8.3 */ 1712 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1713 P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1714 P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1715 P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1716 P8_3_AMUXA = 4, /* Analog mux bus A */ 1717 P8_3_AMUXB = 5, /* Analog mux bus B */ 1718 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1719 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1720 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 1721 P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 1722 P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1723 P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1724 P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1725 P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1726 P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 1727 P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 1728 P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 1729 1730 /* P8.4 */ 1731 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1732 P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1733 P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1734 P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1735 P8_4_AMUXA = 4, /* Analog mux bus A */ 1736 P8_4_AMUXB = 5, /* Analog mux bus B */ 1737 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1738 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1739 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 1740 P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ 1741 P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1742 P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1743 P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1744 P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1745 P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ 1746 1747 /* P8.5 */ 1748 P8_5_GPIO = 0, /* GPIO controls 'out' */ 1749 P8_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1750 P8_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1751 P8_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1752 P8_5_AMUXA = 4, /* Analog mux bus A */ 1753 P8_5_AMUXB = 5, /* Analog mux bus B */ 1754 P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1755 P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1756 P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ 1757 P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ 1758 P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1759 P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1760 P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1761 P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1762 P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ 1763 1764 /* P8.6 */ 1765 P8_6_GPIO = 0, /* GPIO controls 'out' */ 1766 P8_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1767 P8_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1768 P8_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1769 P8_6_AMUXA = 4, /* Analog mux bus A */ 1770 P8_6_AMUXB = 5, /* Analog mux bus B */ 1771 P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1772 P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1773 P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 1774 P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */ 1775 P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ 1776 P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ 1777 P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */ 1778 P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */ 1779 P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */ 1780 1781 /* P8.7 */ 1782 P8_7_GPIO = 0, /* GPIO controls 'out' */ 1783 P8_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1784 P8_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1785 P8_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1786 P8_7_AMUXA = 4, /* Analog mux bus A */ 1787 P8_7_AMUXB = 5, /* Analog mux bus B */ 1788 P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1789 P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1790 P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 1791 P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ 1792 P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ 1793 P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ 1794 P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */ 1795 P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */ 1796 P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */ 1797 1798 /* P9.0 */ 1799 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1800 P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1801 P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1802 P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1803 P9_0_AMUXA = 4, /* Analog mux bus A */ 1804 P9_0_AMUXB = 5, /* Analog mux bus B */ 1805 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1806 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1807 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 1808 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 1809 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1810 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1811 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 1812 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 1813 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 1814 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 1815 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 1816 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 1817 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1818 1819 /* P9.1 */ 1820 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1821 P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1822 P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1823 P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1824 P9_1_AMUXA = 4, /* Analog mux bus A */ 1825 P9_1_AMUXB = 5, /* Analog mux bus B */ 1826 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1827 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1828 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 1829 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 1830 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1831 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1832 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1833 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1834 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 1835 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 1836 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 1837 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 1838 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1839 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1840 1841 /* P9.2 */ 1842 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1843 P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1844 P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1845 P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1846 P9_2_AMUXA = 4, /* Analog mux bus A */ 1847 P9_2_AMUXB = 5, /* Analog mux bus B */ 1848 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1849 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1850 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 1851 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 1852 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 1853 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 1854 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1855 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1856 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1857 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1858 P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ 1859 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1860 1861 /* P9.3 */ 1862 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1863 P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1864 P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1865 P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1866 P9_3_AMUXA = 4, /* Analog mux bus A */ 1867 P9_3_AMUXB = 5, /* Analog mux bus B */ 1868 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1869 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1870 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 1871 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1872 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 1873 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 1874 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1875 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1876 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1877 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1878 P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ 1879 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1880 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1881 1882 /* P9.4 */ 1883 P9_4_GPIO = 0, /* GPIO controls 'out' */ 1884 P9_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1885 P9_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1886 P9_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1887 P9_4_AMUXA = 4, /* Analog mux bus A */ 1888 P9_4_AMUXB = 5, /* Analog mux bus B */ 1889 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1890 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1891 P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ 1892 P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ 1893 P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ 1894 P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ 1895 P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ 1896 P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ 1897 P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ 1898 1899 /* P9.5 */ 1900 P9_5_GPIO = 0, /* GPIO controls 'out' */ 1901 P9_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1902 P9_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1903 P9_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1904 P9_5_AMUXA = 4, /* Analog mux bus A */ 1905 P9_5_AMUXB = 5, /* Analog mux bus B */ 1906 P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1907 P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1908 P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */ 1909 P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ 1910 P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */ 1911 P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */ 1912 P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */ 1913 P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */ 1914 P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ 1915 1916 /* P9.6 */ 1917 P9_6_GPIO = 0, /* GPIO controls 'out' */ 1918 P9_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1919 P9_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1920 P9_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1921 P9_6_AMUXA = 4, /* Analog mux bus A */ 1922 P9_6_AMUXB = 5, /* Analog mux bus B */ 1923 P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1924 P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1925 P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 1926 P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ 1927 P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */ 1928 P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */ 1929 P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */ 1930 P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */ 1931 P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */ 1932 1933 /* P9.7 */ 1934 P9_7_GPIO = 0, /* GPIO controls 'out' */ 1935 P9_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1936 P9_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1937 P9_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1938 P9_7_AMUXA = 4, /* Analog mux bus A */ 1939 P9_7_AMUXB = 5, /* Analog mux bus B */ 1940 P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1941 P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1942 P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1943 P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 1944 P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ 1945 P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ 1946 P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ 1947 P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ 1948 1949 /* P10.0 */ 1950 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1951 P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1952 P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1953 P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1954 P10_0_AMUXA = 4, /* Analog mux bus A */ 1955 P10_0_AMUXB = 5, /* Analog mux bus B */ 1956 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1957 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1958 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 1959 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 1960 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 1961 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 1962 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 1963 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 1964 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1965 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1966 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1967 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1968 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1969 1970 /* P10.1 */ 1971 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1972 P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1973 P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1974 P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1975 P10_1_AMUXA = 4, /* Analog mux bus A */ 1976 P10_1_AMUXB = 5, /* Analog mux bus B */ 1977 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1978 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1979 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 1980 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1981 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 1982 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 1983 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 1984 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 1985 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1986 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1987 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1988 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1989 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1990 1991 /* P10.2 */ 1992 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1993 P10_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1994 P10_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1995 P10_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1996 P10_2_AMUXA = 4, /* Analog mux bus A */ 1997 P10_2_AMUXB = 5, /* Analog mux bus B */ 1998 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1999 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2000 P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ 2001 P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ 2002 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ 2003 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ 2004 P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ 2005 P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ 2006 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 2007 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 2008 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 2009 2010 /* P10.3 */ 2011 P10_3_GPIO = 0, /* GPIO controls 'out' */ 2012 P10_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2013 P10_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2014 P10_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2015 P10_3_AMUXA = 4, /* Analog mux bus A */ 2016 P10_3_AMUXB = 5, /* Analog mux bus B */ 2017 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2018 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2019 P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ 2020 P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 2021 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ 2022 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ 2023 P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ 2024 P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ 2025 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 2026 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 2027 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 2028 2029 /* P10.4 */ 2030 P10_4_GPIO = 0, /* GPIO controls 'out' */ 2031 P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2032 P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2033 P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2034 P10_4_AMUXA = 4, /* Analog mux bus A */ 2035 P10_4_AMUXB = 5, /* Analog mux bus B */ 2036 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2037 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2038 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 2039 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 2040 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ 2041 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ 2042 P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ 2043 P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ 2044 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 2045 P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:0 */ 2046 P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0:0 */ 2047 2048 /* P10.5 */ 2049 P10_5_GPIO = 0, /* GPIO controls 'out' */ 2050 P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2051 P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2052 P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2053 P10_5_AMUXA = 4, /* Analog mux bus A */ 2054 P10_5_AMUXB = 5, /* Analog mux bus B */ 2055 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2056 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2057 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 2058 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 2059 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ 2060 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ 2061 P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ 2062 P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ 2063 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 2064 P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:0 */ 2065 P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0:0 */ 2066 2067 /* P10.6 */ 2068 P10_6_GPIO = 0, /* GPIO controls 'out' */ 2069 P10_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2070 P10_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2071 P10_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2072 P10_6_AMUXA = 4, /* Analog mux bus A */ 2073 P10_6_AMUXB = 5, /* Analog mux bus B */ 2074 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2075 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2076 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 2077 P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 2078 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ 2079 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ 2080 P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ 2081 P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ 2082 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 2083 2084 /* P10.7 */ 2085 P10_7_GPIO = 0, /* GPIO controls 'out' */ 2086 P10_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2087 P10_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2088 P10_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2089 P10_7_AMUXA = 4, /* Analog mux bus A */ 2090 P10_7_AMUXB = 5, /* Analog mux bus B */ 2091 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2092 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2093 P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ 2094 P10_7_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ 2095 P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:77 */ 2096 P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:77 */ 2097 P10_7_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:1 */ 2098 P10_7_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:1 */ 2099 2100 /* P11.0 */ 2101 P11_0_GPIO = 0, /* GPIO controls 'out' */ 2102 P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2103 P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2104 P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2105 P11_0_AMUXA = 4, /* Analog mux bus A */ 2106 P11_0_AMUXB = 5, /* Analog mux bus B */ 2107 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2108 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2109 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 2110 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 2111 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 2112 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 2113 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 2114 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 2115 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 2116 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 2117 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 2118 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 2119 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 2120 2121 /* P11.1 */ 2122 P11_1_GPIO = 0, /* GPIO controls 'out' */ 2123 P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2124 P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2125 P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2126 P11_1_AMUXA = 4, /* Analog mux bus A */ 2127 P11_1_AMUXB = 5, /* Analog mux bus B */ 2128 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2129 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2130 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 2131 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 2132 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 2133 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 2134 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 2135 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 2136 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 2137 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 2138 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 2139 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 2140 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 2141 2142 /* P11.2 */ 2143 P11_2_GPIO = 0, /* GPIO controls 'out' */ 2144 P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2145 P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2146 P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2147 P11_2_AMUXA = 4, /* Analog mux bus A */ 2148 P11_2_AMUXB = 5, /* Analog mux bus B */ 2149 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2150 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2151 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 2152 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 2153 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 2154 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 2155 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 2156 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 2157 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 2158 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 2159 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 2160 2161 /* P11.3 */ 2162 P11_3_GPIO = 0, /* GPIO controls 'out' */ 2163 P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2164 P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2165 P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2166 P11_3_AMUXA = 4, /* Analog mux bus A */ 2167 P11_3_AMUXB = 5, /* Analog mux bus B */ 2168 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2169 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2170 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 2171 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 2172 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 2173 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 2174 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 2175 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 2176 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 2177 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 2178 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 2179 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 2180 2181 /* P11.4 */ 2182 P11_4_GPIO = 0, /* GPIO controls 'out' */ 2183 P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2184 P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2185 P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2186 P11_4_AMUXA = 4, /* Analog mux bus A */ 2187 P11_4_AMUXB = 5, /* Analog mux bus B */ 2188 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2189 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2190 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 2191 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 2192 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 2193 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 2194 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 2195 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 2196 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 2197 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 2198 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 2199 2200 /* P11.5 */ 2201 P11_5_GPIO = 0, /* GPIO controls 'out' */ 2202 P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2203 P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2204 P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2205 P11_5_AMUXA = 4, /* Analog mux bus A */ 2206 P11_5_AMUXB = 5, /* Analog mux bus B */ 2207 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2208 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2209 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 2210 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 2211 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 2212 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 2213 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 2214 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 2215 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 2216 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 2217 2218 /* P11.6 */ 2219 P11_6_GPIO = 0, /* GPIO controls 'out' */ 2220 P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2221 P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2222 P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2223 P11_6_AMUXA = 4, /* Analog mux bus A */ 2224 P11_6_AMUXB = 5, /* Analog mux bus B */ 2225 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2226 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2227 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 2228 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 2229 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 2230 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 2231 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 2232 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 2233 2234 /* P11.7 */ 2235 P11_7_GPIO = 0, /* GPIO controls 'out' */ 2236 P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2237 P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2238 P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2239 P11_7_AMUXA = 4, /* Analog mux bus A */ 2240 P11_7_AMUXB = 5, /* Analog mux bus B */ 2241 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2242 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2243 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 2244 2245 /* P12.0 */ 2246 P12_0_GPIO = 0, /* GPIO controls 'out' */ 2247 P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2248 P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2249 P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2250 P12_0_AMUXA = 4, /* Analog mux bus A */ 2251 P12_0_AMUXB = 5, /* Analog mux bus B */ 2252 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2253 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2254 P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ 2255 P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 2256 P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ 2257 P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ 2258 P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ 2259 P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ 2260 P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 2261 P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 2262 P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 2263 P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 2264 P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 2265 2266 /* P12.1 */ 2267 P12_1_GPIO = 0, /* GPIO controls 'out' */ 2268 P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2269 P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2270 P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2271 P12_1_AMUXA = 4, /* Analog mux bus A */ 2272 P12_1_AMUXB = 5, /* Analog mux bus B */ 2273 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2274 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2275 P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ 2276 P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 2277 P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ 2278 P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ 2279 P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ 2280 P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ 2281 P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 2282 P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 2283 P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 2284 P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 2285 P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 2286 2287 /* P12.2 */ 2288 P12_2_GPIO = 0, /* GPIO controls 'out' */ 2289 P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2290 P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2291 P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2292 P12_2_AMUXA = 4, /* Analog mux bus A */ 2293 P12_2_AMUXB = 5, /* Analog mux bus B */ 2294 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2295 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2296 P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ 2297 P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 2298 P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ 2299 P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ 2300 P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ 2301 P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ 2302 P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 2303 P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 2304 P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 2305 2306 /* P12.3 */ 2307 P12_3_GPIO = 0, /* GPIO controls 'out' */ 2308 P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2309 P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2310 P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2311 P12_3_AMUXA = 4, /* Analog mux bus A */ 2312 P12_3_AMUXB = 5, /* Analog mux bus B */ 2313 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2314 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2315 P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ 2316 P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 2317 P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ 2318 P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ 2319 P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ 2320 P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ 2321 P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 2322 P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 2323 P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 2324 2325 /* P12.4 */ 2326 P12_4_GPIO = 0, /* GPIO controls 'out' */ 2327 P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2328 P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2329 P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2330 P12_4_AMUXA = 4, /* Analog mux bus A */ 2331 P12_4_AMUXB = 5, /* Analog mux bus B */ 2332 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2333 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2334 P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ 2335 P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 2336 P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ 2337 P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ 2338 P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ 2339 P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ 2340 P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ 2341 P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 2342 P12_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:1 */ 2343 P12_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:1:0 */ 2344 2345 /* P12.5 */ 2346 P12_5_GPIO = 0, /* GPIO controls 'out' */ 2347 P12_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2348 P12_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2349 P12_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2350 P12_5_AMUXA = 4, /* Analog mux bus A */ 2351 P12_5_AMUXB = 5, /* Analog mux bus B */ 2352 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2353 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2354 P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ 2355 P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 2356 P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ 2357 P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ 2358 P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ 2359 P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ 2360 P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ 2361 P12_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:1 */ 2362 P12_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:1:0 */ 2363 2364 /* P12.6 */ 2365 P12_6_GPIO = 0, /* GPIO controls 'out' */ 2366 P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2367 P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2368 P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2369 P12_6_AMUXA = 4, /* Analog mux bus A */ 2370 P12_6_AMUXB = 5, /* Analog mux bus B */ 2371 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2372 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2373 P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ 2374 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 2375 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ 2376 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ 2377 P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ 2378 P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ 2379 P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 2380 2381 /* P12.7 */ 2382 P12_7_GPIO = 0, /* GPIO controls 'out' */ 2383 P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2384 P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2385 P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2386 P12_7_AMUXA = 4, /* Analog mux bus A */ 2387 P12_7_AMUXB = 5, /* Analog mux bus B */ 2388 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2389 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2390 P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ 2391 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 2392 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ 2393 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ 2394 P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ 2395 P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ 2396 2397 /* P13.0 */ 2398 P13_0_GPIO = 0, /* GPIO controls 'out' */ 2399 P13_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2400 P13_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2401 P13_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2402 P13_0_AMUXA = 4, /* Analog mux bus A */ 2403 P13_0_AMUXB = 5, /* Analog mux bus B */ 2404 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2405 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2406 P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 2407 P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ 2408 P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ 2409 P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ 2410 P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ 2411 P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ 2412 P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ 2413 P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ 2414 P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ 2415 P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ 2416 2417 /* P13.1 */ 2418 P13_1_GPIO = 0, /* GPIO controls 'out' */ 2419 P13_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2420 P13_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2421 P13_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2422 P13_1_AMUXA = 4, /* Analog mux bus A */ 2423 P13_1_AMUXB = 5, /* Analog mux bus B */ 2424 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2425 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2426 P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 2427 P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 2428 P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ 2429 P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ 2430 P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ 2431 P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ 2432 P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ 2433 P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ 2434 P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ 2435 P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ 2436 2437 /* P13.2 */ 2438 P13_2_GPIO = 0, /* GPIO controls 'out' */ 2439 P13_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2440 P13_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2441 P13_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2442 P13_2_AMUXA = 4, /* Analog mux bus A */ 2443 P13_2_AMUXB = 5, /* Analog mux bus B */ 2444 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2445 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2446 P13_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 2447 P13_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:1 */ 2448 P13_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:95 */ 2449 P13_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:95 */ 2450 P13_2_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:1 */ 2451 P13_2_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:1 */ 2452 P13_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:1 */ 2453 P13_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:1 */ 2454 2455 /* P13.3 */ 2456 P13_3_GPIO = 0, /* GPIO controls 'out' */ 2457 P13_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2458 P13_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2459 P13_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2460 P13_3_AMUXA = 4, /* Analog mux bus A */ 2461 P13_3_AMUXB = 5, /* Analog mux bus B */ 2462 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2463 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2464 P13_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 2465 P13_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:1 */ 2466 P13_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:96 */ 2467 P13_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:96 */ 2468 P13_3_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:1 */ 2469 P13_3_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:1 */ 2470 P13_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:1 */ 2471 P13_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:1 */ 2472 2473 /* P13.4 */ 2474 P13_4_GPIO = 0, /* GPIO controls 'out' */ 2475 P13_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2476 P13_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2477 P13_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2478 P13_4_AMUXA = 4, /* Analog mux bus A */ 2479 P13_4_AMUXB = 5, /* Analog mux bus B */ 2480 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2481 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2482 P13_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 2483 P13_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:1 */ 2484 P13_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:97 */ 2485 P13_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:97 */ 2486 P13_4_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:1 */ 2487 P13_4_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:1 */ 2488 P13_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:1 */ 2489 2490 /* P13.5 */ 2491 P13_5_GPIO = 0, /* GPIO controls 'out' */ 2492 P13_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2493 P13_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2494 P13_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2495 P13_5_AMUXA = 4, /* Analog mux bus A */ 2496 P13_5_AMUXB = 5, /* Analog mux bus B */ 2497 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2498 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2499 P13_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 2500 P13_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:1 */ 2501 P13_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:98 */ 2502 P13_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:98 */ 2503 P13_5_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:1 */ 2504 P13_5_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:1 */ 2505 P13_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:1 */ 2506 2507 /* P13.6 */ 2508 P13_6_GPIO = 0, /* GPIO controls 'out' */ 2509 P13_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2510 P13_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2511 P13_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2512 P13_6_AMUXA = 4, /* Analog mux bus A */ 2513 P13_6_AMUXB = 5, /* Analog mux bus B */ 2514 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2515 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2516 P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ 2517 P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */ 2518 P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */ 2519 P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */ 2520 P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */ 2521 P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */ 2522 P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */ 2523 2524 /* P13.7 */ 2525 P13_7_GPIO = 0, /* GPIO controls 'out' */ 2526 P13_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 2527 P13_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2528 P13_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2529 P13_7_AMUXA = 4, /* Analog mux bus A */ 2530 P13_7_AMUXB = 5, /* Analog mux bus B */ 2531 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2532 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2533 P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ 2534 P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ 2535 P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ 2536 P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ 2537 P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ 2538 P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ 2539 2540 /* USBDP */ 2541 USBDP_GPIO = 0, /* GPIO controls 'out' */ 2542 2543 /* USBDM */ 2544 USBDM_GPIO = 0 /* GPIO controls 'out' */ 2545 } en_hsiom_sel_t; 2546 2547 #endif /* _GPIO_PSOC6_01_124_BGA_H_ */ 2548 2549 2550 /* [] END OF FILE */ 2551
