1 /***************************************************************************//** 2 * \file cyhal_cyw20829_56_qfn.h 3 * 4 * \brief 5 * CYW20829 device GPIO HAL header for 56-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_CYW20829_56_QFN_H_ 28 #define _CYHAL_CYW20829_56_QFN_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_cyw20829_56_qfn CYW20829 56-QFN 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the CYW20829 56-QFN package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 56-QFN package for the CYW20829 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 60 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 61 62 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 63 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 64 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 65 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 66 P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 67 P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 68 P1_6 = CYHAL_GET_GPIO(CYHAL_PORT_1, 6), //!< Port 1 Pin 6 69 70 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 71 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 72 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 73 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 74 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 75 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 76 77 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 78 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 79 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 80 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 81 P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 82 P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 83 P3_6 = CYHAL_GET_GPIO(CYHAL_PORT_3, 6), //!< Port 3 Pin 6 84 P3_7 = CYHAL_GET_GPIO(CYHAL_PORT_3, 7), //!< Port 3 Pin 7 85 86 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 87 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 88 89 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 90 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 91 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 92 } cyhal_gpio_cyw20829_56_qfn_t; 93 94 /** Create generic name for the series/package specific type. */ 95 typedef cyhal_gpio_cyw20829_56_qfn_t cyhal_gpio_t; 96 97 /* Connection type definition */ 98 /** Represents an association between a pin and a resource */ 99 typedef struct 100 { 101 uint8_t block_num; //!< The block number of the resource with this connection 102 uint8_t channel_num; //!< The channel number of the block with this connection 103 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 104 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 105 } cyhal_resource_pin_mapping_t; 106 107 /* Pin connections */ 108 /** Indicates that a pin map exists for adcmic_clk_pdm*/ 109 #define CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_CLK_PDM (CY_GPIO_DM_HIGHZ) 110 /** List of valid pin to peripheral connections for the adcmic_clk_pdm signal. */ 111 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_clk_pdm[2]; 112 /** Indicates that a pin map exists for adcmic_gpio_adc_in*/ 113 #define CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_GPIO_ADC_IN (CY_GPIO_DM_ANALOG) 114 /** List of valid pin to peripheral connections for the adcmic_gpio_adc_in signal. */ 115 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_gpio_adc_in[8]; 116 /** Indicates that a pin map exists for adcmic_pdm_data*/ 117 #define CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_PDM_DATA (CY_GPIO_DM_HIGHZ) 118 /** List of valid pin to peripheral connections for the adcmic_pdm_data signal. */ 119 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_pdm_data[2]; 120 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 121 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 122 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 123 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[2]; 124 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 125 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 126 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 127 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[2]; 128 /** Indicates that a pin map exists for cpuss_clk_swj_swclk_tclk*/ 129 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 130 /** List of valid pin to peripheral connections for the cpuss_clk_swj_swclk_tclk signal. */ 131 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_swj_swclk_tclk[1]; 132 /** Indicates that a pin map exists for cpuss_rst_swj_trstn*/ 133 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_RST_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 134 /** List of valid pin to peripheral connections for the cpuss_rst_swj_trstn signal. */ 135 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_rst_swj_trstn[1]; 136 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 137 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 138 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 139 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 140 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 141 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 142 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 143 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 144 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 145 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 146 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 147 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 148 /** Indicates that a pin map exists for cpuss_trace_clock*/ 149 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 150 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 151 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2]; 152 /** Indicates that a pin map exists for cpuss_trace_data*/ 153 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 154 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 155 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 156 /** Indicates that a pin map exists for keyscan_ks_col*/ 157 #define CYHAL_PIN_MAP_DRIVE_MODE_KEYSCAN_KS_COL (CY_GPIO_DM_PULLUP) 158 /** List of valid pin to peripheral connections for the keyscan_ks_col signal. */ 159 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_col[20]; 160 /** Indicates that a pin map exists for keyscan_ks_row*/ 161 #define CYHAL_PIN_MAP_DRIVE_MODE_KEYSCAN_KS_ROW (CY_GPIO_DM_PULLUP) 162 /** List of valid pin to peripheral connections for the keyscan_ks_row signal. */ 163 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_row[8]; 164 /** Indicates that a pin map exists for lin_lin_en*/ 165 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 166 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 167 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[2]; 168 /** Indicates that a pin map exists for lin_lin_rx*/ 169 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 170 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 171 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[2]; 172 /** Indicates that a pin map exists for lin_lin_tx*/ 173 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 174 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 175 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[2]; 176 /** Indicates that a pin map exists for pdm_pdm_clk*/ 177 #define CYHAL_PIN_MAP_DRIVE_MODE_PDM_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF) 178 /** List of valid pin to peripheral connections for the pdm_pdm_clk signal. */ 179 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_clk[4]; 180 /** Indicates that a pin map exists for pdm_pdm_data*/ 181 #define CYHAL_PIN_MAP_DRIVE_MODE_PDM_PDM_DATA (CY_GPIO_DM_HIGHZ) 182 /** List of valid pin to peripheral connections for the pdm_pdm_data signal. */ 183 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_data[4]; 184 /** Indicates that a pin map exists for peri_tr_io_input*/ 185 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 186 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 187 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[8]; 188 /** Indicates that a pin map exists for peri_tr_io_output*/ 189 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 190 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 191 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2]; 192 /** Indicates that a pin map exists for scb_i2c_scl*/ 193 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 194 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 195 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[5]; 196 /** Indicates that a pin map exists for scb_i2c_sda*/ 197 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 198 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 199 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[5]; 200 /** Indicates that a pin map exists for scb_spi_m_clk*/ 201 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 202 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 203 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[3]; 204 /** Indicates that a pin map exists for scb_spi_m_miso*/ 205 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 206 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 207 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[4]; 208 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 209 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 210 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 211 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[4]; 212 /** Indicates that a pin map exists for scb_spi_m_select0*/ 213 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 214 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 215 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[4]; 216 /** Indicates that a pin map exists for scb_spi_m_select1*/ 217 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 218 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 219 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[3]; 220 /** Indicates that a pin map exists for scb_spi_m_select2*/ 221 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 222 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 223 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[3]; 224 /** Indicates that a pin map exists for scb_spi_m_select3*/ 225 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 226 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 227 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2]; 228 /** Indicates that a pin map exists for scb_spi_s_clk*/ 229 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 230 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 231 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[3]; 232 /** Indicates that a pin map exists for scb_spi_s_miso*/ 233 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 234 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 235 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[4]; 236 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 237 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 238 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 239 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[4]; 240 /** Indicates that a pin map exists for scb_spi_s_select0*/ 241 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 242 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 243 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[4]; 244 /** Indicates that a pin map exists for scb_spi_s_select1*/ 245 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 246 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 247 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[3]; 248 /** Indicates that a pin map exists for scb_spi_s_select2*/ 249 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 250 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 251 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[3]; 252 /** Indicates that a pin map exists for scb_spi_s_select3*/ 253 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 254 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 255 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2]; 256 /** Indicates that a pin map exists for scb_uart_cts*/ 257 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 258 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 259 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[4]; 260 /** Indicates that a pin map exists for scb_uart_rts*/ 261 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 262 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 263 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[2]; 264 /** Indicates that a pin map exists for scb_uart_rx*/ 265 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 266 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 267 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[2]; 268 /** Indicates that a pin map exists for scb_uart_tx*/ 269 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 270 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 271 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[2]; 272 /** Indicates that a pin map exists for smif_spi_clk*/ 273 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 274 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 275 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 276 /** Indicates that a pin map exists for smif_spi_data0*/ 277 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 278 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 279 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 280 /** Indicates that a pin map exists for smif_spi_data1*/ 281 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 282 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 283 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 284 /** Indicates that a pin map exists for smif_spi_data2*/ 285 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 286 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 287 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 288 /** Indicates that a pin map exists for smif_spi_data3*/ 289 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 290 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 291 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 292 /** Indicates that a pin map exists for smif_spi_select0*/ 293 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 294 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 295 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 296 /** Indicates that a pin map exists for smif_spi_select1*/ 297 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 298 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 299 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 300 /** Indicates that a pin map exists for tcpwm_line*/ 301 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 302 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 303 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[26]; 304 /** Indicates that a pin map exists for tcpwm_line_compl*/ 305 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 306 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 307 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[26]; 308 /** Indicates that a pin map exists for tdm_tdm_rx_fsync*/ 309 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_FSYNC (CY_GPIO_DM_STRONG_IN_OFF) 310 /** List of valid pin to peripheral connections for the tdm_tdm_rx_fsync signal. */ 311 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_fsync[1]; 312 /** Indicates that a pin map exists for tdm_tdm_rx_mck*/ 313 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_MCK (CY_GPIO_DM_STRONG_IN_OFF) 314 /** List of valid pin to peripheral connections for the tdm_tdm_rx_mck signal. */ 315 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_mck[1]; 316 /** Indicates that a pin map exists for tdm_tdm_rx_sck*/ 317 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 318 /** List of valid pin to peripheral connections for the tdm_tdm_rx_sck signal. */ 319 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sck[1]; 320 /** Indicates that a pin map exists for tdm_tdm_rx_sd*/ 321 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_SD (CY_GPIO_DM_HIGHZ) 322 /** List of valid pin to peripheral connections for the tdm_tdm_rx_sd signal. */ 323 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sd[1]; 324 /** Indicates that a pin map exists for tdm_tdm_tx_fsync*/ 325 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_FSYNC (CY_GPIO_DM_STRONG_IN_OFF) 326 /** List of valid pin to peripheral connections for the tdm_tdm_tx_fsync signal. */ 327 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_fsync[1]; 328 /** Indicates that a pin map exists for tdm_tdm_tx_mck*/ 329 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_MCK (CY_GPIO_DM_STRONG_IN_OFF) 330 /** List of valid pin to peripheral connections for the tdm_tdm_tx_mck signal. */ 331 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_mck[1]; 332 /** Indicates that a pin map exists for tdm_tdm_tx_sck*/ 333 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 334 /** List of valid pin to peripheral connections for the tdm_tdm_tx_sck signal. */ 335 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sck[1]; 336 /** Indicates that a pin map exists for tdm_tdm_tx_sd*/ 337 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_SD (CY_GPIO_DM_STRONG_IN_OFF) 338 /** List of valid pin to peripheral connections for the tdm_tdm_tx_sd signal. */ 339 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sd[1]; 340 341 #if defined(__cplusplus) 342 } 343 #endif /* __cplusplus */ 344 345 /** \} group_hal_impl_pin_package */ 346 347 #endif /* _CYHAL_CYW20829_56_QFN_H_ */ 348 349 350 /* [] END OF FILE */ 351
