1 /***************************************************************************//** 2 * \file cyhal_cyw20829_40_qfn.h 3 * 4 * \brief 5 * CYW20829 device GPIO HAL header for 40-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_CYW20829_40_QFN_H_ 28 #define _CYHAL_CYW20829_40_QFN_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_cyw20829_40_qfn CYW20829 40-QFN 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the CYW20829 40-QFN package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 40-QFN package for the CYW20829 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 56 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 57 58 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 59 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 60 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 61 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 62 63 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 64 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 65 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 66 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 67 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 68 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 69 70 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 71 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 72 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 73 74 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 75 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 76 77 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 78 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 79 } cyhal_gpio_cyw20829_40_qfn_t; 80 81 /** Create generic name for the series/package specific type. */ 82 typedef cyhal_gpio_cyw20829_40_qfn_t cyhal_gpio_t; 83 84 /* Connection type definition */ 85 /** Represents an association between a pin and a resource */ 86 typedef struct 87 { 88 uint8_t block_num; //!< The block number of the resource with this connection 89 uint8_t channel_num; //!< The channel number of the block with this connection 90 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 91 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 92 } cyhal_resource_pin_mapping_t; 93 94 /* Pin connections */ 95 /** Indicates that a pin map exists for adcmic_clk_pdm*/ 96 #define CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_CLK_PDM (CY_GPIO_DM_HIGHZ) 97 /** List of valid pin to peripheral connections for the adcmic_clk_pdm signal. */ 98 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_clk_pdm[2]; 99 /** Indicates that a pin map exists for adcmic_gpio_adc_in*/ 100 #define CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_GPIO_ADC_IN (CY_GPIO_DM_ANALOG) 101 /** List of valid pin to peripheral connections for the adcmic_gpio_adc_in signal. */ 102 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_gpio_adc_in[3]; 103 /** Indicates that a pin map exists for adcmic_pdm_data*/ 104 #define CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_PDM_DATA (CY_GPIO_DM_HIGHZ) 105 /** List of valid pin to peripheral connections for the adcmic_pdm_data signal. */ 106 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_pdm_data[2]; 107 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 108 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 109 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 110 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[2]; 111 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 112 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 113 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 114 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[2]; 115 /** Indicates that a pin map exists for cpuss_clk_swj_swclk_tclk*/ 116 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 117 /** List of valid pin to peripheral connections for the cpuss_clk_swj_swclk_tclk signal. */ 118 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_swj_swclk_tclk[1]; 119 /** Indicates that a pin map exists for cpuss_rst_swj_trstn*/ 120 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_RST_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 121 /** List of valid pin to peripheral connections for the cpuss_rst_swj_trstn signal. */ 122 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_rst_swj_trstn[1]; 123 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 124 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 125 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 126 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 127 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 128 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 129 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 130 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 131 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 132 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 133 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 134 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 135 /** Indicates that a pin map exists for cpuss_trace_clock*/ 136 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 137 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 138 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 139 /** Indicates that a pin map exists for cpuss_trace_data*/ 140 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 141 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 142 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[7]; 143 /** Indicates that a pin map exists for keyscan_ks_col*/ 144 #define CYHAL_PIN_MAP_DRIVE_MODE_KEYSCAN_KS_COL (CY_GPIO_DM_PULLUP) 145 /** List of valid pin to peripheral connections for the keyscan_ks_col signal. */ 146 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_col[2]; 147 /** Indicates that a pin map exists for keyscan_ks_row*/ 148 #define CYHAL_PIN_MAP_DRIVE_MODE_KEYSCAN_KS_ROW (CY_GPIO_DM_PULLUP) 149 /** List of valid pin to peripheral connections for the keyscan_ks_row signal. */ 150 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_row[7]; 151 /** Indicates that a pin map exists for lin_lin_en*/ 152 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 153 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 154 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[1]; 155 /** Indicates that a pin map exists for lin_lin_rx*/ 156 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 157 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 158 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[1]; 159 /** Indicates that a pin map exists for lin_lin_tx*/ 160 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 161 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 162 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[1]; 163 /** Indicates that a pin map exists for pdm_pdm_clk*/ 164 #define CYHAL_PIN_MAP_DRIVE_MODE_PDM_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF) 165 /** List of valid pin to peripheral connections for the pdm_pdm_clk signal. */ 166 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_clk[3]; 167 /** Indicates that a pin map exists for pdm_pdm_data*/ 168 #define CYHAL_PIN_MAP_DRIVE_MODE_PDM_PDM_DATA (CY_GPIO_DM_HIGHZ) 169 /** List of valid pin to peripheral connections for the pdm_pdm_data signal. */ 170 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_data[3]; 171 /** Indicates that a pin map exists for peri_tr_io_input*/ 172 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 173 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 174 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[6]; 175 /** Indicates that a pin map exists for peri_tr_io_output*/ 176 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 177 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 178 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2]; 179 /** Indicates that a pin map exists for scb_i2c_scl*/ 180 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 181 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 182 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[4]; 183 /** Indicates that a pin map exists for scb_i2c_sda*/ 184 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 185 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 186 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[4]; 187 /** Indicates that a pin map exists for scb_spi_m_clk*/ 188 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 189 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 190 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[3]; 191 /** Indicates that a pin map exists for scb_spi_m_miso*/ 192 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 193 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 194 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[3]; 195 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 196 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 197 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 198 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[3]; 199 /** Indicates that a pin map exists for scb_spi_m_select0*/ 200 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 201 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 202 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[3]; 203 /** Indicates that a pin map exists for scb_spi_m_select1*/ 204 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 205 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 206 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[1]; 207 /** Indicates that a pin map exists for scb_spi_m_select2*/ 208 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 209 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 210 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[1]; 211 /** Indicates that a pin map exists for scb_spi_m_select3*/ 212 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 213 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 214 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[1]; 215 /** Indicates that a pin map exists for scb_spi_s_clk*/ 216 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 217 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 218 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[3]; 219 /** Indicates that a pin map exists for scb_spi_s_miso*/ 220 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 221 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 222 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[3]; 223 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 224 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 225 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 226 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[3]; 227 /** Indicates that a pin map exists for scb_spi_s_select0*/ 228 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 229 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 230 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[3]; 231 /** Indicates that a pin map exists for scb_spi_s_select1*/ 232 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 233 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 234 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[1]; 235 /** Indicates that a pin map exists for scb_spi_s_select2*/ 236 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 237 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 238 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[1]; 239 /** Indicates that a pin map exists for scb_spi_s_select3*/ 240 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 241 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 242 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[1]; 243 /** Indicates that a pin map exists for scb_uart_cts*/ 244 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 245 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 246 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[3]; 247 /** Indicates that a pin map exists for scb_uart_rts*/ 248 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 249 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 250 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[2]; 251 /** Indicates that a pin map exists for scb_uart_rx*/ 252 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 253 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 254 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[2]; 255 /** Indicates that a pin map exists for scb_uart_tx*/ 256 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 257 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 258 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[2]; 259 /** Indicates that a pin map exists for smif_spi_clk*/ 260 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 261 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 262 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 263 /** Indicates that a pin map exists for smif_spi_data0*/ 264 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 265 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 266 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 267 /** Indicates that a pin map exists for smif_spi_data1*/ 268 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 269 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 270 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 271 /** Indicates that a pin map exists for smif_spi_data2*/ 272 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 273 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 274 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 275 /** Indicates that a pin map exists for smif_spi_data3*/ 276 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 277 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 278 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 279 /** Indicates that a pin map exists for smif_spi_select0*/ 280 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 281 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 282 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 283 /** Indicates that a pin map exists for smif_spi_select1*/ 284 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 285 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 286 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 287 /** Indicates that a pin map exists for tcpwm_line*/ 288 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 289 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 290 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[12]; 291 /** Indicates that a pin map exists for tcpwm_line_compl*/ 292 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 293 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 294 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[14]; 295 /** Indicates that a pin map exists for tdm_tdm_rx_fsync*/ 296 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_FSYNC (CY_GPIO_DM_STRONG_IN_OFF) 297 /** List of valid pin to peripheral connections for the tdm_tdm_rx_fsync signal. */ 298 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_fsync[1]; 299 /** Indicates that a pin map exists for tdm_tdm_rx_mck*/ 300 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_MCK (CY_GPIO_DM_STRONG_IN_OFF) 301 /** List of valid pin to peripheral connections for the tdm_tdm_rx_mck signal. */ 302 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_mck[1]; 303 /** Indicates that a pin map exists for tdm_tdm_rx_sck*/ 304 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 305 /** List of valid pin to peripheral connections for the tdm_tdm_rx_sck signal. */ 306 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sck[1]; 307 /** Indicates that a pin map exists for tdm_tdm_rx_sd*/ 308 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_SD (CY_GPIO_DM_HIGHZ) 309 /** List of valid pin to peripheral connections for the tdm_tdm_rx_sd signal. */ 310 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sd[1]; 311 /** Indicates that a pin map exists for tdm_tdm_tx_fsync*/ 312 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_FSYNC (CY_GPIO_DM_STRONG_IN_OFF) 313 /** List of valid pin to peripheral connections for the tdm_tdm_tx_fsync signal. */ 314 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_fsync[1]; 315 /** Indicates that a pin map exists for tdm_tdm_tx_mck*/ 316 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_MCK (CY_GPIO_DM_STRONG_IN_OFF) 317 /** List of valid pin to peripheral connections for the tdm_tdm_tx_mck signal. */ 318 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_mck[1]; 319 /** Indicates that a pin map exists for tdm_tdm_tx_sck*/ 320 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 321 /** List of valid pin to peripheral connections for the tdm_tdm_tx_sck signal. */ 322 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sck[1]; 323 /** Indicates that a pin map exists for tdm_tdm_tx_sd*/ 324 #define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_SD (CY_GPIO_DM_STRONG_IN_OFF) 325 /** List of valid pin to peripheral connections for the tdm_tdm_tx_sd signal. */ 326 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sd[1]; 327 328 #if defined(__cplusplus) 329 } 330 #endif /* __cplusplus */ 331 332 /** \} group_hal_impl_pin_package */ 333 334 #endif /* _CYHAL_CYW20829_40_QFN_H_ */ 335 336 337 /* [] END OF FILE */ 338
