1 /***************************************************************************//**
2 * \file cy_ble_clk.c
3 * \version 3.60
4 *
5 * \brief
6 * This driver provides the source code for API BLE ECO clock.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2017-2020 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 #if defined (CY_IP_MXBLESS) && defined (CY_IP_MXS40IOSS)
29
30 #include "cy_syslib.h"
31 #include "cy_gpio.h"
32 #include "cy_syspm.h"
33 #include "cy_ble_clk.h"
34 #include "cy_sysclk.h"
35
36 /* C binding of definitions if building with C++ compiler */
37 #ifdef __cplusplus
38 extern "C" {
39 #endif /* __cplusplus */
40
41 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.4', 1, \
42 'Checked manually. Type cast to uint8_t made intentionally.');
43
44 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.8', 3, \
45 'Checked manually. Type cast to uint8_t made intentionally.');
46
47 /*******************************************************************************
48 * Internal functions
49 *******************************************************************************/
50
51 #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
52 static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegRead(uint16_t addr, uint16_t *data);
53 static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegWrite(uint16_t addr, uint16_t data);
54 static cy_en_ble_eco_status_t Cy_BLE_HAL_EcoSetTrim(uint32_t trim, uint32_t startUpTime);
55 static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t bleEcoFreq,
56 cy_en_ble_eco_sys_clk_div_t sysClkDiv);
57 #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */
58
59
60 /*******************************************************************************
61 * Internal Defines
62 *******************************************************************************/
63
64 /** \cond INTERNAL */
65
66 #define CY_BLE_PORT2_CFG_VAL (0x66666666u)
67 #define CY_BLE_PORT3_CFG_VAL (0x66EEE666u)
68 #define CY_BLE_PORT4_CFG_VAL (0x6666E666u)
69
70 #define CY_BLE_PORT_CFG_OUT_VAL (0xFFFF0000u)
71
72 #define CY_BLE_PORT2_HSIOM_SEL0 (0x1C1C1C1Cu)
73 #define CY_BLE_PORT2_HSIOM_SEL1 (0x1C1C1C1Cu)
74 #define CY_BLE_PORT3_HSIOM_SEL0 (0x1A1A1A1Cu)
75 #define CY_BLE_PORT3_HSIOM_SEL1 (0x00001A1Au)
76 #define CY_BLE_PORT4_HSIOM_SEL0 (0x1C001A1Au)
77 #define CY_BLE_PORT4_HSIOM_SEL1 (0x00000000u)
78
79 #define CY_BLE_GPIO_PRT2 (&((GPIO_Type*)(cy_device->gpioBase))->PRT[2])
80 #define CY_BLE_GPIO_PRT3 (&((GPIO_Type*)(cy_device->gpioBase))->PRT[3])
81 #define CY_BLE_GPIO_PRT4 (&((GPIO_Type*)(cy_device->gpioBase))->PRT[4])
82 #define CY_BLE_GPIO_VDD_ACTIVE (((GPIO_Type*)(cy_device->gpioBase))->VDD_ACTIVE)
83
84 #define CY_BLE_DEFAULT_OSC_STARTUP_DELAY_LF (25u)
85 #define CY_BLE_DEFAULT_CAP_TRIM_VALUE (32u)
86 #define CY_BLE_DEFAULT_ECO_FREQ (CY_BLE_BLESS_ECO_FREQ_32MHZ)
87 #define CY_BLE_DEFAULT_ECO_DIV (CY_BLE_SYS_ECO_CLK_DIV_4)
88
89 #define CY_BLE_DEFAULT_HVLDO_STARTUP_DELAY (6UL)
90 #define CY_BLE_DEFAULT_ISOLATE_DEASSERT_DELAY (0UL)
91 #define CY_BLE_DEFAULT_ACT_TO_SWITCH_DELAY (0UL)
92 #define CY_BLE_DEFAULT_HVLDO_DISABLE_DELAY (1UL)
93 #define CY_BLE_DEFAULT_ACT_STARTUP_DELAY (10UL)
94 #define CY_BLE_DEFAULT_DIG_LDO_STARTUP_DELAY (0UL)
95 #define CY_BLE_DEFAULT_XTAL_DISABLE_DELAY (1UL)
96 #define CY_BLE_DEFAULT_DIG_LDO_DISABLE_DELAY (0UL)
97 #define CY_BLE_DEFAULT_VDDR_STABLE_DELAY (1UL)
98 #define CY_BLE_DEFAULT_RCB_CTRL_LEAD (0x2UL)
99 #define CY_BLE_DEFAULT_RCB_CTRL_LAG (0x2UL)
100 #define CY_BLE_DEFAULT_RCB_CTRL_DIV (0x1UL) /* LL 8 MHz / 2 */
101 #define CY_BLE_DEFAULT_RCB_CTRL_FREQ (4000000UL) /* Default RCB clock is 4 MHz */
102 #define CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ (32000000UL)
103 #define CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ (16000000UL)
104 #define CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL (CY_BLE_PMU_MODE_TRANSITION_REG_CLK_ANA_DIG_EN_BIT | \
105 CY_BLE_PMU_MODE_TRANSITION_REG_RST_ACT_N_BIT)
106 #define CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL (CY_BLE_PMU_PMU_CTRL_REG_CLK_CMOS_SEL_BIT)
107
108 /* Radio registers */
109 #define CY_BLE_RCB_FIFO_WR_BIT_MASK (0x8000UL)
110 #define CY_BLE_RCB_FIFO_WR_BIT_SHIFT (16U)
111
112 #define CY_BLE_PMU_MODE_TRANSITION_REG (0x1e02U)
113 #define CY_BLE_PMU_MODE_TRANSITION_REG_CLK_ANA_DIG_EN_BIT (uint16_t)(1UL << 12U)
114 #define CY_BLE_PMU_MODE_TRANSITION_REG_RST_ACT_N_BIT (uint16_t)(1UL << 11U)
115
116 #define CY_BLE_PMU_PMU_CTRL_REG (0x1e03u)
117 #define CY_BLE_PMU_PMU_CTRL_REG_CLK_CMOS_SEL_BIT (uint16_t)(1UL << 10U)
118
119 #define CY_BLE_RF_DCXO_CFG_REG (0x1e08U)
120 #define CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_SHIFT (1U)
121 #define CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_MASK (0xffUL)
122 #define CY_BLE_RF_DCXO_CFG_REG_VALUE (0x1001U)
123
124 #define CY_BLE_RF_DCXO_CFG2_REG (0x1e0fU)
125 #define CY_BLE_RF_DCXO_CFG2_REG_VALUE (0x6837U)
126
127 #define CY_BLE_RF_DCXO_BUF_CFG_REG (0x1e09U)
128 #define CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT (uint16_t)(1UL << 6U)
129 #define CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT (4U)
130 #define CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_MASK (0x03UL)
131 #define CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT (0U)
132 #define CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_MASK (0x0fUL)
133
134 #define CY_BLE_RF_LDO_CFG_REG (0x1e07u)
135 #define CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_SHIFT (11U)
136 #define CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_MASK (0x03UL)
137 #define CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_SHIFT (7U)
138 #define CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_MASK (0x15UL)
139 #define CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_SHIFT (5U)
140 #define CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_MASK (0x03UL)
141
142 #define CY_BLE_RF_LDO_EN_REG (0x1e06U)
143 #define CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT (6U)
144 #define CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_MASK (0x03UL)
145
146 #define CY_BLE_DELAY_TIME (1U) /* in us */
147 #define CY_BLE_RCB_TIMEOUT (1000U / CY_BLE_DELAY_TIME) /* 1ms */
148 #define CY_BLE_VIO_TIMEOUT (2000U / CY_BLE_DELAY_TIME) /* 2ms */
149 #define CY_BLE_ACT_TIMEOUT (950000U / CY_BLE_DELAY_TIME) /* 950ms */
150 #define CY_BLE_RCB_RETRIES (10U)
151
152
153 /* Range for inputs parameters */
154 #define CY_BLE_ECO_XTAL_START_UP_TIME_MAX ((uint32_t) (4593.75 / 31.25))
155 #define CY_BLE_ECO_XTAL_START_UP_TIME_MIN ((uint32_t) (400 / 31.25))
156
157 #define CY_BLE_ECO_CLOAD_MIN ((uint32_t) ((7.5 - 7.5)/0.075))
158 #define CY_BLE_ECO_CLOAD_MAX ((uint32_t) ((26.325 - 7.5)/0.075))
159
160 #define CY_BLE_ECO_SET_TRIM_DELAY_COEF (32U)
161 #define CY_BLE_ECO_LDO_ENABLE_DELAY (64U)
162 /** \endcond */
163
164
165 /*******************************************************************************
166 * Function Name: Cy_BLE_EcoConfigure
167 ****************************************************************************//**
168 *
169 * This API configures and enables the BLE ECO clock.
170 *
171 * If Cy_BLE_Enable() API is called by the application, the stack enables
172 * the BLE ECO clock automatically with the following default parameters:
173 *
174 * Parameter | Value
175 * -------------------- | -----------
176 * ECO Frequency | CY_BLE_DEFAULT_ECO_FREQ
177 * Divider | CY_BLE_DEFAULT_ECO_DIV
178 * Startup time | CY_BLE_DEFAULT_OSC_STARTUP_DELAY_LF
179 * Load cap | CY_BLE_DEFAULT_CAP_TRIM_VALUE
180 *
181 * If there is a need to start the BLE ECO with non-default parameters, call the
182 * Cy_BLE_EcoConfigure() function with the custom configuration each time before calling
183 * the Cy_BLE_Enable() function.
184 *
185 * This clock is stopped in Deep Sleep and Hibernate power modes.
186 *
187 * \param freq - Operating frequency of the crystal, type of
188 * \ref cy_en_ble_eco_freq_t.
189 *
190 * \param sysClkDiv - System divider for ECO clock, type of
191 * \ref cy_en_ble_eco_sys_clk_div_t.
192 *
193 * \param cLoad - ECO crystal load capacitance in multiple of 0.075pF
194 * (pF_from_user valid range: 7.5...26.625pF)
195 * cLoad = ((pF_from_user - 7.5)/0.075)
196 *
197 * \param xtalStartUpTime - ECO crystal startup time in multiple of 31.25us
198 * (startup_time_from_user valid range: 400...4593.75us)
199 * xtalStartUpTime = startup_time_from_user/31.25
200 *
201 * \param voltageReg - BLE Voltage regulator, type of
202 * \ref cy_en_ble_eco_voltage_reg_t.
203 *
204 * \return
205 * \ref cy_en_ble_eco_status_t : The return value indicates if the function
206 * succeeded or failed. The possible error codes:
207 *
208 * Error Codes | Description
209 * -------------------- | -----------
210 * CY_BLE_ECO_SUCCESS | The function completed successfully.
211 * CY_BLE_ECO_BAD_PARAM | The wrong input parameter.
212 * CY_BLE_ECO_RCB_CONTROL_LL | The RCB Control is with BLE Link Layer.
213 * CY_BLE_ECO_ALREADY_STARTED | The BLE ECO clock is already started.
214 * CY_BLE_ECO_HARDWARE_ERROR | The RCB or BLE ECO operation failed.
215 *
216 * For the PSoC 64 devices, there are possible situations when the function returns
217 * the PRA error status code. This is because for PSoC 64 devices, the function
218 * uses the PRA driver to change the frequency value on the protected side.
219 * Refer to \ref cy_en_pra_status_t for more details.
220 *
221 * \funcusage
222 * \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure()
223 *
224 * \sideeffect
225 * The I/O pins will be automatically unfrozen coming out of Hibernate when
226 * the BLE ECO is in use.
227 *
228 * \note Limitation: Do not call this API if the BLE is executed with LPM.
229 * There is a risk that when the Cy_BLE_EcoConfigure() function is called on
230 * one core, the BLE is in Deep Sleep mode on the other core. It will cause
231 * a fault hard exception.
232 *
233 *******************************************************************************/
Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq,cy_en_ble_eco_sys_clk_div_t sysClkDiv,uint32_t cLoad,uint32_t xtalStartUpTime,cy_en_ble_eco_voltage_reg_t voltageReg)234 cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_eco_sys_clk_div_t sysClkDiv,
235 uint32_t cLoad, uint32_t xtalStartUpTime, cy_en_ble_eco_voltage_reg_t voltageReg)
236 {
237 cy_en_ble_eco_status_t status = CY_BLE_ECO_SUCCESS;
238
239 #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
240 cy_stc_pra_ble_eco_config_t ecoConfigParams;
241 ecoConfigParams.freq = freq;
242 ecoConfigParams.sysClkDiv = sysClkDiv;
243 ecoConfigParams.cLoad = cLoad;
244 ecoConfigParams.xtalStartUpTime = xtalStartUpTime;
245 ecoConfigParams.voltageReg = voltageReg;
246
247 status = (cy_en_ble_eco_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SECURE_ONLY,
248 CY_PRA_BLE_CLK_FUNC_ECO_CONFIGURE,
249 &ecoConfigParams);
250 #else
251 uint32_t temp = 0UL;
252
253 if( (freq > CY_BLE_BLESS_ECO_FREQ_32MHZ) || (sysClkDiv > CY_BLE_SYS_ECO_CLK_DIV_8) ||
254 (xtalStartUpTime > CY_BLE_ECO_XTAL_START_UP_TIME_MAX) || (xtalStartUpTime < CY_BLE_ECO_XTAL_START_UP_TIME_MIN) ||
255 (cLoad > CY_BLE_ECO_CLOAD_MAX))
256 {
257 status = CY_BLE_ECO_BAD_PARAM;
258 }
259 else
260 {
261 /* Unfreeze IO after Hibernate */
262 if(Cy_SysPm_GetIoFreezeStatus())
263 {
264 Cy_SysPm_IoUnfreeze();
265 }
266
267 if(Cy_BLE_EcoIsEnabled())
268 {
269 status = CY_BLE_ECO_ALREADY_STARTED;
270 }
271 else
272 {
273 /* HAL Initialization */
274 Cy_BLE_HAL_Init();
275
276 /* BLESS MT Delays configuration */
277 BLE_BLESS_MT_DELAY_CFG =
278 (uint32_t)(CY_BLE_DEFAULT_HVLDO_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Pos) |
279 (uint32_t)(CY_BLE_DEFAULT_ISOLATE_DEASSERT_DELAY << BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Pos) |
280 (uint32_t)(CY_BLE_DEFAULT_ACT_TO_SWITCH_DELAY << BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Pos) |
281 (uint32_t)(CY_BLE_DEFAULT_HVLDO_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Pos);
282
283 BLE_BLESS_MT_DELAY_CFG2 =
284 (uint32_t)(xtalStartUpTime << BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Pos) |
285 (uint32_t)(CY_BLE_DEFAULT_ACT_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Pos) |
286 (uint32_t)(CY_BLE_DEFAULT_DIG_LDO_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Pos);
287
288 BLE_BLESS_MT_DELAY_CFG3 =
289 (uint32_t)(CY_BLE_DEFAULT_XTAL_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Pos) |
290 (uint32_t)(CY_BLE_DEFAULT_DIG_LDO_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Pos) |
291 (uint32_t)(CY_BLE_DEFAULT_VDDR_STABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Pos);
292
293 /* RCB Initialization
294 * Check if the RCB Control is with LL.
295 */
296 if((BLE_RCB_RCBLL_CTRL & BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Msk) != 0U)
297 {
298 status = CY_BLE_ECO_RCB_CONTROL_LL;
299 }
300 else
301 {
302 uint32_t rcbDivider = 0UL;
303
304 /* If clock source for RCB is PeriClk */
305 if((BLE_BLESS_LL_CLK_EN & BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Msk) == 0U)
306 {
307 uint32_t periClkFreqHz = Cy_SysClk_ClkPeriGetFrequency();
308
309 if(periClkFreqHz > CY_BLE_DEFAULT_RCB_CTRL_FREQ)
310 {
311 rcbDivider = (periClkFreqHz / CY_BLE_DEFAULT_RCB_CTRL_FREQ) - 1U;
312 }
313 }
314 else
315 {
316 rcbDivider = CY_BLE_DEFAULT_RCB_CTRL_DIV;
317 }
318
319 /* Configure default RCB Parameters. */
320 BLE_RCB_CTRL |= (BLE_RCB_CTRL_ENABLED_Msk |
321 BLE_RCB_CTRL_RX_CLK_EDGE_Msk |
322 (CY_BLE_DEFAULT_RCB_CTRL_LEAD << BLE_RCB_CTRL_LEAD_Pos) |
323 (CY_BLE_DEFAULT_RCB_CTRL_LAG << BLE_RCB_CTRL_LAG_Pos) |
324 ((rcbDivider > 0U) ? ((rcbDivider << BLE_RCB_CTRL_DIV_Pos) |
325 BLE_RCB_CTRL_DIV_ENABLED_Msk) : 0U));
326
327 /* If user uses SIMO Buck, enable Buck2 in hardware mode for BLE */
328 if((Cy_SysPm_SimoBuckIsEnabled()) && (voltageReg == CY_BLE_ECO_VOLTAGE_REG_AUTO))
329 {
330 Cy_SysPm_BuckSetVoltage2(CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V, true);
331 Cy_SysPm_BuckSetVoltage2HwControl(true);
332 }
333 else /* Configure BLE LDO if SIMO Buck2 is not enabled */
334 {
335 BLE_BLESS_MISC_EN_CTRL |= (BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Msk |
336 BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Msk);
337 }
338
339 /* Enable the VIO supply and LDO in standby mode for slow ramp */
340 temp = BLE_BLESS_MT_CFG;
341 temp |= BLE_BLESS_MT_CFG_HVLDO_BYPASS_Msk |
342 BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk |
343 BLE_BLESS_MT_CFG_HVLDO_EN_Msk |
344 BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk;
345 BLE_BLESS_MT_CFG = temp;
346 Cy_SysLib_DelayUs(CY_BLE_ECO_LDO_ENABLE_DELAY);
347
348 if((BLE_BLESS_MT_VIO_CTRL & BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk) == 0U)
349 {
350 /* Enable LDO */
351 BLE_BLESS_MT_VIO_CTRL = BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk;
352
353 /* Wait for 64us after turning HVLDO ON */
354 Cy_SysLib_DelayUs(CY_BLE_ECO_LDO_ENABLE_DELAY);
355
356 /* Enable LDO Delayed */
357 BLE_BLESS_MT_VIO_CTRL = BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk |
358 BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Msk;
359 /* Wait for 64us */
360 Cy_SysLib_DelayUs(CY_BLE_ECO_LDO_ENABLE_DELAY);
361 }
362
363 /* Disable override mode and let hardware take control of HVLDO */
364 temp &= ~(BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk |
365 BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk);
366 BLE_BLESS_MT_CFG = temp;
367
368 /* Wait for the VIO stable key write operation to complete */
369 {
370 uint32_t timeout = CY_BLE_VIO_TIMEOUT;
371 while(((CY_BLE_GPIO_VDD_ACTIVE & 0x10U) == 0U) && (timeout > 0U))
372 {
373 timeout--;
374 Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
375 }
376 if(timeout == 0U)
377 {
378 status = CY_BLE_ECO_HARDWARE_ERROR;
379 }
380 }
381
382
383 if(status == CY_BLE_ECO_SUCCESS)
384 {
385 uint32_t timeout = CY_BLE_ACT_TIMEOUT;
386
387 /* Clear the BLERD_ACTIVE_INTR */
388 BLE_BLESS_INTR_STAT |= BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Msk;
389
390 if((!Cy_SysPm_SimoBuckOutputIsEnabled(CY_SYSPM_BUCK_VRF)) || (voltageReg == CY_BLE_ECO_VOLTAGE_REG_BLESSLDO))
391 {
392 temp |= BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk;
393 }
394 /* Enable Radio */
395 temp |= BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk;
396
397 /* Disable ECO in DeepSleep mode */
398 temp &= ~BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Msk;
399 BLE_BLESS_MT_CFG = temp;
400
401 /* Wait for BLESS in ACTIVE state */
402 while(((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) == 0U) && (timeout > 0U))
403 {
404 timeout--;
405 Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
406 }
407 if(timeout == 0U)
408 {
409 status = CY_BLE_ECO_HARDWARE_ERROR;
410 }
411 }
412
413 if(status == CY_BLE_ECO_SUCCESS)
414 {
415 /* Enable and configure radio clock */
416 status = Cy_BLE_HAL_MxdRadioEnableClocks(freq, sysClkDiv);
417 }
418
419 if(status == CY_BLE_ECO_SUCCESS)
420 {
421 /* Set Load capacitance */
422 status = Cy_BLE_HAL_EcoSetTrim(cLoad, xtalStartUpTime);
423 }
424 }
425 }
426 }
427 #endif /* ((CY_CPU_CORTEX_M4) && (!defined(CY_DEVICE_SECURE))) */
428
429 return(status);
430 }
431
432
433 /*******************************************************************************
434 * Function Name: Cy_BLE_EcoReset
435 ****************************************************************************//**
436 *
437 * This API resets and disables the BLE ECO clock.
438 *
439 * \return
440 * None
441 *
442 *******************************************************************************/
Cy_BLE_EcoReset(void)443 void Cy_BLE_EcoReset(void)
444 {
445 /* Initiate Soft Reset */
446 #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
447 CY_PRA_FUNCTION_CALL_VOID_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, CY_PRA_BLE_CLK_FUNC_ECO_RESET);
448 #else
449 BLE_BLESS_LL_CLK_EN |= BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk;
450 cy_BleEcoClockFreqHz = 0UL; /* Reset the BLE ECO frequency */
451 #endif
452 }
453
454
455 /*******************************************************************************
456 * Function Name: Cy_BLE_EcoStart
457 ****************************************************************************//**
458 *
459 * This API configure and enables the BLE ECO clock.
460 *
461 * This API is used as the PSoC Creator wrapper function. This function is not
462 * recommended for new designs. Please use Cy_BLE_EcoConfigure()
463 * instead of this function.
464 *
465 * \param config
466 * The pointer to the configuration structure cy_stc_ble_eco_config_t.
467 *
468 * \return
469 * \ref cy_en_ble_eco_status_t : The return value indicates if the function
470 * succeeded or failed. The possible error codes:
471 *
472 * Error Codes | Description
473 * -------------------- | -----------
474 * CY_BLE_ECO_SUCCESS | The function completed successfully.
475 * CY_BLE_ECO_BAD_PARAM | The wrong input parameter.
476 * CY_BLE_ECO_RCB_CONTROL_LL | The RCB Control is with BLE Link Layer.
477 * CY_BLE_ECO_ALREADY_STARTED | The BLE ECO clock is already started.
478 * CY_BLE_ECO_HARDWARE_ERROR | The RCB or BLE ECO operation failed.
479 *
480 * \sideeffect
481 * The I/O pins will be automatically unfrozen coming out of Hibernate when
482 * the BLE ECO is in use.
483 *
484 * \note Limitation: Do not call this API if the BLE is executed with LPM.
485 * There is a risk that when the Cy_BLE_EcoStart() function is called on one
486 * core, the BLE is in Deep Sleep mode on the other core. It will cause
487 * a fault hard exception.
488 *
489 *******************************************************************************/
Cy_BLE_EcoStart(const cy_stc_ble_eco_config_t * config)490 cy_en_ble_eco_status_t Cy_BLE_EcoStart(const cy_stc_ble_eco_config_t *config)
491 {
492 cy_en_ble_eco_status_t retValue = CY_BLE_ECO_BAD_PARAM;
493 if(config != NULL)
494 {
495 /* Configure BLE ECO clock */
496 retValue = Cy_BLE_EcoConfigure(config->ecoFreq, config->ecoSysDiv, (uint32_t) config->loadCap,
497 (uint32_t) config->ecoXtalStartUpTime, CY_BLE_ECO_VOLTAGE_REG_AUTO);
498 }
499 return (retValue);
500 }
501
502
503 /*******************************************************************************
504 * Function Name: Cy_BLE_EcoStop
505 ****************************************************************************//**
506 *
507 * This API stops BLE ECO clock.
508 *
509 * This API is used as the PSoC Creator wrapper function. This function is not
510 * recommended for new designs. Please use Cy_BLE_EcoReset() instead of this
511 * function.
512 *
513 * \return
514 * None
515 *
516 *******************************************************************************/
Cy_BLE_EcoStop(void)517 void Cy_BLE_EcoStop(void)
518 {
519 Cy_BLE_EcoReset();
520 }
521
522
523 /*******************************************************************************
524 * Function Name: Cy_BLE_HAL_Init
525 ****************************************************************************//**
526 *
527 * Initializes the BLESS port.
528 *
529 * \return
530 * None
531 *
532 *******************************************************************************/
Cy_BLE_HAL_Init(void)533 void Cy_BLE_HAL_Init(void)
534 {
535 /* Configures pins for BLESS */
536 const cy_stc_gpio_prt_config_t port2_cfg =
537 {
538 0UL, /* out */
539 0UL, /* ntrMask */
540 0UL, /* intrCfg */
541 CY_BLE_PORT2_CFG_VAL, /* cfg */
542 0UL, /* cfgIn */
543 CY_BLE_PORT_CFG_OUT_VAL, /* cfgOut */
544 0UL, /* cfgSIO */
545 CY_BLE_PORT2_HSIOM_SEL0, /* sel0Active */
546 CY_BLE_PORT2_HSIOM_SEL1 /* sel1Active */
547 };
548
549 const cy_stc_gpio_prt_config_t port3_cfg =
550 {
551 0UL, /* out */
552 0UL, /* ntrMask */
553 0UL, /* intrCfg */
554 CY_BLE_PORT3_CFG_VAL, /* cfg */
555 0UL, /* cfgIn */
556 CY_BLE_PORT_CFG_OUT_VAL, /* cfgOut */
557 0UL, /* cfgSIO */
558 CY_BLE_PORT3_HSIOM_SEL0, /* sel0Active */
559 CY_BLE_PORT3_HSIOM_SEL1 /* sel1Active */
560 };
561
562 const cy_stc_gpio_prt_config_t port4_cfg =
563 {
564 0UL, /* out */
565 0UL, /* ntrMask */
566 0UL, /* intrCfg */
567 CY_BLE_PORT4_CFG_VAL, /* cfg */
568 0UL, /* cfgIn */
569 CY_BLE_PORT_CFG_OUT_VAL, /* cfgOut */
570 0UL, /* cfgSIO */
571 CY_BLE_PORT4_HSIOM_SEL0, /* sel0Active */
572 CY_BLE_PORT4_HSIOM_SEL1 /* sel1Active */
573 };
574
575 (void)Cy_GPIO_Port_Init(CY_BLE_GPIO_PRT2, &port2_cfg);
576 (void)Cy_GPIO_Port_Init(CY_BLE_GPIO_PRT3, &port3_cfg);
577 (void)Cy_GPIO_Port_Init(CY_BLE_GPIO_PRT4, &port4_cfg);
578
579 }
580
581
582 #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
583 /*******************************************************************************
584 * Function Name: Cy_BLE_HAL_RcbRegRead
585 ****************************************************************************//**
586 *
587 * Reads Radio register.
588 *
589 * \param addr : Register address.
590 * \param *data: Register data (output parameter).
591 *
592 * \return
593 * \ref cy_en_ble_eco_status_t : Return value indicates if the function succeeded or
594 * failed. The following are possible error codes:
595 *
596 * Error Codes | Description
597 * -------------------- | -----------
598 * CY_BLE_ECO_SUCCESS | On successful operation.
599 * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed
600 *
601 *******************************************************************************/
Cy_BLE_HAL_RcbRegRead(uint16_t addr,uint16_t * data)602 static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegRead(uint16_t addr, uint16_t *data)
603 {
604 cy_en_ble_eco_status_t status = CY_BLE_ECO_HARDWARE_ERROR;
605 uint32_t timeout = CY_BLE_RCB_TIMEOUT;
606 uint32_t temp = (uint32_t)((CY_BLE_RCB_FIFO_WR_BIT_MASK | addr) << CY_BLE_RCB_FIFO_WR_BIT_SHIFT);
607
608 /* Write Address to the RCB */
609 BLE_RCB_TX_FIFO_WR = temp;
610
611 /* Wait for Data. */
612 while(((BLE_RCB_INTR & BLE_RCB_INTR_RCB_DONE_Msk) == 0U) && (timeout > 0U))
613 {
614 timeout--;
615 Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
616 }
617
618 if(timeout > 0U)
619 {
620 BLE_RCB_INTR |= BLE_RCB_INTR_RCB_DONE_Msk;
621 *data = (uint16_t)BLE_RCB_RX_FIFO_RD;
622 status = CY_BLE_ECO_SUCCESS;
623 }
624
625 return(status);
626 }
627
628
629 /*******************************************************************************
630 * Function Name: Cy_BLE_HAL_RcbRegWrite
631 ****************************************************************************//**
632 *
633 * Writes Radio register.
634 *
635 * \param addr: Register address.
636 * \param data: Register data.
637 *
638 * \return
639 * \ref cy_en_ble_eco_status_t : Return value indicates if the function succeeded or
640 * failed. The following are possible error codes:
641 *
642 * Error Codes | Description
643 * -------------------- | -----------
644 * CY_BLE_ECO_SUCCESS | On successful operation.
645 * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed
646 *
647 *******************************************************************************/
Cy_BLE_HAL_RcbRegWrite(uint16_t addr,uint16_t data)648 static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegWrite(uint16_t addr, uint16_t data)
649 {
650 cy_en_ble_eco_status_t status = CY_BLE_ECO_HARDWARE_ERROR;
651 uint32_t timeout = CY_BLE_RCB_TIMEOUT;
652 uint32_t temp = ((uint32_t)((~CY_BLE_RCB_FIFO_WR_BIT_MASK & addr) << CY_BLE_RCB_FIFO_WR_BIT_SHIFT)) | data;
653
654 BLE_RCB_TX_FIFO_WR = temp;
655
656 /* Wait for RCB done. */
657 while(((BLE_RCB_INTR & BLE_RCB_INTR_RCB_DONE_Msk) == 0U) && (timeout > 0U))
658 {
659 timeout--;
660 Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
661 }
662
663 if(timeout > 0U)
664 {
665 BLE_RCB_INTR |= BLE_RCB_INTR_RCB_DONE_Msk;
666 status = CY_BLE_ECO_SUCCESS;
667 }
668
669 return(status);
670 }
671
672
673 /*******************************************************************************
674 * Function Name: Cy_BLE_HAL_EcoSetTrim
675 ****************************************************************************//**
676 *
677 * Sets ECO trim value.
678 *
679 * \param trim : Trim value.
680 * \param startUpTime : Start up time delay.
681 *
682 * \return
683 * \ref cy_en_ble_eco_status_t : Return value indicates if the function succeeded or
684 * failed. The following are possible error codes:
685 *
686 * Error Codes | Description
687 * -------------------- | -----------
688 * CY_BLE_ECO_SUCCESS | On successful operation.
689 * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed
690 *
691 *******************************************************************************/
Cy_BLE_HAL_EcoSetTrim(uint32_t trim,uint32_t startUpTime)692 static cy_en_ble_eco_status_t Cy_BLE_HAL_EcoSetTrim(uint32_t trim, uint32_t startUpTime)
693 {
694 uint16_t reg = CY_BLE_RF_DCXO_CFG_REG_VALUE;
695 cy_en_ble_eco_status_t status;
696
697 /* Load the new CAP TRIM value */
698 reg |= (uint16_t)((uint16_t)trim << CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_SHIFT);
699
700 /* Write the new value to the register */
701 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_CFG_REG, reg);
702
703 if(status == CY_BLE_ECO_SUCCESS)
704 {
705 /* Write the new value to the CFG2 register */
706 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_CFG2_REG, CY_BLE_RF_DCXO_CFG2_REG_VALUE);
707 }
708
709 Cy_SysLib_DelayUs((uint16_t)startUpTime * CY_BLE_ECO_SET_TRIM_DELAY_COEF);
710
711 return(status);
712 }
713
714
715 /*******************************************************************************
716 * Function Name: Cy_BLE_HAL_MxdRadioEnableClocks
717 ****************************************************************************//**
718 *
719 * Enables and configures radio clock.
720 *
721 * \param bleEcoFreq : ECO Frequency.
722 * \param sysClkDiv : System divider for ECO clock.
723 *
724 * \return
725 * \ref cy_en_ble_eco_status_t : Return value indicates if the function succeeded or
726 * failed. The following are possible error codes:
727 *
728 * Error Codes | Description
729 * -------------------- | -----------
730 * CY_BLE_ECO_SUCCESS | On successful operation.
731 * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed
732 *
733 *******************************************************************************/
Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t bleEcoFreq,cy_en_ble_eco_sys_clk_div_t sysClkDiv)734 static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t bleEcoFreq,
735 cy_en_ble_eco_sys_clk_div_t sysClkDiv)
736 {
737 uint16_t temp;
738 uint32_t retries = CY_BLE_RCB_RETRIES;
739 cy_en_ble_eco_status_t status;
740
741 /* De-assert active domain reset and enable clock buffer in MXD Radio */
742 do
743 {
744 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_PMU_MODE_TRANSITION_REG, CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL);
745 if(status == CY_BLE_ECO_SUCCESS)
746 {
747 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_MODE_TRANSITION_REG, &temp);
748 }
749 if(retries > 0U)
750 {
751 retries--;
752 }
753 else
754 {
755 status = CY_BLE_ECO_HARDWARE_ERROR;
756 }
757 }
758 while((status == CY_BLE_ECO_SUCCESS) && (temp != CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL));
759
760 /* Check if ECO clock output is enabled
761 * In MXD_VER2, ECO clock is stopped on overwriting this bit */
762 if(status == CY_BLE_ECO_SUCCESS)
763 {
764 retries = CY_BLE_RCB_RETRIES;
765 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp);
766 if((status == CY_BLE_ECO_SUCCESS) && ((temp & CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL) == 0U))
767 {
768 /* Enable digital ECO clock output from MXD Radio to BLESS */
769 do
770 {
771 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_PMU_PMU_CTRL_REG, CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL);
772 if(status == CY_BLE_ECO_SUCCESS)
773 {
774 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp);
775 }
776 if(retries > 0U)
777 {
778 retries--;
779 }
780 else
781 {
782 status = CY_BLE_ECO_HARDWARE_ERROR;
783 }
784 }
785 while((status == CY_BLE_ECO_SUCCESS) && (temp != CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL));
786 }
787 }
788
789 /* Configure ECO clock frequency and clock divider in MXD Radio */
790 if(status == CY_BLE_ECO_SUCCESS)
791 {
792 /* Read the MXD Radio register */
793 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_RF_DCXO_BUF_CFG_REG, &temp);
794 }
795 if(status == CY_BLE_ECO_SUCCESS)
796 {
797 uint16_t blerdDivider;
798 uint16_t ecoSysDivider;
799 uint16_t blellDivider = 0U;
800
801 /* Clear clock divider and select amp buffer output bits */
802 temp &= CY_LO16(~((CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_MASK << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT) |
803 (CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_MASK << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT)));
804
805 /* Total ECO divider consist of divider located on BLERD and BLESS divider
806 * Set BLERD divider to maximum value taking in to account that 8 MHz is required for BLELL.
807 * BLELL clock frequency is set to 8 MHz irrespective of the crystal value.
808 */
809 if(bleEcoFreq == CY_BLE_BLESS_ECO_FREQ_32MHZ)
810 {
811 if(sysClkDiv >= CY_BLE_SYS_ECO_CLK_DIV_4)
812 {
813 blerdDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_4;
814 }
815 else
816 {
817 blerdDivider = (uint16_t)sysClkDiv;
818 blellDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_4 - blerdDivider;
819 }
820 temp |= CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT;
821 temp |= ((uint16_t)CY_BLE_MXD_RADIO_CLK_BUF_AMP_32M_LARGE << (uint16_t)CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT);
822
823 /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */
824 cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ / (1UL << (uint16_t)sysClkDiv);
825 }
826 else
827 {
828 if(sysClkDiv >= CY_BLE_SYS_ECO_CLK_DIV_2)
829 {
830 blerdDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_2;
831 }
832 else
833 {
834 blerdDivider = (uint16_t)sysClkDiv;
835 blellDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_2 - blerdDivider;
836 }
837 temp &= (uint16_t) ~CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT;
838 temp |= (uint16_t)((uint32_t)CY_BLE_MXD_RADIO_CLK_BUF_AMP_16M_LARGE << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT);
839
840 /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */
841 cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ / (1UL << (uint16_t)sysClkDiv);
842 }
843
844 temp |= (uint16_t)(blerdDivider << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT);
845
846 /* Write the MXD Radio register */
847 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_BUF_CFG_REG, temp);
848
849 /* Reduce BLESS divider by BLERD divider value */
850 ecoSysDivider = (uint16_t)sysClkDiv - blerdDivider;
851 temp = (uint16_t)(ecoSysDivider & BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Msk);
852 temp |= (uint16_t)(blellDivider << BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Pos);
853
854 /* Set clock divider */
855 BLE_BLESS_XTAL_CLK_DIV_CONFIG = temp;
856 }
857
858 /* Update RADIO LDO trim values */
859 if((Cy_SysLib_GetDeviceRevision() != CY_SYSLIB_DEVICE_REV_0A) && (SFLASH->RADIO_LDO_TRIMS != 0U))
860 {
861 if(status == CY_BLE_ECO_SUCCESS)
862 {
863 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_RF_LDO_CFG_REG, &temp);
864 }
865
866 if(status == CY_BLE_ECO_SUCCESS)
867 {
868 /* Update LDO_IF value */
869 temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_SHIFT));
870 temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_IF_Msk) >>
871 SFLASH_RADIO_LDO_TRIMS_LDO_IF_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_SHIFT);
872
873 /* Update LDO_ACT value */
874 temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_SHIFT));
875 temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Msk) >>
876 SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_SHIFT);
877
878 /* Update LDO_DIG value */
879 temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_SHIFT));
880 temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Msk) >>
881 SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_SHIFT);
882
883 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_LDO_CFG_REG, temp);
884 }
885
886 if(status == CY_BLE_ECO_SUCCESS)
887 {
888 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_RF_LDO_EN_REG, &temp);
889 }
890
891 if(status == CY_BLE_ECO_SUCCESS)
892 {
893 /* Update LDO_LNA value */
894 temp &= (uint16_t)~(CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_MASK << CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT);
895 temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Msk) >>
896 SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos) << CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT);
897
898 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_LDO_EN_REG, temp);
899 }
900 }
901 return(status);
902 }
903 #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */
904
905 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.8');
906
907 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.4');
908
909 #ifdef __cplusplus
910 }
911 #endif /* __cplusplus */
912 #endif /* defined(CY_IP_MXBLESS) */
913
914
915 /* [] END OF FILE */
916
