1
2 /**
3 * @file xmc_hrpwm.c
4 * @date 2015-07-14
5 *
6 * @cond
7 **********************************************************************************
8 * XMClib v2.1.24 - XMC Peripheral Driver Library
9 *
10 * Copyright (c) 2015-2019, Infineon Technologies AG
11 * All rights reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification,are permitted provided that the following conditions are met:
15 *
16 * Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright notice,
20 * this list of conditions and the following disclaimer in the documentation
21 * and/or other materials provided with the distribution.
22 *
23 * Neither the name of the copyright holders nor the names of its contributors
24 * may be used to endorse or promote products derived from this software without
25 * specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
31 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 *
39 * To improve the quality of the software, users are encouraged to share
40 * modifications, enhancements or bug fixes with Infineon Technologies AG
41 * dave@infineon.com).
42 **********************************************************************************
43 *
44 * Change History
45 * --------------
46 *
47 * 2015-02-18:
48 * - Variable g_hrpwm_char_data[] defined in startup file is used in place of trim data macro<br>
49 *
50 * 2015-05-12:
51 * - XMC_HRPWM_CSG_SelClampingInput() api is added to select the clamping input.<br>
52 * - In XMC_HRPWM_Init() api macros used to check 'ccu_clock' frequency are renamed for readability<br>
53 * - 80MHz HRC operation would need a minimum of 70 Mhz CCU clock.<br>
54 *
55 * 2015-06-20:
56 * - Removed version macros and declaration of GetDriverVersion API <br>
57 * - Updated copyright and change history section.<br>
58 *
59 * 2015-07-06:
60 * - CSG trimming data assignment is corrected.<br>
61 *
62 * 2015-07-14:
63 * - Redundant code removed in XMC_HRPWM_HRC_ConfigSourceSelect0() and XMC_HRPWM_HRC_ConfigSourceSelect1() API's.<br>
64 * - Enums and masks are type casted to uint32_t type.
65 *
66 * @endcond
67 *
68 */
69
70 /**
71 *
72 * @brief HRPWM low level driver API prototype definition for XMC family of microcontrollers <br>
73 *
74 * <b>Detailed description of file</b> <br>
75 * APIs provided in this file cover the following functional blocks of HRPWM: <br>
76 * -- High Resolution Channel (APIs prefixed with XMC_HRPWM_HRC_) <br>
77 * -- Comparator and Slope Generator (APIs prefixed with XMC_HRPWM_CSG_) <br>
78 *
79 */
80
81 /***********************************************************************************************************************
82 * HEADER FILES
83 **********************************************************************************************************************/
84 #include <xmc_hrpwm.h>
85
86 #if defined(HRPWM0)
87 #include <xmc_scu.h>
88
89 /***********************************************************************************************************************
90 * MACROS
91 **********************************************************************************************************************/
92 /* 70MHz is considered as the minimum range for 80MHz HRC operation */
93 #define XMC_HRPWM_70MHZ_FREQUENCY 70000000U
94
95 /* 100MHz is considered as the maximum range for 80MHz HRC operation */
96 #define XMC_HRPWM_100MHZ_FREQUENCY 100000000U
97
98 /* 150MHz is considered as the maximum range for 120MHz HRC operation */
99 #define XMC_HRPWM_150MHZ_FREQUENCY 150000000U
100
101 /* 200MHz is considered as the maximum range for 180MHz HRC operation */
102 #define XMC_HRPWM_200MHZ_FREQUENCY 200000000U
103
104 #if (UC_SERIES == XMC44)
105 #define XMC_HRPWM_DELAY_CNT (28800U) /* Provides ~2.8 msec delay @ 220MHz frequency */
106
107 #elif (UC_SERIES == XMC42)
108 #define XMC_HRPWM_DELAY_CNT (19200U) /* Provides ~2.8 msec delay @ 150MHz frequency */
109
110 #else
111 #define XMC_HRPWM_DELAY_CNT (36000U) /* Provides ~5.3 msec delay @ 150MHz frequency */
112 #endif
113
114 /*********************************************************************************************************************
115 * LOCAL ROUTINES
116 ********************************************************************************************************************/
117 static void XMC_HRPWM_lDelay(void);
118
119 /***********************************************************************************************************************
120 * API IMPLEMENTATION - GENERAL
121 **********************************************************************************************************************/
122
123 /* Delay */
XMC_HRPWM_lDelay(void)124 void XMC_HRPWM_lDelay(void)
125 {
126 volatile uint32_t i;
127
128 for (i = 0U; i <= XMC_HRPWM_DELAY_CNT; i++) /* Wait more than 2 microseconds */
129 {
130 __NOP();
131 }
132 }
133
134 /***********************************************************************************************************************
135 * API IMPLEMENTATION - HRPWM GLOBAL
136 **********************************************************************************************************************/
137 /* Initializes HRPWM global registers */
XMC_HRPWM_Init(XMC_HRPWM_t * const hrpwm)138 XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm)
139 {
140 uint32_t *csg_memory;
141 uint32_t ccu_clock;
142 uint32_t clkc;
143 XMC_HRPWM_STATUS_t status;
144
145 XMC_ASSERT("XMC_HRPWM_Init:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
146
147 status = XMC_HRPWM_STATUS_ERROR;
148
149 /* Apply reset to HRPWM module */
150 XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0);
151
152 /* Release reset for HRPWM module */
153 XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0);
154
155 /* Ungate clock */
156 XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_HRPWM0);
157
158 hrpwm->GLBANA = (uint32_t)0x00004A4E; /* Initialization sequence */
159
160 hrpwm->HRBSC |= (uint32_t)HRPWM0_HRBSC_HRBE_Msk; /* Enable Bias Generator of HRPWM */
161
162 /* Update CSG0 memory data */
163 csg_memory = (uint32_t *)XMC_HRPWM_CSG0_MEMORY_ADDRESS;
164 *csg_memory = g_hrpwm_char_data[0];
165 /* write csg memory bits[14:11] with 0b1100 */
166 *csg_memory &= (uint32_t)(0xFFFF87FF);
167 *csg_memory |= (uint32_t)(0x00006000);
168
169 /* Update CSG1 trimming data */
170 csg_memory = (uint32_t *)XMC_HRPWM_CSG1_MEMORY_ADDRESS;
171 *csg_memory = g_hrpwm_char_data[1];
172 /* write csg memory bits[14:11] with 0b1100 */
173 *csg_memory &= (uint32_t)(0xFFFF87FF);
174 *csg_memory |= (uint32_t)(0x00006000);
175
176 /* Update CSG2 trimming data */
177 csg_memory = (uint32_t *)XMC_HRPWM_CSG2_MEMORY_ADDRESS;
178 *csg_memory = g_hrpwm_char_data[2];
179 /* write csg memory bits[14:11] with 0b1100 */
180 *csg_memory &= (uint32_t)(0xFFFF87FF);
181 *csg_memory |= (uint32_t)(0x00006000);
182
183 /* Set CSG units to high speed mode */
184 hrpwm->CSGCFG = (uint32_t)(0x0000003F);
185
186 /* Read CCU clock frequency */
187 ccu_clock = XMC_SCU_CLOCK_GetCcuClockFrequency();
188
189 if ((ccu_clock > XMC_HRPWM_70MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_100MHZ_FREQUENCY))
190 {
191 clkc = 3U; /* Clock frequency range 70MHz+ - 100MHz is considered as 80MHz HRC operation */
192 }
193 else if ((ccu_clock > XMC_HRPWM_100MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_150MHZ_FREQUENCY))
194 {
195 clkc = 2U; /* Clock frequency range 100MHz+ - 150MHz is considered as 120MHz HRC operation */
196 }
197 else if ((ccu_clock > XMC_HRPWM_150MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_200MHZ_FREQUENCY))
198 {
199 clkc = 1U; /* Clock frequency range 150MHz+ - 200MHz is considered as 180MHz HRC operation */
200 }
201 else
202 {
203 clkc = 0U; /* Invalid frequency for HRC operation: Clock frequency <= 60MHz & Clock frequency > 200MHz */
204 }
205
206 if (clkc != 0U) /* Enter the loop only if the clock frequency is valid */
207 {
208 /* Program HRC clock configuration with clock frequency information */
209 hrpwm->HRCCFG |= (clkc << HRPWM0_HRCCFG_CLKC_Pos);
210
211 hrpwm->HRCCFG |= (uint32_t)HRPWM0_HRCCFG_HRCPM_Msk; /* Release HR generation from power down mode */
212
213 XMC_HRPWM_lDelay(); /* As per Initialization sequence */
214
215 /* Enable global high resolution generation / Force charge pump down */
216 hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk;
217
218 XMC_HRPWM_lDelay();
219
220 /* Check High resolution ready bit field */
221 if ((hrpwm->HRGHRS & HRPWM0_HRGHRS_HRGR_Msk) == 1U)
222 {
223 /* High resolution logic unit is ready */
224 status = XMC_HRPWM_STATUS_OK;
225 }
226 }
227 else
228 {
229 status = XMC_HRPWM_STATUS_ERROR; /* Clock frequency is invalid */
230 }
231
232 return (status);
233 }
234
235 /* Enable global high resolution generation */
XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t * const hrpwm)236 void XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t *const hrpwm)
237 {
238 XMC_ASSERT("XMC_HRPWM_EnableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
239
240 /* Enable global high resolution generation / Force charge pump down */
241 hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk;
242
243 XMC_HRPWM_lDelay(); /* Elapse startup time */
244 }
245
246 /* Disable global high resolution generation */
XMC_HRPWM_DisableGlobalHR(XMC_HRPWM_t * const hrpwm)247 void XMC_HRPWM_DisableGlobalHR(XMC_HRPWM_t *const hrpwm)
248 {
249 XMC_ASSERT("XMC_HRPWM_DisableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
250
251 /* Enable global high resolution generation / Force charge pump down */
252 hrpwm->GLBANA &= ~((uint32_t)HRPWM0_GLBANA_GHREN_Msk);
253 }
254
255 /***********************************************************************************************************************
256 * API IMPLEMENTATION - HRPWM HRC GLOBAL
257 **********************************************************************************************************************/
258 /* Checks and returns high resolution generation working status */
XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t * const hrpwm)259 XMC_HRPWM_HR_LOGIC_t XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t *const hrpwm)
260 {
261 XMC_HRPWM_HR_LOGIC_t status;
262
263 XMC_ASSERT("XMC_HRPWM_GetHRGenReadyStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
264
265 if (hrpwm->HRGHRS)
266 {
267 status = XMC_HRPWM_HR_LOGIC_WORKING;
268 }
269 else
270 {
271 status = XMC_HRPWM_HR_LOGIC_NOT_WORKING;
272 }
273 return status;
274 }
275
276 /***********************************************************************************************************************
277 * API IMPLEMENTATION - HRPWM HRC CHANNEL
278 **********************************************************************************************************************/
279 /* Initialize HRPWM HRC channel */
XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t * const hrc,const XMC_HRPWM_HRC_CONFIG_t * const config)280 void XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_CONFIG_t *const config)
281 {
282 XMC_ASSERT("XMC_HRPWM_HRC_Init:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc));
283
284 /* Setting of HRCy mode configuration */
285 hrc->GC = config->gc;
286
287 /* Passive level configuration */
288 hrc->PL = config->psl;
289 }
290
291 /* Configure Source selector 0 */
XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t * const hrc,const XMC_HRPWM_HRC_SRC_CONFIG_t * const config)292 void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config)
293 {
294 uint32_t reg;
295
296 XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect0:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc));
297
298 /* HRC mode config for source selector 0 */
299 hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM0_Msk);
300 hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM0_Pos;
301
302 /*****************************************************************************
303 * HRCy global control selection (HRCyGSEL)
304 ****************************************************************************/
305 reg = 0U;
306
307 if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG)
308 {
309 reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C0SS_Pos;
310 reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S0M_Pos; /* comparator output controls the set config */
311 }
312
313 if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG)
314 {
315 reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C0CS_Pos;
316 reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_C0M_Pos; /* comparator output controls the clear config */
317 }
318
319 reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S0ES_Pos;
320 reg |= ((uint32_t)config->clear_edge_config) << HRPWM0_HRC_GSEL_C0ES_Pos;
321 hrc->GSEL &= (uint32_t)0xFFFF0000;
322 hrc->GSEL |= reg;
323
324 /*****************************************************************************
325 * HRCy timer selection (HRCyTSEL)
326 ****************************************************************************/
327 reg = (uint32_t)config->timer_sel;
328 reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS0E_Pos;
329 hrc->TSEL &= (uint32_t)0xFFFEFFF8;
330 hrc->TSEL |= reg;
331 }
332
333 /* Configure Source selector 1 */
XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t * const hrc,const XMC_HRPWM_HRC_SRC_CONFIG_t * const config)334 void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config)
335 {
336 uint32_t reg;
337
338 XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect1:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc));
339
340 /* HRC mode config for source selector 1 */
341 hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM1_Msk);
342 hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM1_Pos;
343
344 /*****************************************************************************
345 * HRCy global control selection (HRCyGSEL)
346 ****************************************************************************/
347 reg = 0U;
348
349 if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG)
350 {
351 reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C1SS_Pos;
352 reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S1M_Pos; /* comparator output controls the set config*/
353 }
354
355 if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG)
356 {
357 reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C1CS_Pos;
358 reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_C1M_Pos; /* comparator output controls the clear config */
359 }
360
361 reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S1ES_Pos;
362 reg |= ((uint32_t)config->clear_edge_config) << HRPWM0_HRC_GSEL_C1ES_Pos;
363 hrc->GSEL &= (uint32_t)0x0000FFFF;
364 hrc->GSEL |= reg;
365
366 /*****************************************************************************
367 * HRCy timer selection (HRCyTSEL)
368 ****************************************************************************/
369 reg = (uint32_t)config->timer_sel;
370 reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS1E_Pos;
371 hrc->TSEL &= (uint32_t)0xFFFDFFC7;
372 hrc->TSEL |= reg;
373 }
374
375 /***********************************************************************************************************************
376 * API IMPLEMENTATION - HRPWM CSG GLOBAL
377 **********************************************************************************************************************/
378 /* No api's for CSG GLOBAL in xmc_hrpwm.c file */
379
380 /***********************************************************************************************************************
381 * API IMPLEMENTATION - HRPWM CSG SLICE
382 **********************************************************************************************************************/
383 /* Initialization of CSG slice */
XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_CONFIG_t * const config)384 void XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CONFIG_t *const config)
385 {
386 uint32_t reg;
387
388 XMC_ASSERT("XMC_HRPWM_CSG_Init:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
389
390 /* Passive level configuration */
391 csg->PLC = config->cmp_config.plc;
392
393 /* DAC Reference values */
394 csg->SDSV1 = config->dac_config.dac_dsv1;
395 csg->DSV2 = config->dac_config.dac_dsv2;
396
397 /* Pulse Swallow value */
398 csg->SPC = config->sgen_config.pulse_swallow_val;
399
400 /* Slope generation control (CSGySC) */
401 if(config->sgen_config.ctrl_mode != (uint32_t) XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC)
402 {
403 /* Dynamic Slope Generation */
404 csg->SC = config->sgen_config.sc;
405 }
406 else
407 {
408 /* Static Mode */
409 csg->SC = ((uint32_t)config->sgen_config.static_mode_ist_enable) << HRPWM0_CSG_SC_IST_Pos;
410 }
411 reg = ((uint32_t)config->dac_config.start_mode) << HRPWM0_CSG_SC_SWSM_Pos;
412 csg->SC |= reg;
413
414 /* Comparator Initialization */
415 csg->CC = config->cmp_config.cc;
416
417 /* Blanking value */
418 csg->BLV = config->cmp_config.blanking_val;
419 }
420
421 /* Set either CINA or CINB as inverting input of the comparator */
XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_CMP_INPUT_t input)422 void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CMP_INPUT_t input)
423 {
424 XMC_ASSERT("XMC_HRPWM_CSG_SetCMPInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
425
426 if (input == XMC_HRPWM_CSG_CMP_INPUT_CINA)
427 {
428 /* Inverting comparator input connected to CINA */
429 csg->CC &= ~((uint32_t)HRPWM0_CSG_CC_IMCS_Msk);
430 }
431 else
432 {
433 /* Inverting comparator input connected to CINB */
434 csg->CC |= (uint32_t)HRPWM0_CSG_CC_IMCS_Msk;
435 }
436 }
437
438 /* Configure input selection for Blanking function */
XMC_HRPWM_CSG_SelBlankingInput(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_INPUT_CONFIG_t * const config)439 void XMC_HRPWM_CSG_SelBlankingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
440 {
441 uint32_t reg;
442
443 XMC_ASSERT("XMC_HRPWM_CSG_SelBlankingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
444
445 reg = csg->CC;
446
447 if ((reg & HRPWM0_CSG_CC_EBE_Msk) != 0U) /* external blanking trigger enabled? */
448 {
449 reg &= ~((uint32_t)HRPWM0_CSG_CC_IBS_Msk);
450 reg |= (uint32_t) config->mapped_input;
451 }
452
453 reg &= ~((uint32_t)HRPWM0_CSG_CC_BLMC_Msk);
454 reg |= ((uint32_t) config->edge) << HRPWM0_CSG_CC_BLMC_Pos;
455
456 csg->CC = reg;
457 }
458
459 /* Configure input selection for Clamping */
XMC_HRPWM_CSG_SelClampingInput(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_INPUT_CONFIG_t * const config)460 void XMC_HRPWM_CSG_SelClampingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
461 {
462 uint32_t reg;
463
464 XMC_ASSERT("XMC_HRPWM_CSG_SelClampingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
465
466 reg = csg->PLC;
467
468 reg &= ~((uint32_t)HRPWM0_CSG_PLC_IPLS_Msk);
469 reg |= (uint32_t) config->mapped_input;
470
471 reg &= ~((uint32_t)HRPWM0_CSG_PLC_PLCL_Msk);
472 reg |= ((uint32_t) config->level) << HRPWM0_CSG_PLC_PLCL_Pos;
473
474 csg->PLC = reg;
475 }
476
477 /* Configure input selection to start slope generation function */
XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_INPUT_CONFIG_t * const config)478 void XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
479 {
480 XMC_ASSERT("XMC_HRPWM_CSG_StartSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
481
482 csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STRIS_Msk);
483 csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STRIS_Pos;
484 csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STRES_Msk);
485 csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STRES_Pos;
486 }
487
488 /* Configure input selection to stop slope generation function */
XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_INPUT_CONFIG_t * const config)489 void XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
490 {
491 XMC_ASSERT("XMC_HRPWM_CSG_StopSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
492
493 csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STPIS_Msk);
494 csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STPIS_Pos;
495 csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STPES_Msk);
496 csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STPES_Pos;
497 }
498
499 /* Configure input selection for triggering DAC conversion */
XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_INPUT_CONFIG_t * const config)500 void XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
501 {
502 XMC_ASSERT("XMC_HRPWM_CSG_TriggerDACConvConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
503
504 csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_TRGIS_Msk);
505 csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_TRGIS_Pos;
506 csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_TRGES_Msk);
507 csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_TRGES_Pos;
508 }
509
510 /* Configure input selection for triggering shadow transfer */
XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_INPUT_CONFIG_t * const config)511 void XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
512 {
513 XMC_ASSERT("XMC_HRPWM_CSG_TriggerShadowXferConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
514
515 csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STIS_Msk);
516 csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STIS_Pos;
517 csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STES_Msk);
518 csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STES_Pos;
519 }
520
521 /* Configure input selection to trigger a switch in DAC reference value. This is only applicable to DAC in static mode */
XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_INPUT_CONFIG_t * const config)522 void XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
523 {
524 XMC_ASSERT("XMC_HRPWM_CSG_DACRefValSwitchingConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
525
526 csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SVIS_Msk);
527 csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_SVIS_Pos;
528 csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_SVLS_Msk);
529 csg->IES |= ((uint32_t)config->level) << HRPWM0_CSG_IES_SVLS_Pos;
530 }
531
532 /* Configure input selection for clock selection used in slope generation */
XMC_HRPWM_CSG_SelSlopeGenClkInput(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_CLK_INPUT_t input_clk)533 void XMC_HRPWM_CSG_SelSlopeGenClkInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CLK_INPUT_t input_clk)
534 {
535 XMC_ASSERT("XMC_HRPWM_CSG_SelSlopeGenClkInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
536
537 csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SCS_Msk);
538 csg->DCI |= ((uint32_t)input_clk) << HRPWM0_CSG0_DCI_SCS_Pos;
539 }
540
541 /* Set the service request interrupt node */
XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t * const csg,const XMC_HRPWM_CSG_IRQ_ID_t event,const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr)542 void XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_IRQ_ID_t event,
543 const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr)
544 {
545 XMC_ASSERT("XMC_HRPWM_CSG_SetSRNode:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
546
547 switch (event)
548 {
549 case (XMC_HRPWM_CSG_IRQ_ID_VLS1):
550 csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_VLS1S_Msk);
551 csg->SRS |= (uint32_t)sr;
552 break;
553
554 case (XMC_HRPWM_CSG_IRQ_ID_VLS2):
555 csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_VLS2S_Msk);
556 csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_VLS2S_Pos;
557 break;
558
559 case (XMC_HRPWM_CSG_IRQ_ID_TRGS):
560 csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_TRLS_Msk);
561 csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_TRLS_Pos;
562 break;
563
564 case (XMC_HRPWM_CSG_IRQ_ID_STRS):
565 case (XMC_HRPWM_CSG_IRQ_ID_STPS):
566 csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_SSLS_Msk);
567 csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_SSLS_Pos;
568 break;
569
570 case (XMC_HRPWM_CSG_IRQ_ID_STD):
571 csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_STLS_Msk);
572 csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_STLS_Pos;
573 break;
574
575 case (XMC_HRPWM_CSG_IRQ_ID_CRSE):
576 case (XMC_HRPWM_CSG_IRQ_ID_CFSE):
577 csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_CRFLS_Msk);
578 csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_CRFLS_Pos;
579 break;
580
581 case (XMC_HRPWM_CSG_IRQ_ID_CSEE):
582 csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_CSLS_Msk);
583 csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_CSLS_Pos;
584 break;
585
586 default:
587 break;
588 }
589 }
590
591 #endif /* #if defined(HRPWM0) */
592
