1 /***************************************************************************//** 2 * \file gpio_xmc7100_100_teqfp.h 3 * 4 * \brief 5 * XMC7100 device GPIO header for 100-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_XMC7100_100_TEQFP_H_ 28 #define _GPIO_XMC7100_100_TEQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TEQFP 44 #define CY_GPIO_PIN_COUNT 100u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_MAIN, 50 AMUXBUS_REGHC_ISENSE, 51 AMUXBUS_TEST, 52 AMUXBUS_TESTECT, 53 AMUXBUS_TESTSRSS, 54 }; 55 56 /* AMUX Splitter Controls */ 57 typedef enum 58 { 59 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_REGHC_ISENSE */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (AUTOLVL) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P0_1_PORT GPIO_PRT0 71 #define P0_1_PIN 1u 72 #define P0_1_NUM 1u 73 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 78 #define P0_3_PORT GPIO_PRT0 79 #define P0_3_PIN 3u 80 #define P0_3_NUM 3u 81 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 2 (AUTOLVL) */ 84 #define P2_0_PORT GPIO_PRT2 85 #define P2_0_PIN 0u 86 #define P2_0_NUM 0u 87 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 88 #define P2_1_PORT GPIO_PRT2 89 #define P2_1_PIN 1u 90 #define P2_1_NUM 1u 91 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 92 #define P2_2_PORT GPIO_PRT2 93 #define P2_2_PIN 2u 94 #define P2_2_NUM 2u 95 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 96 #define P2_3_PORT GPIO_PRT2 97 #define P2_3_PIN 3u 98 #define P2_3_NUM 3u 99 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 100 101 /* PORT 3 (AUTOLVL) */ 102 #define P3_0_PORT GPIO_PRT3 103 #define P3_0_PIN 0u 104 #define P3_0_NUM 0u 105 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 106 #define P3_1_PORT GPIO_PRT3 107 #define P3_1_PIN 1u 108 #define P3_1_NUM 1u 109 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 110 111 /* PORT 5 (AUTOLVL) */ 112 #define P5_0_PORT GPIO_PRT5 113 #define P5_0_PIN 0u 114 #define P5_0_NUM 0u 115 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 116 #define P5_1_PORT GPIO_PRT5 117 #define P5_1_PIN 1u 118 #define P5_1_NUM 1u 119 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 120 #define P5_2_PORT GPIO_PRT5 121 #define P5_2_PIN 2u 122 #define P5_2_NUM 2u 123 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 124 #define P5_3_PORT GPIO_PRT5 125 #define P5_3_PIN 3u 126 #define P5_3_NUM 3u 127 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 128 129 /* PORT 6 (AUTOLVL) */ 130 #define P6_0_PORT GPIO_PRT6 131 #define P6_0_PIN 0u 132 #define P6_0_NUM 0u 133 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 134 #define P6_1_PORT GPIO_PRT6 135 #define P6_1_PIN 1u 136 #define P6_1_NUM 1u 137 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 138 #define P6_2_PORT GPIO_PRT6 139 #define P6_2_PIN 2u 140 #define P6_2_NUM 2u 141 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 142 #define P6_3_PORT GPIO_PRT6 143 #define P6_3_PIN 3u 144 #define P6_3_NUM 3u 145 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 146 #define P6_4_PORT GPIO_PRT6 147 #define P6_4_PIN 4u 148 #define P6_4_NUM 4u 149 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 150 #define P6_5_PORT GPIO_PRT6 151 #define P6_5_PIN 5u 152 #define P6_5_NUM 5u 153 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 154 155 /* PORT 7 (AUTOLVL) */ 156 #define P7_0_PORT GPIO_PRT7 157 #define P7_0_PIN 0u 158 #define P7_0_NUM 0u 159 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 160 #define P7_1_PORT GPIO_PRT7 161 #define P7_1_PIN 1u 162 #define P7_1_NUM 1u 163 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 164 #define P7_2_PORT GPIO_PRT7 165 #define P7_2_PIN 2u 166 #define P7_2_NUM 2u 167 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 168 #define P7_3_PORT GPIO_PRT7 169 #define P7_3_PIN 3u 170 #define P7_3_NUM 3u 171 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 172 #define P7_4_PORT GPIO_PRT7 173 #define P7_4_PIN 4u 174 #define P7_4_NUM 4u 175 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 176 #define P7_5_PORT GPIO_PRT7 177 #define P7_5_PIN 5u 178 #define P7_5_NUM 5u 179 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 180 181 /* PORT 8 (AUTOLVL) */ 182 #define P8_0_PORT GPIO_PRT8 183 #define P8_0_PIN 0u 184 #define P8_0_NUM 0u 185 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 186 #define P8_1_PORT GPIO_PRT8 187 #define P8_1_PIN 1u 188 #define P8_1_NUM 1u 189 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 190 #define P8_2_PORT GPIO_PRT8 191 #define P8_2_PIN 2u 192 #define P8_2_NUM 2u 193 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 194 195 /* PORT 11 (AUTOLVL) */ 196 #define P11_0_PORT GPIO_PRT11 197 #define P11_0_PIN 0u 198 #define P11_0_NUM 0u 199 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 200 #define P11_1_PORT GPIO_PRT11 201 #define P11_1_PIN 1u 202 #define P11_1_NUM 1u 203 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 204 #define P11_2_PORT GPIO_PRT11 205 #define P11_2_PIN 2u 206 #define P11_2_NUM 2u 207 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 208 209 /* PORT 12 (AUTOLVL) */ 210 #define P12_0_PORT GPIO_PRT12 211 #define P12_0_PIN 0u 212 #define P12_0_NUM 0u 213 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 214 #define P12_1_PORT GPIO_PRT12 215 #define P12_1_PIN 1u 216 #define P12_1_NUM 1u 217 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 218 #define P12_2_PORT GPIO_PRT12 219 #define P12_2_PIN 2u 220 #define P12_2_NUM 2u 221 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 222 #define P12_3_PORT GPIO_PRT12 223 #define P12_3_PIN 3u 224 #define P12_3_NUM 3u 225 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 226 #define P12_4_PORT GPIO_PRT12 227 #define P12_4_PIN 4u 228 #define P12_4_NUM 4u 229 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 230 231 /* PORT 13 (AUTOLVL) */ 232 #define P13_0_PORT GPIO_PRT13 233 #define P13_0_PIN 0u 234 #define P13_0_NUM 0u 235 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 236 #define P13_1_PORT GPIO_PRT13 237 #define P13_1_PIN 1u 238 #define P13_1_NUM 1u 239 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 240 #define P13_2_PORT GPIO_PRT13 241 #define P13_2_PIN 2u 242 #define P13_2_NUM 2u 243 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 244 #define P13_3_PORT GPIO_PRT13 245 #define P13_3_PIN 3u 246 #define P13_3_NUM 3u 247 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 248 #define P13_4_PORT GPIO_PRT13 249 #define P13_4_PIN 4u 250 #define P13_4_NUM 4u 251 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 252 #define P13_5_PORT GPIO_PRT13 253 #define P13_5_PIN 5u 254 #define P13_5_NUM 5u 255 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 256 #define P13_6_PORT GPIO_PRT13 257 #define P13_6_PIN 6u 258 #define P13_6_NUM 6u 259 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 260 #define P13_7_PORT GPIO_PRT13 261 #define P13_7_PIN 7u 262 #define P13_7_NUM 7u 263 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 264 265 /* PORT 14 (AUTOLVL) */ 266 #define P14_0_PORT GPIO_PRT14 267 #define P14_0_PIN 0u 268 #define P14_0_NUM 0u 269 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 270 #define P14_1_PORT GPIO_PRT14 271 #define P14_1_PIN 1u 272 #define P14_1_NUM 1u 273 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 274 275 /* PORT 18 (AUTOLVL) */ 276 #define P18_0_PORT GPIO_PRT18 277 #define P18_0_PIN 0u 278 #define P18_0_NUM 0u 279 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 280 #define P18_1_PORT GPIO_PRT18 281 #define P18_1_PIN 1u 282 #define P18_1_NUM 1u 283 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 284 #define P18_2_PORT GPIO_PRT18 285 #define P18_2_PIN 2u 286 #define P18_2_NUM 2u 287 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 288 #define P18_3_PORT GPIO_PRT18 289 #define P18_3_PIN 3u 290 #define P18_3_NUM 3u 291 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 292 #define P18_4_PORT GPIO_PRT18 293 #define P18_4_PIN 4u 294 #define P18_4_NUM 4u 295 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 296 #define P18_5_PORT GPIO_PRT18 297 #define P18_5_PIN 5u 298 #define P18_5_NUM 5u 299 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 300 #define P18_6_PORT GPIO_PRT18 301 #define P18_6_PIN 6u 302 #define P18_6_NUM 6u 303 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 304 #define P18_7_PORT GPIO_PRT18 305 #define P18_7_PIN 7u 306 #define P18_7_NUM 7u 307 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 308 309 /* PORT 19 (AUTOLVL) */ 310 #define P19_0_PORT GPIO_PRT19 311 #define P19_0_PIN 0u 312 #define P19_0_NUM 0u 313 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 314 #define P19_1_PORT GPIO_PRT19 315 #define P19_1_PIN 1u 316 #define P19_1_NUM 1u 317 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 318 #define P19_2_PORT GPIO_PRT19 319 #define P19_2_PIN 2u 320 #define P19_2_NUM 2u 321 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 322 #define P19_3_PORT GPIO_PRT19 323 #define P19_3_PIN 3u 324 #define P19_3_NUM 3u 325 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 326 327 /* PORT 21 (AUTOLVL) */ 328 #define P21_0_PORT GPIO_PRT21 329 #define P21_0_PIN 0u 330 #define P21_0_NUM 0u 331 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 332 #define P21_1_PORT GPIO_PRT21 333 #define P21_1_PIN 1u 334 #define P21_1_NUM 1u 335 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 336 #define P21_2_PORT GPIO_PRT21 337 #define P21_2_PIN 2u 338 #define P21_2_NUM 2u 339 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 340 #define P21_3_PORT GPIO_PRT21 341 #define P21_3_PIN 3u 342 #define P21_3_NUM 3u 343 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 344 #define P21_5_PORT GPIO_PRT21 345 #define P21_5_PIN 5u 346 #define P21_5_NUM 5u 347 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 348 349 /* PORT 22 (AUTOLVL) */ 350 #define P22_1_PORT GPIO_PRT22 351 #define P22_1_PIN 1u 352 #define P22_1_NUM 1u 353 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 354 #define P22_2_PORT GPIO_PRT22 355 #define P22_2_PIN 2u 356 #define P22_2_NUM 2u 357 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 358 #define P22_3_PORT GPIO_PRT22 359 #define P22_3_PIN 3u 360 #define P22_3_NUM 3u 361 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 362 363 /* PORT 23 (AUTOLVL) */ 364 #define P23_3_PORT GPIO_PRT23 365 #define P23_3_PIN 3u 366 #define P23_3_NUM 3u 367 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 368 #define P23_4_PORT GPIO_PRT23 369 #define P23_4_PIN 4u 370 #define P23_4_NUM 4u 371 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 372 #define P23_5_PORT GPIO_PRT23 373 #define P23_5_PIN 5u 374 #define P23_5_NUM 5u 375 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 376 #define P23_6_PORT GPIO_PRT23 377 #define P23_6_PIN 6u 378 #define P23_6_NUM 6u 379 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 380 #define P23_7_PORT GPIO_PRT23 381 #define P23_7_PIN 7u 382 #define P23_7_NUM 7u 383 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 384 385 /* Analog Connections */ 386 #define PASS0_I_TEMP_KELVIN_PORT 21u 387 #define PASS0_I_TEMP_KELVIN_PIN 2u 388 #define PASS0_SARMUX_MOTOR0_PORT 11u 389 #define PASS0_SARMUX_MOTOR0_PIN 0u 390 #define PASS0_SARMUX_MOTOR1_PORT 11u 391 #define PASS0_SARMUX_MOTOR1_PIN 1u 392 #define PASS0_SARMUX_MOTOR2_PORT 11u 393 #define PASS0_SARMUX_MOTOR2_PIN 2u 394 #define PASS0_SARMUX_PADS0_PORT 6u 395 #define PASS0_SARMUX_PADS0_PIN 0u 396 #define PASS0_SARMUX_PADS1_PORT 6u 397 #define PASS0_SARMUX_PADS1_PIN 1u 398 #define PASS0_SARMUX_PADS16_PORT 7u 399 #define PASS0_SARMUX_PADS16_PIN 0u 400 #define PASS0_SARMUX_PADS17_PORT 7u 401 #define PASS0_SARMUX_PADS17_PIN 1u 402 #define PASS0_SARMUX_PADS18_PORT 7u 403 #define PASS0_SARMUX_PADS18_PIN 2u 404 #define PASS0_SARMUX_PADS19_PORT 7u 405 #define PASS0_SARMUX_PADS19_PIN 3u 406 #define PASS0_SARMUX_PADS2_PORT 6u 407 #define PASS0_SARMUX_PADS2_PIN 2u 408 #define PASS0_SARMUX_PADS20_PORT 7u 409 #define PASS0_SARMUX_PADS20_PIN 4u 410 #define PASS0_SARMUX_PADS21_PORT 7u 411 #define PASS0_SARMUX_PADS21_PIN 5u 412 #define PASS0_SARMUX_PADS24_PORT 8u 413 #define PASS0_SARMUX_PADS24_PIN 1u 414 #define PASS0_SARMUX_PADS25_PORT 8u 415 #define PASS0_SARMUX_PADS25_PIN 2u 416 #define PASS0_SARMUX_PADS3_PORT 6u 417 #define PASS0_SARMUX_PADS3_PIN 3u 418 #define PASS0_SARMUX_PADS36_PORT 12u 419 #define PASS0_SARMUX_PADS36_PIN 0u 420 #define PASS0_SARMUX_PADS37_PORT 12u 421 #define PASS0_SARMUX_PADS37_PIN 1u 422 #define PASS0_SARMUX_PADS38_PORT 12u 423 #define PASS0_SARMUX_PADS38_PIN 2u 424 #define PASS0_SARMUX_PADS39_PORT 12u 425 #define PASS0_SARMUX_PADS39_PIN 3u 426 #define PASS0_SARMUX_PADS4_PORT 6u 427 #define PASS0_SARMUX_PADS4_PIN 4u 428 #define PASS0_SARMUX_PADS40_PORT 12u 429 #define PASS0_SARMUX_PADS40_PIN 4u 430 #define PASS0_SARMUX_PADS44_PORT 13u 431 #define PASS0_SARMUX_PADS44_PIN 0u 432 #define PASS0_SARMUX_PADS45_PORT 13u 433 #define PASS0_SARMUX_PADS45_PIN 1u 434 #define PASS0_SARMUX_PADS46_PORT 13u 435 #define PASS0_SARMUX_PADS46_PIN 2u 436 #define PASS0_SARMUX_PADS47_PORT 13u 437 #define PASS0_SARMUX_PADS47_PIN 3u 438 #define PASS0_SARMUX_PADS48_PORT 13u 439 #define PASS0_SARMUX_PADS48_PIN 4u 440 #define PASS0_SARMUX_PADS49_PORT 13u 441 #define PASS0_SARMUX_PADS49_PIN 5u 442 #define PASS0_SARMUX_PADS5_PORT 6u 443 #define PASS0_SARMUX_PADS5_PIN 5u 444 #define PASS0_SARMUX_PADS50_PORT 13u 445 #define PASS0_SARMUX_PADS50_PIN 6u 446 #define PASS0_SARMUX_PADS51_PORT 13u 447 #define PASS0_SARMUX_PADS51_PIN 7u 448 #define PASS0_SARMUX_PADS52_PORT 14u 449 #define PASS0_SARMUX_PADS52_PIN 0u 450 #define PASS0_SARMUX_PADS53_PORT 14u 451 #define PASS0_SARMUX_PADS53_PIN 1u 452 #define PASS0_SARMUX_PADS64_PORT 18u 453 #define PASS0_SARMUX_PADS64_PIN 0u 454 #define PASS0_SARMUX_PADS65_PORT 18u 455 #define PASS0_SARMUX_PADS65_PIN 1u 456 #define PASS0_SARMUX_PADS66_PORT 18u 457 #define PASS0_SARMUX_PADS66_PIN 2u 458 #define PASS0_SARMUX_PADS67_PORT 18u 459 #define PASS0_SARMUX_PADS67_PIN 3u 460 #define PASS0_SARMUX_PADS68_PORT 18u 461 #define PASS0_SARMUX_PADS68_PIN 4u 462 #define PASS0_SARMUX_PADS69_PORT 18u 463 #define PASS0_SARMUX_PADS69_PIN 5u 464 #define PASS0_SARMUX_PADS70_PORT 18u 465 #define PASS0_SARMUX_PADS70_PIN 6u 466 #define PASS0_SARMUX_PADS71_PORT 18u 467 #define PASS0_SARMUX_PADS71_PIN 7u 468 #define PASS0_VE_TEMP_KELVIN_PORT 23u 469 #define PASS0_VE_TEMP_KELVIN_PIN 4u 470 #define SRSS_ADFT_PIN0_PORT 23u 471 #define SRSS_ADFT_PIN0_PIN 4u 472 #define SRSS_ADFT_PIN1_PORT 23u 473 #define SRSS_ADFT_PIN1_PIN 3u 474 #define SRSS_ECO_IN_PORT 21u 475 #define SRSS_ECO_IN_PIN 2u 476 #define SRSS_ECO_OUT_PORT 21u 477 #define SRSS_ECO_OUT_PIN 3u 478 #define SRSS_REGHC_ISENSE_INM_PORT 22u 479 #define SRSS_REGHC_ISENSE_INM_PIN 2u 480 #define SRSS_REGHC_ISENSE_INP_PORT 22u 481 #define SRSS_REGHC_ISENSE_INP_PIN 1u 482 #define SRSS_REGHC_RST_VOUT_PORT 22u 483 #define SRSS_REGHC_RST_VOUT_PIN 3u 484 #define SRSS_VEXT_REF_REG_PORT 21u 485 #define SRSS_VEXT_REF_REG_PIN 3u 486 #define SRSS_WCO_IN_PORT 21u 487 #define SRSS_WCO_IN_PIN 0u 488 #define SRSS_WCO_OUT_PORT 21u 489 #define SRSS_WCO_OUT_PIN 1u 490 491 /* HSIOM Connections */ 492 typedef enum 493 { 494 /* Generic HSIOM connections */ 495 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 496 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 497 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 498 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 499 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 500 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 501 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 502 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 503 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 504 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 505 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 506 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 507 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 508 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 509 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 510 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 511 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 512 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 513 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 514 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 515 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 516 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 517 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 518 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 519 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 520 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 521 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 522 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 523 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 524 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 525 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 526 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 527 528 /* P0.0 */ 529 P0_0_GPIO = 0, /* GPIO controls 'out' */ 530 P0_0_AMUXA = 4, /* Analog mux bus A */ 531 P0_0_AMUXB = 5, /* Analog mux bus B */ 532 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 533 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 534 P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ 535 P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 536 P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ 537 P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ 538 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 539 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 540 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 541 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 542 543 /* P0.1 */ 544 P0_1_GPIO = 0, /* GPIO controls 'out' */ 545 P0_1_AMUXA = 4, /* Analog mux bus A */ 546 P0_1_AMUXB = 5, /* Analog mux bus B */ 547 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 548 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 549 P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ 550 P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ 551 P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ 552 P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ 553 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 554 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 555 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 556 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 557 558 /* P0.2 */ 559 P0_2_GPIO = 0, /* GPIO controls 'out' */ 560 P0_2_AMUXA = 4, /* Analog mux bus A */ 561 P0_2_AMUXB = 5, /* Analog mux bus B */ 562 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 563 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 564 P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ 565 P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ 566 P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ 567 P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ 568 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 569 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 570 P0_2_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:2 */ 571 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 572 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 573 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 574 575 /* P0.3 */ 576 P0_3_GPIO = 0, /* GPIO controls 'out' */ 577 P0_3_AMUXA = 4, /* Analog mux bus A */ 578 P0_3_AMUXB = 5, /* Analog mux bus B */ 579 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 580 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 581 P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ 582 P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ 583 P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ 584 P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ 585 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 586 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 587 P0_3_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:2 */ 588 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 589 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 590 591 /* P2.0 */ 592 P2_0_GPIO = 0, /* GPIO controls 'out' */ 593 P2_0_AMUXA = 4, /* Analog mux bus A */ 594 P2_0_AMUXB = 5, /* Analog mux bus B */ 595 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 596 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 597 P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 598 P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ 599 P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 600 P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 601 P2_0_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:0 */ 602 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 603 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 604 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 605 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 606 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 607 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 608 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 609 610 /* P2.1 */ 611 P2_1_GPIO = 0, /* GPIO controls 'out' */ 612 P2_1_AMUXA = 4, /* Analog mux bus A */ 613 P2_1_AMUXB = 5, /* Analog mux bus B */ 614 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 615 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 616 P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 617 P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 618 P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ 619 P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 620 P2_1_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:0 */ 621 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 622 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 623 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 624 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 625 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 626 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 627 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 628 629 /* P2.2 */ 630 P2_2_GPIO = 0, /* GPIO controls 'out' */ 631 P2_2_AMUXA = 4, /* Analog mux bus A */ 632 P2_2_AMUXB = 5, /* Analog mux bus B */ 633 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 634 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 635 P2_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 636 P2_2_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 637 P2_2_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:1 */ 638 P2_2_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:1 */ 639 P2_2_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:0 */ 640 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 641 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 642 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 643 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 644 P2_2_ETH0_RX_ER = 24, /* Digital Active - eth[0].rx_er:0 */ 645 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 646 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 647 648 /* P2.3 */ 649 P2_3_GPIO = 0, /* GPIO controls 'out' */ 650 P2_3_AMUXA = 4, /* Analog mux bus A */ 651 P2_3_AMUXB = 5, /* Analog mux bus B */ 652 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 653 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 654 P2_3_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 655 P2_3_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 656 P2_3_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:1 */ 657 P2_3_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:1 */ 658 P2_3_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:0 */ 659 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 660 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 661 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 662 P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL = 24, /* Digital Active - eth[0].eth_tsu_timer_cmp_val:0 */ 663 P2_3_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:1 */ 664 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 665 666 /* P3.0 */ 667 P3_0_GPIO = 0, /* GPIO controls 'out' */ 668 P3_0_AMUXA = 4, /* Analog mux bus A */ 669 P3_0_AMUXB = 5, /* Analog mux bus B */ 670 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 671 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 672 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 673 P3_0_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 674 P3_0_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ 675 P3_0_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:1 */ 676 P3_0_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:0 */ 677 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 678 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 679 P3_0_CANFD0_TTCAN_TX3 = 21, /* Digital Active - canfd[0].ttcan_tx[3]:0 */ 680 P3_0_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio:0 */ 681 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 682 683 /* P3.1 */ 684 P3_1_GPIO = 0, /* GPIO controls 'out' */ 685 P3_1_AMUXA = 4, /* Analog mux bus A */ 686 P3_1_AMUXB = 5, /* Analog mux bus B */ 687 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 688 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 689 P3_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 690 P3_1_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 691 P3_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ 692 P3_1_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:1 */ 693 P3_1_TCPWM0_LINE_COMPL519 = 16, /* Digital Active - tcpwm[0].line_compl[519]:0 */ 694 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 695 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 696 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 697 P3_1_CANFD0_TTCAN_RX3 = 21, /* Digital Active - canfd[0].ttcan_rx[3]:0 */ 698 P3_1_ETH0_MDC = 24, /* Digital Active - eth[0].mdc:0 */ 699 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 700 701 /* P5.0 */ 702 P5_0_GPIO = 0, /* GPIO controls 'out' */ 703 P5_0_AMUXA = 4, /* Analog mux bus A */ 704 P5_0_AMUXB = 5, /* Analog mux bus B */ 705 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 706 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 707 P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ 708 P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ 709 P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 710 P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 711 P5_0_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:1 */ 712 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 713 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 714 715 /* P5.1 */ 716 P5_1_GPIO = 0, /* GPIO controls 'out' */ 717 P5_1_AMUXA = 4, /* Analog mux bus A */ 718 P5_1_AMUXB = 5, /* Analog mux bus B */ 719 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 720 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 721 P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ 722 P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ 723 P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 724 P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 725 P5_1_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:1 */ 726 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 727 728 /* P5.2 */ 729 P5_2_GPIO = 0, /* GPIO controls 'out' */ 730 P5_2_AMUXA = 4, /* Analog mux bus A */ 731 P5_2_AMUXB = 5, /* Analog mux bus B */ 732 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 733 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 734 P5_2_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:0 */ 735 P5_2_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:0 */ 736 P5_2_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ 737 P5_2_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ 738 P5_2_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:2 */ 739 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 740 741 /* P5.3 */ 742 P5_3_GPIO = 0, /* GPIO controls 'out' */ 743 P5_3_AMUXA = 4, /* Analog mux bus A */ 744 P5_3_AMUXB = 5, /* Analog mux bus B */ 745 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 746 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 747 P5_3_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:0 */ 748 P5_3_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:0 */ 749 P5_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ 750 P5_3_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ 751 P5_3_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:2 */ 752 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 753 754 /* P6.0 */ 755 P6_0_GPIO = 0, /* GPIO controls 'out' */ 756 P6_0_AMUXA = 4, /* Analog mux bus A */ 757 P6_0_AMUXB = 5, /* Analog mux bus B */ 758 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 759 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 760 P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 761 P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ 762 P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ 763 P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ 764 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 765 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 766 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 767 P6_0_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:1 */ 768 769 /* P6.1 */ 770 P6_1_GPIO = 0, /* GPIO controls 'out' */ 771 P6_1_AMUXA = 4, /* Analog mux bus A */ 772 P6_1_AMUXB = 5, /* Analog mux bus B */ 773 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 774 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 775 P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 776 P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 777 P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 778 P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ 779 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 780 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 781 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 782 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 783 784 /* P6.2 */ 785 P6_2_GPIO = 0, /* GPIO controls 'out' */ 786 P6_2_AMUXA = 4, /* Analog mux bus A */ 787 P6_2_AMUXB = 5, /* Analog mux bus B */ 788 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 789 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 790 P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 791 P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 792 P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ 793 P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 794 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 795 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 796 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 797 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 798 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 799 P6_2_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:0 */ 800 801 /* P6.3 */ 802 P6_3_GPIO = 0, /* GPIO controls 'out' */ 803 P6_3_AMUXA = 4, /* Analog mux bus A */ 804 P6_3_AMUXB = 5, /* Analog mux bus B */ 805 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 806 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 807 P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 808 P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 809 P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 810 P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ 811 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 812 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 813 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 814 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 815 P6_3_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:0 */ 816 P6_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:0 */ 817 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 818 819 /* P6.4 */ 820 P6_4_GPIO = 0, /* GPIO controls 'out' */ 821 P6_4_AMUXA = 4, /* Analog mux bus A */ 822 P6_4_AMUXB = 5, /* Analog mux bus B */ 823 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 824 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 825 P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 826 P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 827 P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ 828 P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ 829 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 830 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 831 P6_4_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:0 */ 832 P6_4_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:0 */ 833 834 /* P6.5 */ 835 P6_5_GPIO = 0, /* GPIO controls 'out' */ 836 P6_5_AMUXA = 4, /* Analog mux bus A */ 837 P6_5_AMUXB = 5, /* Analog mux bus B */ 838 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 839 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 840 P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 841 P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 842 P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ 843 P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ 844 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 845 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 846 P6_5_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:0 */ 847 P6_5_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:0 */ 848 849 /* P7.0 */ 850 P7_0_GPIO = 0, /* GPIO controls 'out' */ 851 P7_0_AMUXA = 4, /* Analog mux bus A */ 852 P7_0_AMUXB = 5, /* Analog mux bus B */ 853 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 854 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 855 P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 856 P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 857 P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ 858 P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ 859 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 860 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 861 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 862 P7_0_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:0 */ 863 P7_0_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:0 */ 864 865 /* P7.1 */ 866 P7_1_GPIO = 0, /* GPIO controls 'out' */ 867 P7_1_AMUXA = 4, /* Analog mux bus A */ 868 P7_1_AMUXB = 5, /* Analog mux bus B */ 869 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 870 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 871 P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ 872 P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 873 P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ 874 P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ 875 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 876 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 877 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 878 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 879 P7_1_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:0 */ 880 P7_1_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:0 */ 881 882 /* P7.2 */ 883 P7_2_GPIO = 0, /* GPIO controls 'out' */ 884 P7_2_AMUXA = 4, /* Analog mux bus A */ 885 P7_2_AMUXB = 5, /* Analog mux bus B */ 886 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 887 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 888 P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 889 P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ 890 P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ 891 P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ 892 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 893 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 894 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 895 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 896 P7_2_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:0 */ 897 P7_2_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:0 */ 898 899 /* P7.3 */ 900 P7_3_GPIO = 0, /* GPIO controls 'out' */ 901 P7_3_AMUXA = 4, /* Analog mux bus A */ 902 P7_3_AMUXB = 5, /* Analog mux bus B */ 903 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 904 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 905 P7_3_TCPWM0_LINE16 = 8, /* Digital Active - tcpwm[0].line[16]:0 */ 906 P7_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 907 P7_3_TCPWM0_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[48]:0 */ 908 P7_3_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:0 */ 909 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 910 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 911 P7_3_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:0 */ 912 P7_3_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:0 */ 913 914 /* P7.4 */ 915 P7_4_GPIO = 0, /* GPIO controls 'out' */ 916 P7_4_AMUXA = 4, /* Analog mux bus A */ 917 P7_4_AMUXB = 5, /* Analog mux bus B */ 918 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 919 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 920 P7_4_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:0 */ 921 P7_4_TCPWM0_LINE_COMPL16 = 9, /* Digital Active - tcpwm[0].line_compl[16]:0 */ 922 P7_4_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:0 */ 923 P7_4_TCPWM0_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[49]:0 */ 924 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 925 P7_4_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:0 */ 926 P7_4_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:0 */ 927 928 /* P7.5 */ 929 P7_5_GPIO = 0, /* GPIO controls 'out' */ 930 P7_5_AMUXA = 4, /* Analog mux bus A */ 931 P7_5_AMUXB = 5, /* Analog mux bus B */ 932 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 933 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 934 P7_5_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:0 */ 935 P7_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 936 P7_5_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:0 */ 937 P7_5_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:0 */ 938 P7_5_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:0 */ 939 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 940 P7_5_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:0 */ 941 P7_5_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:0 */ 942 943 /* P8.0 */ 944 P8_0_GPIO = 0, /* GPIO controls 'out' */ 945 P8_0_AMUXA = 4, /* Analog mux bus A */ 946 P8_0_AMUXB = 5, /* Analog mux bus B */ 947 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 948 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 949 P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ 950 P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ 951 P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ 952 P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ 953 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 954 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 955 P8_0_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:0 */ 956 P8_0_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:0 */ 957 958 /* P8.1 */ 959 P8_1_GPIO = 0, /* GPIO controls 'out' */ 960 P8_1_AMUXA = 4, /* Analog mux bus A */ 961 P8_1_AMUXB = 5, /* Analog mux bus B */ 962 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 963 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 964 P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 965 P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ 966 P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ 967 P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ 968 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 969 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 970 P8_1_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:0 */ 971 P8_1_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:0 */ 972 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 973 974 /* P8.2 */ 975 P8_2_GPIO = 0, /* GPIO controls 'out' */ 976 P8_2_AMUXA = 4, /* Analog mux bus A */ 977 P8_2_AMUXB = 5, /* Analog mux bus B */ 978 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 979 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 980 P8_2_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ 981 P8_2_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ 982 P8_2_TCPWM0_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[63]:0 */ 983 P8_2_TCPWM0_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[61]:0 */ 984 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 985 P8_2_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:0 */ 986 P8_2_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:0 */ 987 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 988 989 /* P11.0 */ 990 P11_0_GPIO = 0, /* GPIO controls 'out' */ 991 P11_0_AMUXA = 4, /* Analog mux bus A */ 992 P11_0_AMUXB = 5, /* Analog mux bus B */ 993 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 994 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 995 P11_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:2 */ 996 P11_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:2 */ 997 P11_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:2 */ 998 P11_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:2 */ 999 P11_0_AUDIOSS0_MCLK = 25, /* Digital Active - audioss[0].mclk:0 */ 1000 1001 /* P11.1 */ 1002 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1003 P11_1_AMUXA = 4, /* Analog mux bus A */ 1004 P11_1_AMUXB = 5, /* Analog mux bus B */ 1005 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1006 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1007 P11_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:2 */ 1008 P11_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:2 */ 1009 P11_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:2 */ 1010 P11_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:2 */ 1011 P11_1_AUDIOSS0_TX_SCK = 25, /* Digital Active - audioss[0].tx_sck:0 */ 1012 1013 /* P11.2 */ 1014 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1015 P11_2_AMUXA = 4, /* Analog mux bus A */ 1016 P11_2_AMUXB = 5, /* Analog mux bus B */ 1017 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1018 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1019 P11_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:2 */ 1020 P11_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:2 */ 1021 P11_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:2 */ 1022 P11_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:2 */ 1023 P11_2_AUDIOSS0_TX_WS = 25, /* Digital Active - audioss[0].tx_ws:0 */ 1024 1025 /* P12.0 */ 1026 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1027 P12_0_AMUXA = 4, /* Analog mux bus A */ 1028 P12_0_AMUXB = 5, /* Analog mux bus B */ 1029 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1030 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1031 P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 1032 P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ 1033 P12_0_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:0 */ 1034 P12_0_TCPWM0_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ 1035 P12_0_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:0 */ 1036 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 1037 P12_0_TCPWM0_LINE_COMPL35 = 23, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 1038 P12_0_AUDIOSS0_TX_SDO = 25, /* Digital Active - audioss[0].tx_sdo:0 */ 1039 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 1040 1041 /* P12.1 */ 1042 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1043 P12_1_AMUXA = 4, /* Analog mux bus A */ 1044 P12_1_AMUXB = 5, /* Analog mux bus B */ 1045 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1046 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1047 P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 1048 P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 1049 P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ 1050 P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ 1051 P12_1_SCB8_UART_TX = 17, /* Digital Active - scb[8].uart_tx:0 */ 1052 P12_1_SCB8_I2C_SDA = 18, /* Digital Active - scb[8].i2c_sda:0 */ 1053 P12_1_SCB8_SPI_MOSI = 19, /* Digital Active - scb[8].spi_mosi:0 */ 1054 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 1055 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 1056 P12_1_AUDIOSS0_CLK_I2S_IF = 25, /* Digital Active - audioss[0].clk_i2s_if:0 */ 1057 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 1058 1059 /* P12.2 */ 1060 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1061 P12_2_AMUXA = 4, /* Analog mux bus A */ 1062 P12_2_AMUXB = 5, /* Analog mux bus B */ 1063 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1064 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1065 P12_2_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:0 */ 1066 P12_2_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ 1067 P12_2_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:0 */ 1068 P12_2_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:0 */ 1069 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 1070 P12_2_SCB8_UART_RTS = 17, /* Digital Active - scb[8].uart_rts:0 */ 1071 P12_2_SCB8_I2C_SCL = 18, /* Digital Active - scb[8].i2c_scl:0 */ 1072 P12_2_SCB8_SPI_CLK = 19, /* Digital Active - scb[8].spi_clk:0 */ 1073 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 1074 P12_2_AUDIOSS0_RX_SCK = 25, /* Digital Active - audioss[0].rx_sck:0 */ 1075 1076 /* P12.3 */ 1077 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1078 P12_3_AMUXA = 4, /* Analog mux bus A */ 1079 P12_3_AMUXB = 5, /* Analog mux bus B */ 1080 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1081 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1082 P12_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:0 */ 1083 P12_3_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:0 */ 1084 P12_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:0 */ 1085 P12_3_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:0 */ 1086 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 1087 P12_3_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:0 */ 1088 P12_3_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:0 */ 1089 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 1090 P12_3_AUDIOSS0_RX_WS = 25, /* Digital Active - audioss[0].rx_ws:0 */ 1091 1092 /* P12.4 */ 1093 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1094 P12_4_AMUXA = 4, /* Analog mux bus A */ 1095 P12_4_AMUXB = 5, /* Analog mux bus B */ 1096 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1097 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1098 P12_4_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:0 */ 1099 P12_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:0 */ 1100 P12_4_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:0 */ 1101 P12_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:0 */ 1102 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 1103 P12_4_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:0 */ 1104 P12_4_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:2 */ 1105 P12_4_AUDIOSS0_RX_SDI = 25, /* Digital Active - audioss[0].rx_sdi:0 */ 1106 1107 /* P13.0 */ 1108 P13_0_GPIO = 0, /* GPIO controls 'out' */ 1109 P13_0_AMUXA = 4, /* Analog mux bus A */ 1110 P13_0_AMUXB = 5, /* Analog mux bus B */ 1111 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1112 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1113 P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 1114 P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ 1115 P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ 1116 P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ 1117 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 1118 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 1119 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 1120 P13_0_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:0 */ 1121 P13_0_AUDIOSS1_MCLK = 25, /* Digital Active - audioss[1].mclk:0 */ 1122 1123 /* P13.1 */ 1124 P13_1_GPIO = 0, /* GPIO controls 'out' */ 1125 P13_1_AMUXA = 4, /* Analog mux bus A */ 1126 P13_1_AMUXB = 5, /* Analog mux bus B */ 1127 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1128 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1129 P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ 1130 P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 1131 P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ 1132 P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ 1133 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 1134 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 1135 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 1136 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 1137 P13_1_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:0 */ 1138 P13_1_AUDIOSS1_TX_SCK = 25, /* Digital Active - audioss[1].tx_sck:0 */ 1139 1140 /* P13.2 */ 1141 P13_2_GPIO = 0, /* GPIO controls 'out' */ 1142 P13_2_AMUXA = 4, /* Analog mux bus A */ 1143 P13_2_AMUXB = 5, /* Analog mux bus B */ 1144 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1145 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1146 P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 1147 P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ 1148 P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ 1149 P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ 1150 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 1151 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 1152 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 1153 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 1154 P13_2_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:0 */ 1155 P13_2_AUDIOSS1_TX_WS = 25, /* Digital Active - audioss[1].tx_ws:0 */ 1156 1157 /* P13.3 */ 1158 P13_3_GPIO = 0, /* GPIO controls 'out' */ 1159 P13_3_AMUXA = 4, /* Analog mux bus A */ 1160 P13_3_AMUXB = 5, /* Analog mux bus B */ 1161 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1162 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1163 P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ 1164 P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 1165 P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ 1166 P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ 1167 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 1168 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 1169 P13_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:2 */ 1170 P13_3_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:0 */ 1171 P13_3_AUDIOSS1_TX_SDO = 25, /* Digital Active - audioss[1].tx_sdo:0 */ 1172 1173 /* P13.4 */ 1174 P13_4_GPIO = 0, /* GPIO controls 'out' */ 1175 P13_4_AMUXA = 4, /* Analog mux bus A */ 1176 P13_4_AMUXB = 5, /* Analog mux bus B */ 1177 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1178 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1179 P13_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ 1180 P13_4_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:0 */ 1181 P13_4_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:0 */ 1182 P13_4_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:0 */ 1183 P13_4_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:1 */ 1184 P13_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:2 */ 1185 P13_4_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:0 */ 1186 P13_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:0 */ 1187 P13_4_AUDIOSS1_CLK_I2S_IF = 25, /* Digital Active - audioss[1].clk_i2s_if:0 */ 1188 1189 /* P13.5 */ 1190 P13_5_GPIO = 0, /* GPIO controls 'out' */ 1191 P13_5_AMUXA = 4, /* Analog mux bus A */ 1192 P13_5_AMUXB = 5, /* Analog mux bus B */ 1193 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1194 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1195 P13_5_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:0 */ 1196 P13_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ 1197 P13_5_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:0 */ 1198 P13_5_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:0 */ 1199 P13_5_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:1 */ 1200 P13_5_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:0 */ 1201 P13_5_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:0 */ 1202 P13_5_AUDIOSS1_RX_SCK = 25, /* Digital Active - audioss[1].rx_sck:0 */ 1203 1204 /* P13.6 */ 1205 P13_6_GPIO = 0, /* GPIO controls 'out' */ 1206 P13_6_AMUXA = 4, /* Analog mux bus A */ 1207 P13_6_AMUXB = 5, /* Analog mux bus B */ 1208 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1209 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1210 P13_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ 1211 P13_6_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:0 */ 1212 P13_6_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:0 */ 1213 P13_6_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:0 */ 1214 P13_6_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:1 */ 1215 P13_6_SCB3_SPI_SELECT3 = 21, /* Digital Active - scb[3].spi_select3:0 */ 1216 P13_6_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:0 */ 1217 P13_6_AUDIOSS1_RX_WS = 25, /* Digital Active - audioss[1].rx_ws:0 */ 1218 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 1219 1220 /* P13.7 */ 1221 P13_7_GPIO = 0, /* GPIO controls 'out' */ 1222 P13_7_AMUXA = 4, /* Analog mux bus A */ 1223 P13_7_AMUXB = 5, /* Analog mux bus B */ 1224 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1225 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1226 P13_7_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:0 */ 1227 P13_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ 1228 P13_7_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:0 */ 1229 P13_7_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:0 */ 1230 P13_7_TCPWM0_LINE_COMPL517 = 16, /* Digital Active - tcpwm[0].line_compl[517]:1 */ 1231 P13_7_AUDIOSS1_RX_SDI = 25, /* Digital Active - audioss[1].rx_sdi:0 */ 1232 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 1233 1234 /* P14.0 */ 1235 P14_0_GPIO = 0, /* GPIO controls 'out' */ 1236 P14_0_AMUXA = 4, /* Analog mux bus A */ 1237 P14_0_AMUXB = 5, /* Analog mux bus B */ 1238 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1239 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1240 P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ 1241 P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ 1242 P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ 1243 P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ 1244 P14_0_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:1 */ 1245 P14_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:0 */ 1246 P14_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:0 */ 1247 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 1248 P14_0_AUDIOSS2_MCLK = 25, /* Digital Active - audioss[2].mclk:0 */ 1249 1250 /* P14.1 */ 1251 P14_1_GPIO = 0, /* GPIO controls 'out' */ 1252 P14_1_AMUXA = 4, /* Analog mux bus A */ 1253 P14_1_AMUXB = 5, /* Analog mux bus B */ 1254 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1255 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1256 P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ 1257 P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ 1258 P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ 1259 P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ 1260 P14_1_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:1 */ 1261 P14_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:0 */ 1262 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 1263 P14_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:0 */ 1264 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 1265 P14_1_AUDIOSS2_TX_SCK = 25, /* Digital Active - audioss[2].tx_sck:0 */ 1266 1267 /* P18.0 */ 1268 P18_0_GPIO = 0, /* GPIO controls 'out' */ 1269 P18_0_AMUXA = 4, /* Analog mux bus A */ 1270 P18_0_AMUXB = 5, /* Analog mux bus B */ 1271 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1272 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1273 P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ 1274 P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 1275 P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ 1276 P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ 1277 P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ 1278 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 1279 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 1280 P18_0_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:1 */ 1281 P18_0_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk:0 */ 1282 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 1283 1284 /* P18.1 */ 1285 P18_1_GPIO = 0, /* GPIO controls 'out' */ 1286 P18_1_AMUXA = 4, /* Analog mux bus A */ 1287 P18_1_AMUXB = 5, /* Analog mux bus B */ 1288 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1289 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1290 P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ 1291 P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 1292 P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ 1293 P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ 1294 P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ 1295 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 1296 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 1297 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 1298 P18_1_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:1 */ 1299 P18_1_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl:0 */ 1300 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 1301 1302 /* P18.2 */ 1303 P18_2_GPIO = 0, /* GPIO controls 'out' */ 1304 P18_2_AMUXA = 4, /* Analog mux bus A */ 1305 P18_2_AMUXB = 5, /* Analog mux bus B */ 1306 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1307 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1308 P18_2_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:1 */ 1309 P18_2_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 1310 P18_2_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:1 */ 1311 P18_2_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:1 */ 1312 P18_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:0 */ 1313 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 1314 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 1315 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 1316 P18_2_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:1 */ 1317 P18_2_ETH0_TX_ER = 24, /* Digital Active - eth[0].tx_er:0 */ 1318 1319 /* P18.3 */ 1320 P18_3_GPIO = 0, /* GPIO controls 'out' */ 1321 P18_3_AMUXA = 4, /* Analog mux bus A */ 1322 P18_3_AMUXB = 5, /* Analog mux bus B */ 1323 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1324 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1325 P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ 1326 P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ 1327 P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ 1328 P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ 1329 P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ 1330 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 1331 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 1332 P18_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:2 */ 1333 P18_3_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk:0 */ 1334 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 1335 1336 /* P18.4 */ 1337 P18_4_GPIO = 0, /* GPIO controls 'out' */ 1338 P18_4_AMUXA = 4, /* Analog mux bus A */ 1339 P18_4_AMUXB = 5, /* Analog mux bus B */ 1340 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1341 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1342 P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ 1343 P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ 1344 P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ 1345 P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ 1346 P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ 1347 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 1348 P18_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:2 */ 1349 P18_4_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0]:0 */ 1350 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1351 1352 /* P18.5 */ 1353 P18_5_GPIO = 0, /* GPIO controls 'out' */ 1354 P18_5_AMUXA = 4, /* Analog mux bus A */ 1355 P18_5_AMUXB = 5, /* Analog mux bus B */ 1356 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1357 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1358 P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ 1359 P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ 1360 P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ 1361 P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ 1362 P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ 1363 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 1364 P18_5_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1]:0 */ 1365 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1366 1367 /* P18.6 */ 1368 P18_6_GPIO = 0, /* GPIO controls 'out' */ 1369 P18_6_AMUXA = 4, /* Analog mux bus A */ 1370 P18_6_AMUXB = 5, /* Analog mux bus B */ 1371 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1372 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1373 P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ 1374 P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ 1375 P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ 1376 P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ 1377 P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ 1378 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 1379 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 1380 P18_6_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2]:0 */ 1381 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1382 1383 /* P18.7 */ 1384 P18_7_GPIO = 0, /* GPIO controls 'out' */ 1385 P18_7_AMUXA = 4, /* Analog mux bus A */ 1386 P18_7_AMUXB = 5, /* Analog mux bus B */ 1387 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1388 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1389 P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ 1390 P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ 1391 P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ 1392 P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ 1393 P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ 1394 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 1395 P18_7_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3]:0 */ 1396 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1397 1398 /* P19.0 */ 1399 P19_0_GPIO = 0, /* GPIO controls 'out' */ 1400 P19_0_AMUXA = 4, /* Analog mux bus A */ 1401 P19_0_AMUXB = 5, /* Analog mux bus B */ 1402 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1403 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1404 P19_0_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:2 */ 1405 P19_0_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:1 */ 1406 P19_0_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:2 */ 1407 P19_0_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:1 */ 1408 P19_0_TCPWM0_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536]:0 */ 1409 P19_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:1 */ 1410 P19_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:1 */ 1411 P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ 1412 P19_0_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0]:0 */ 1413 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 1414 1415 /* P19.1 */ 1416 P19_1_GPIO = 0, /* GPIO controls 'out' */ 1417 P19_1_AMUXA = 4, /* Analog mux bus A */ 1418 P19_1_AMUXB = 5, /* Analog mux bus B */ 1419 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1420 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1421 P19_1_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ 1422 P19_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 1423 P19_1_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:1 */ 1424 P19_1_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:2 */ 1425 P19_1_TCPWM0_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537]:0 */ 1426 P19_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:1 */ 1427 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 1428 P19_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:1 */ 1429 P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ 1430 P19_1_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1]:0 */ 1431 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 1432 1433 /* P19.2 */ 1434 P19_2_GPIO = 0, /* GPIO controls 'out' */ 1435 P19_2_AMUXA = 4, /* Analog mux bus A */ 1436 P19_2_AMUXB = 5, /* Analog mux bus B */ 1437 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1438 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1439 P19_2_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:2 */ 1440 P19_2_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:1 */ 1441 P19_2_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:2 */ 1442 P19_2_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:1 */ 1443 P19_2_TCPWM0_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539]:0 */ 1444 P19_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:1 */ 1445 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 1446 P19_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:1 */ 1447 P19_2_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2]:0 */ 1448 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 1449 1450 /* P19.3 */ 1451 P19_3_GPIO = 0, /* GPIO controls 'out' */ 1452 P19_3_AMUXA = 4, /* Analog mux bus A */ 1453 P19_3_AMUXB = 5, /* Analog mux bus B */ 1454 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1455 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1456 P19_3_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:2 */ 1457 P19_3_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:2 */ 1458 P19_3_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:2 */ 1459 P19_3_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:2 */ 1460 P19_3_TCPWM0_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540]:0 */ 1461 P19_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:1 */ 1462 P19_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:1 */ 1463 P19_3_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3]:0 */ 1464 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 1465 1466 /* P21.0 */ 1467 P21_0_GPIO = 0, /* GPIO controls 'out' */ 1468 P21_0_AMUXA = 4, /* Analog mux bus A */ 1469 P21_0_AMUXB = 5, /* Analog mux bus B */ 1470 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1471 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1472 P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ 1473 P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ 1474 P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ 1475 P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ 1476 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 1477 1478 /* P21.1 */ 1479 P21_1_GPIO = 0, /* GPIO controls 'out' */ 1480 P21_1_AMUXA = 4, /* Analog mux bus A */ 1481 P21_1_AMUXB = 5, /* Analog mux bus B */ 1482 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1483 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1484 P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ 1485 P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ 1486 P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ 1487 P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ 1488 1489 /* P21.2 */ 1490 P21_2_GPIO = 0, /* GPIO controls 'out' */ 1491 P21_2_AMUXA = 4, /* Analog mux bus A */ 1492 P21_2_AMUXB = 5, /* Analog mux bus B */ 1493 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1494 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1495 P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ 1496 P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ 1497 P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ 1498 P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ 1499 P21_2_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:0 */ 1500 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 1501 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1502 1503 /* P21.3 */ 1504 P21_3_GPIO = 0, /* GPIO controls 'out' */ 1505 P21_3_AMUXA = 4, /* Analog mux bus A */ 1506 P21_3_AMUXB = 5, /* Analog mux bus B */ 1507 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1508 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1509 P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ 1510 P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ 1511 P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ 1512 P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ 1513 1514 /* P21.5 */ 1515 P21_5_GPIO = 0, /* GPIO controls 'out' */ 1516 P21_5_AMUXA = 4, /* Analog mux bus A */ 1517 P21_5_AMUXB = 5, /* Analog mux bus B */ 1518 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1519 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1520 P21_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:1 */ 1521 P21_5_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:1 */ 1522 P21_5_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:1 */ 1523 P21_5_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:1 */ 1524 P21_5_TCPWM0_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ 1525 P21_5_TCPWM0_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ 1526 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 1527 P21_5_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 1528 P21_5_TCPWM0_LINE34 = 22, /* Digital Active - tcpwm[0].line[34]:1 */ 1529 P21_5_TCPWM0_LINE_COMPL35 = 23, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 1530 P21_5_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl:0 */ 1531 P21_5_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1532 1533 /* P22.1 */ 1534 P22_1_GPIO = 0, /* GPIO controls 'out' */ 1535 P22_1_AMUXA = 4, /* Analog mux bus A */ 1536 P22_1_AMUXB = 5, /* Analog mux bus B */ 1537 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1538 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1539 P22_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ 1540 P22_1_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ 1541 P22_1_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:1 */ 1542 P22_1_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:1 */ 1543 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 1544 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 1545 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 1546 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 1547 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1548 1549 /* P22.2 */ 1550 P22_2_GPIO = 0, /* GPIO controls 'out' */ 1551 P22_2_AMUXA = 4, /* Analog mux bus A */ 1552 P22_2_AMUXB = 5, /* Analog mux bus B */ 1553 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1554 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1555 P22_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:1 */ 1556 P22_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:1 */ 1557 P22_2_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:1 */ 1558 P22_2_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:1 */ 1559 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 1560 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 1561 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 1562 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1563 1564 /* P22.3 */ 1565 P22_3_GPIO = 0, /* GPIO controls 'out' */ 1566 P22_3_AMUXA = 4, /* Analog mux bus A */ 1567 P22_3_AMUXB = 5, /* Analog mux bus B */ 1568 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1569 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1570 P22_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:1 */ 1571 P22_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:1 */ 1572 P22_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:1 */ 1573 P22_3_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:1 */ 1574 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 1575 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 1576 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1577 1578 /* P23.3 */ 1579 P23_3_GPIO = 0, /* GPIO controls 'out' */ 1580 P23_3_AMUXA = 4, /* Analog mux bus A */ 1581 P23_3_AMUXB = 5, /* Analog mux bus B */ 1582 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1583 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1584 P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ 1585 P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ 1586 P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ 1587 P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ 1588 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 1589 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 1590 P23_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:2 */ 1591 P23_3_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk:0 */ 1592 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 1593 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 1594 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1595 1596 /* P23.4 */ 1597 P23_4_GPIO = 0, /* GPIO controls 'out' */ 1598 P23_4_AMUXA = 4, /* Analog mux bus A */ 1599 P23_4_AMUXB = 5, /* Analog mux bus B */ 1600 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1601 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1602 P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 1603 P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ 1604 P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ 1605 P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ 1606 P23_4_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:2 */ 1607 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 1608 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 1609 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 1610 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 1611 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1612 1613 /* P23.5 */ 1614 P23_5_GPIO = 0, /* GPIO controls 'out' */ 1615 P23_5_AMUXA = 4, /* Analog mux bus A */ 1616 P23_5_AMUXB = 5, /* Analog mux bus B */ 1617 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1618 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1619 P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 1620 P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 1621 P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ 1622 P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ 1623 P23_5_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:2 */ 1624 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 1625 P23_5_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:0 */ 1626 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 1627 1628 /* P23.6 */ 1629 P23_6_GPIO = 0, /* GPIO controls 'out' */ 1630 P23_6_AMUXA = 4, /* Analog mux bus A */ 1631 P23_6_AMUXB = 5, /* Analog mux bus B */ 1632 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1633 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1634 P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 1635 P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 1636 P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ 1637 P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ 1638 P23_6_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:2 */ 1639 P23_6_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:0 */ 1640 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 1641 1642 /* P23.7 */ 1643 P23_7_GPIO = 0, /* GPIO controls 'out' */ 1644 P23_7_AMUXA = 4, /* Analog mux bus A */ 1645 P23_7_AMUXB = 5, /* Analog mux bus B */ 1646 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1647 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1648 P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 1649 P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 1650 P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ 1651 P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ 1652 P23_7_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:2 */ 1653 P23_7_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:1 */ 1654 P23_7_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:0 */ 1655 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 1656 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 1657 P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1658 } en_hsiom_sel_t; 1659 1660 #endif /* _GPIO_XMC7100_100_TEQFP_H_ */ 1661 1662 1663 /* [] END OF FILE */ 1664
