1 /***************************************************************************//** 2 * \file cyip_dw.h 3 * 4 * \brief 5 * DW IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_DW_H_ 28 #define _CYIP_DW_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * DW 34 *******************************************************************************/ 35 36 #define DW_CH_STRUCT_SECTION_SIZE 0x00000040UL 37 #define DW_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief DW channel structure (DW_CH_STRUCT) 41 */ 42 typedef struct { 43 __IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */ 44 __IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */ 45 __IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */ 46 __IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */ 47 __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */ 48 __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */ 49 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */ 50 __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */ 51 __IOM uint32_t SRAM_DATA0; /*!< 0x00000020 SRAM data 0 */ 52 __IOM uint32_t SRAM_DATA1; /*!< 0x00000024 SRAM data 1 */ 53 __IOM uint32_t TR_CMD; /*!< 0x00000028 Channel software trigger */ 54 __IM uint32_t RESERVED[5]; 55 } DW_CH_STRUCT_Type; /*!< Size = 64 (0x40) */ 56 57 /** 58 * \brief DW-0/1 (DW) 59 */ 60 typedef struct { 61 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 62 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 63 __IM uint32_t RESERVED[6]; 64 __IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */ 65 __IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */ 66 __IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */ 67 __IM uint32_t RESERVED1; 68 __IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */ 69 __IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */ 70 __IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */ 71 __IM uint32_t RESERVED2; 72 __IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */ 73 __IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */ 74 __IM uint32_t RESERVED3[14]; 75 __IOM uint32_t ECC_CTL; /*!< 0x00000080 ECC control */ 76 __IM uint32_t RESERVED4[31]; 77 __IOM uint32_t CRC_CTL; /*!< 0x00000100 CRC control */ 78 __IM uint32_t RESERVED5[3]; 79 __IOM uint32_t CRC_DATA_CTL; /*!< 0x00000110 CRC data control */ 80 __IM uint32_t RESERVED6[3]; 81 __IOM uint32_t CRC_POL_CTL; /*!< 0x00000120 CRC polynomial control */ 82 __IM uint32_t RESERVED7[3]; 83 __IOM uint32_t CRC_LFSR_CTL; /*!< 0x00000130 CRC LFSR control */ 84 __IM uint32_t RESERVED8[3]; 85 __IOM uint32_t CRC_REM_CTL; /*!< 0x00000140 CRC remainder control */ 86 __IM uint32_t RESERVED9; 87 __IM uint32_t CRC_REM_RESULT; /*!< 0x00000148 CRC remainder result */ 88 __IM uint32_t RESERVED10[8109]; 89 DW_CH_STRUCT_Type CH_STRUCT[512]; /*!< 0x00008000 DW channel structure */ 90 } DW_Type; /*!< Size = 65536 (0x10000) */ 91 92 93 /* DW_CH_STRUCT.CH_CTL */ 94 #define DW_CH_STRUCT_CH_CTL_P_Pos 0UL 95 #define DW_CH_STRUCT_CH_CTL_P_Msk 0x1UL 96 #define DW_CH_STRUCT_CH_CTL_NS_Pos 1UL 97 #define DW_CH_STRUCT_CH_CTL_NS_Msk 0x2UL 98 #define DW_CH_STRUCT_CH_CTL_B_Pos 2UL 99 #define DW_CH_STRUCT_CH_CTL_B_Msk 0x4UL 100 #define DW_CH_STRUCT_CH_CTL_PC_Pos 4UL 101 #define DW_CH_STRUCT_CH_CTL_PC_Msk 0xF0UL 102 #define DW_CH_STRUCT_CH_CTL_PRIO_Pos 8UL 103 #define DW_CH_STRUCT_CH_CTL_PRIO_Msk 0x300UL 104 #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos 11UL 105 #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk 0x800UL 106 #define DW_CH_STRUCT_CH_CTL_ENABLED_Pos 31UL 107 #define DW_CH_STRUCT_CH_CTL_ENABLED_Msk 0x80000000UL 108 /* DW_CH_STRUCT.CH_STATUS */ 109 #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos 0UL 110 #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk 0xFUL 111 #define DW_CH_STRUCT_CH_STATUS_PENDING_Pos 31UL 112 #define DW_CH_STRUCT_CH_STATUS_PENDING_Msk 0x80000000UL 113 /* DW_CH_STRUCT.CH_IDX */ 114 #define DW_CH_STRUCT_CH_IDX_X_IDX_Pos 0UL 115 #define DW_CH_STRUCT_CH_IDX_X_IDX_Msk 0xFFUL 116 #define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos 8UL 117 #define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk 0xFF00UL 118 /* DW_CH_STRUCT.CH_CURR_PTR */ 119 #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos 2UL 120 #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL 121 /* DW_CH_STRUCT.INTR */ 122 #define DW_CH_STRUCT_INTR_CH_Pos 0UL 123 #define DW_CH_STRUCT_INTR_CH_Msk 0x1UL 124 /* DW_CH_STRUCT.INTR_SET */ 125 #define DW_CH_STRUCT_INTR_SET_CH_Pos 0UL 126 #define DW_CH_STRUCT_INTR_SET_CH_Msk 0x1UL 127 /* DW_CH_STRUCT.INTR_MASK */ 128 #define DW_CH_STRUCT_INTR_MASK_CH_Pos 0UL 129 #define DW_CH_STRUCT_INTR_MASK_CH_Msk 0x1UL 130 /* DW_CH_STRUCT.INTR_MASKED */ 131 #define DW_CH_STRUCT_INTR_MASKED_CH_Pos 0UL 132 #define DW_CH_STRUCT_INTR_MASKED_CH_Msk 0x1UL 133 /* DW_CH_STRUCT.SRAM_DATA0 */ 134 #define DW_CH_STRUCT_SRAM_DATA0_DATA_Pos 0UL 135 #define DW_CH_STRUCT_SRAM_DATA0_DATA_Msk 0xFFFFFFFFUL 136 /* DW_CH_STRUCT.SRAM_DATA1 */ 137 #define DW_CH_STRUCT_SRAM_DATA1_DATA_Pos 0UL 138 #define DW_CH_STRUCT_SRAM_DATA1_DATA_Msk 0xFFFFFFFFUL 139 /* DW_CH_STRUCT.TR_CMD */ 140 #define DW_CH_STRUCT_TR_CMD_ACTIVATE_Pos 0UL 141 #define DW_CH_STRUCT_TR_CMD_ACTIVATE_Msk 0x1UL 142 143 144 /* DW.CTL */ 145 #define DW_CTL_ECC_EN_Pos 0UL 146 #define DW_CTL_ECC_EN_Msk 0x1UL 147 #define DW_CTL_ECC_INJ_EN_Pos 1UL 148 #define DW_CTL_ECC_INJ_EN_Msk 0x2UL 149 #define DW_CTL_ENABLED_Pos 31UL 150 #define DW_CTL_ENABLED_Msk 0x80000000UL 151 /* DW.STATUS */ 152 #define DW_STATUS_P_Pos 0UL 153 #define DW_STATUS_P_Msk 0x1UL 154 #define DW_STATUS_NS_Pos 1UL 155 #define DW_STATUS_NS_Msk 0x2UL 156 #define DW_STATUS_B_Pos 2UL 157 #define DW_STATUS_B_Msk 0x4UL 158 #define DW_STATUS_PC_Pos 4UL 159 #define DW_STATUS_PC_Msk 0xF0UL 160 #define DW_STATUS_PRIO_Pos 8UL 161 #define DW_STATUS_PRIO_Msk 0x300UL 162 #define DW_STATUS_PREEMPTABLE_Pos 11UL 163 #define DW_STATUS_PREEMPTABLE_Msk 0x800UL 164 #define DW_STATUS_CH_IDX_Pos 16UL 165 #define DW_STATUS_CH_IDX_Msk 0x1FF0000UL 166 #define DW_STATUS_STATE_Pos 28UL 167 #define DW_STATUS_STATE_Msk 0x70000000UL 168 #define DW_STATUS_ACTIVE_Pos 31UL 169 #define DW_STATUS_ACTIVE_Msk 0x80000000UL 170 /* DW.ACT_DESCR_CTL */ 171 #define DW_ACT_DESCR_CTL_DATA_Pos 0UL 172 #define DW_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL 173 /* DW.ACT_DESCR_SRC */ 174 #define DW_ACT_DESCR_SRC_DATA_Pos 0UL 175 #define DW_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL 176 /* DW.ACT_DESCR_DST */ 177 #define DW_ACT_DESCR_DST_DATA_Pos 0UL 178 #define DW_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL 179 /* DW.ACT_DESCR_X_CTL */ 180 #define DW_ACT_DESCR_X_CTL_DATA_Pos 0UL 181 #define DW_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL 182 /* DW.ACT_DESCR_Y_CTL */ 183 #define DW_ACT_DESCR_Y_CTL_DATA_Pos 0UL 184 #define DW_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL 185 /* DW.ACT_DESCR_NEXT_PTR */ 186 #define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL 187 #define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL 188 /* DW.ACT_SRC */ 189 #define DW_ACT_SRC_SRC_ADDR_Pos 0UL 190 #define DW_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL 191 /* DW.ACT_DST */ 192 #define DW_ACT_DST_DST_ADDR_Pos 0UL 193 #define DW_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL 194 /* DW.ECC_CTL */ 195 #define DW_ECC_CTL_WORD_ADDR_Pos 0UL 196 #define DW_ECC_CTL_WORD_ADDR_Msk 0x3FFUL 197 #define DW_ECC_CTL_PARITY_Pos 25UL 198 #define DW_ECC_CTL_PARITY_Msk 0xFE000000UL 199 /* DW.CRC_CTL */ 200 #define DW_CRC_CTL_DATA_REVERSE_Pos 0UL 201 #define DW_CRC_CTL_DATA_REVERSE_Msk 0x1UL 202 #define DW_CRC_CTL_REM_REVERSE_Pos 8UL 203 #define DW_CRC_CTL_REM_REVERSE_Msk 0x100UL 204 /* DW.CRC_DATA_CTL */ 205 #define DW_CRC_DATA_CTL_DATA_XOR_Pos 0UL 206 #define DW_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL 207 /* DW.CRC_POL_CTL */ 208 #define DW_CRC_POL_CTL_POLYNOMIAL_Pos 0UL 209 #define DW_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL 210 /* DW.CRC_LFSR_CTL */ 211 #define DW_CRC_LFSR_CTL_LFSR32_Pos 0UL 212 #define DW_CRC_LFSR_CTL_LFSR32_Msk 0xFFFFFFFFUL 213 /* DW.CRC_REM_CTL */ 214 #define DW_CRC_REM_CTL_REM_XOR_Pos 0UL 215 #define DW_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL 216 /* DW.CRC_REM_RESULT */ 217 #define DW_CRC_REM_RESULT_REM_Pos 0UL 218 #define DW_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL 219 220 221 #endif /* _CYIP_DW_H_ */ 222 223 224 /* [] END OF FILE */ 225
