1 /***************************************************************************//** 2 * \file cyip_pass_v2.h 3 * 4 * \brief 5 * PASS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PASS_V2_H_ 28 #define _CYIP_PASS_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PASS 34 *******************************************************************************/ 35 36 #define PASS_TIMER_V2_SECTION_SIZE 0x00000100UL 37 #define PASS_LPOSC_V2_SECTION_SIZE 0x00000100UL 38 #define PASS_FIFO_V2_SECTION_SIZE 0x00000100UL 39 #define PASS_AREFV2_V2_SECTION_SIZE 0x00000100UL 40 #define PASS_V2_SECTION_SIZE 0x00010000UL 41 42 /** 43 * \brief Programmable Analog Subsystem (PASS_TIMER) 44 */ 45 typedef struct { 46 __IOM uint32_t CTRL; /*!< 0x00000000 Timer trigger control register */ 47 __IOM uint32_t CONFIG; /*!< 0x00000004 Timer trigger configuration register */ 48 __IOM uint32_t PERIOD; /*!< 0x00000008 Timer trigger period register */ 49 __IM uint32_t RESERVED[61]; 50 } PASS_TIMER_V2_Type; /*!< Size = 256 (0x100) */ 51 52 /** 53 * \brief LPOSC configuration (PASS_LPOSC) 54 */ 55 typedef struct { 56 __IOM uint32_t CTRL; /*!< 0x00000000 Low Power Oscillator control */ 57 __IOM uint32_t CONFIG; /*!< 0x00000004 Low Power Oscillator configuration register */ 58 __IOM uint32_t ADFT; /*!< 0x00000008 Retention, Hidden */ 59 __IM uint32_t RESERVED[61]; 60 } PASS_LPOSC_V2_Type; /*!< Size = 256 (0x100) */ 61 62 /** 63 * \brief FIFO configuration (PASS_FIFO) 64 */ 65 typedef struct { 66 __IOM uint32_t CTRL; /*!< 0x00000000 FIFO control register */ 67 __IOM uint32_t CONFIG; /*!< 0x00000004 FIFO configuration register */ 68 __IOM uint32_t CLEAR; /*!< 0x00000008 FIFO clear register */ 69 __IOM uint32_t LEVEL; /*!< 0x0000000C FIFO level register */ 70 __IM uint32_t USED; /*!< 0x00000010 FIFO used register */ 71 __IM uint32_t STATUS; /*!< 0x00000014 FIFO status register */ 72 __IM uint32_t RD_DATA; /*!< 0x00000018 FIFO read data register */ 73 __IM uint32_t RESERVED; 74 __IOM uint32_t INTR; /*!< 0x00000020 Interrupt register */ 75 __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt set register */ 76 __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt mask register */ 77 __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt masked register */ 78 __IM uint32_t RESERVED1[52]; 79 } PASS_FIFO_V2_Type; /*!< Size = 256 (0x100) */ 80 81 /** 82 * \brief AREF configuration (PASS_AREFV2) 83 */ 84 typedef struct { 85 __IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */ 86 __IM uint32_t RESERVED[63]; 87 } PASS_AREFV2_V2_Type; /*!< Size = 256 (0x100) */ 88 89 /** 90 * \brief PASS top-level MMIO (AREF, LPOSC, FIFO, INTR, Trigger) (PASS) 91 */ 92 typedef struct { 93 __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */ 94 __IM uint32_t RESERVED[3]; 95 __IOM uint32_t DPSLP_CLOCK_SEL; /*!< 0x00000010 Deepsleep clock select */ 96 __IOM uint32_t ANA_PWR_CFG; /*!< 0x00000014 Analog power configuration */ 97 __IM uint32_t RESERVED1[2]; 98 __IOM uint32_t CTBM_CLOCK_SEL[2]; /*!< 0x00000020 Clock select for CTBm */ 99 __IM uint32_t RESERVED2[2]; 100 __IOM uint32_t SAR_DPSLP_CTRL[2]; /*!< 0x00000030 Deepsleep control for SARv3 */ 101 __IM uint32_t RESERVED3[2]; 102 __IOM uint32_t SAR_CLOCK_SEL[2]; /*!< 0x00000040 Clock select for SARv3 */ 103 __IM uint32_t RESERVED4[2]; 104 __IM uint32_t SAR_TR_SCAN_CNT_STATUS[2]; /*!< 0x00000050 SAR trigger scan control status */ 105 __IM uint32_t RESERVED5[2]; 106 __IOM uint32_t SAR_TR_SCAN_CNT; /*!< 0x00000060 SAR trigger scan control */ 107 __IOM uint32_t SAR_OVR_CTRL; /*!< 0x00000064 SAR HW trigger override */ 108 __IOM uint32_t SAR_SIMULT_CTRL; /*!< 0x00000068 SAR simultaneous trigger control */ 109 __IOM uint32_t SAR_SIMULT_FW_START_CTRL; /*!< 0x0000006C SAR simultaneous start control */ 110 __IOM uint32_t SAR_TR_OUT_CTRL; /*!< 0x00000070 SAR trigger out control */ 111 __IM uint32_t RESERVED6[35]; 112 PASS_TIMER_V2_Type TIMER; /*!< 0x00000100 Programmable Analog Subsystem */ 113 PASS_LPOSC_V2_Type LPOSC; /*!< 0x00000200 LPOSC configuration */ 114 PASS_FIFO_V2_Type FIFO[2]; /*!< 0x00000300 FIFO configuration */ 115 __IM uint32_t RESERVED7[576]; 116 PASS_AREFV2_V2_Type AREFV2; /*!< 0x00000E00 AREF configuration */ 117 __IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */ 118 __IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */ 119 __IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */ 120 __IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */ 121 __IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 VREF Trim bits */ 122 __IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */ 123 __IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */ 124 __IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */ 125 } PASS_V2_Type; /*!< Size = 3872 (0xF20) */ 126 127 128 /* PASS_TIMER.CTRL */ 129 #define PASS_TIMER_V2_CTRL_ENABLED_Pos 31UL 130 #define PASS_TIMER_V2_CTRL_ENABLED_Msk 0x80000000UL 131 /* PASS_TIMER.CONFIG */ 132 #define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Pos 0UL 133 #define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Msk 0x3UL 134 /* PASS_TIMER.PERIOD */ 135 #define PASS_TIMER_V2_PERIOD_PER_VAL_Pos 0UL 136 #define PASS_TIMER_V2_PERIOD_PER_VAL_Msk 0xFFFFUL 137 138 139 /* PASS_LPOSC.CTRL */ 140 #define PASS_LPOSC_V2_CTRL_ENABLED_Pos 31UL 141 #define PASS_LPOSC_V2_CTRL_ENABLED_Msk 0x80000000UL 142 /* PASS_LPOSC.CONFIG */ 143 #define PASS_LPOSC_V2_CONFIG_DEEPSLEEP_MODE_Pos 0UL 144 #define PASS_LPOSC_V2_CONFIG_DEEPSLEEP_MODE_Msk 0x1UL 145 /* PASS_LPOSC.ADFT */ 146 #define PASS_LPOSC_V2_ADFT_ADFT_SEL_Pos 0UL 147 #define PASS_LPOSC_V2_ADFT_ADFT_SEL_Msk 0x3UL 148 149 150 /* PASS_FIFO.CTRL */ 151 #define PASS_FIFO_V2_CTRL_ENABLED_Pos 31UL 152 #define PASS_FIFO_V2_CTRL_ENABLED_Msk 0x80000000UL 153 /* PASS_FIFO.CONFIG */ 154 #define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Pos 0UL 155 #define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Msk 0x1UL 156 #define PASS_FIFO_V2_CONFIG_CHAIN_TO_NXT_Pos 1UL 157 #define PASS_FIFO_V2_CONFIG_CHAIN_TO_NXT_Msk 0x2UL 158 #define PASS_FIFO_V2_CONFIG_TR_INTR_CLR_RD_EN_Pos 2UL 159 #define PASS_FIFO_V2_CONFIG_TR_INTR_CLR_RD_EN_Msk 0x4UL 160 /* PASS_FIFO.CLEAR */ 161 #define PASS_FIFO_V2_CLEAR_CLEAR_Pos 0UL 162 #define PASS_FIFO_V2_CLEAR_CLEAR_Msk 0x1UL 163 /* PASS_FIFO.LEVEL */ 164 #define PASS_FIFO_V2_LEVEL_LEVEL_Pos 0UL 165 #define PASS_FIFO_V2_LEVEL_LEVEL_Msk 0xFFUL 166 /* PASS_FIFO.USED */ 167 #define PASS_FIFO_V2_USED_USED_Pos 0UL 168 #define PASS_FIFO_V2_USED_USED_Msk 0xFFUL 169 /* PASS_FIFO.STATUS */ 170 #define PASS_FIFO_V2_STATUS_RD_PTR_Pos 0UL 171 #define PASS_FIFO_V2_STATUS_RD_PTR_Msk 0xFFUL 172 #define PASS_FIFO_V2_STATUS_WR_PTR_Pos 8UL 173 #define PASS_FIFO_V2_STATUS_WR_PTR_Msk 0xFF00UL 174 /* PASS_FIFO.RD_DATA */ 175 #define PASS_FIFO_V2_RD_DATA_RESULT_Pos 0UL 176 #define PASS_FIFO_V2_RD_DATA_RESULT_Msk 0xFFFFUL 177 #define PASS_FIFO_V2_RD_DATA_CHAN_ID_Pos 16UL 178 #define PASS_FIFO_V2_RD_DATA_CHAN_ID_Msk 0xF0000UL 179 /* PASS_FIFO.INTR */ 180 #define PASS_FIFO_V2_INTR_FIFO_LEVEL_Pos 0UL 181 #define PASS_FIFO_V2_INTR_FIFO_LEVEL_Msk 0x1UL 182 #define PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Pos 1UL 183 #define PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Msk 0x2UL 184 #define PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Pos 2UL 185 #define PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Msk 0x4UL 186 /* PASS_FIFO.INTR_SET */ 187 #define PASS_FIFO_V2_INTR_SET_FIFO_LEVEL_Pos 0UL 188 #define PASS_FIFO_V2_INTR_SET_FIFO_LEVEL_Msk 0x1UL 189 #define PASS_FIFO_V2_INTR_SET_FIFO_OVERFLOW_Pos 1UL 190 #define PASS_FIFO_V2_INTR_SET_FIFO_OVERFLOW_Msk 0x2UL 191 #define PASS_FIFO_V2_INTR_SET_FIFO_UNDERFLOW_Pos 2UL 192 #define PASS_FIFO_V2_INTR_SET_FIFO_UNDERFLOW_Msk 0x4UL 193 /* PASS_FIFO.INTR_MASK */ 194 #define PASS_FIFO_V2_INTR_MASK_FIFO_LEVEL_Pos 0UL 195 #define PASS_FIFO_V2_INTR_MASK_FIFO_LEVEL_Msk 0x1UL 196 #define PASS_FIFO_V2_INTR_MASK_FIFO_OVERFLOW_Pos 1UL 197 #define PASS_FIFO_V2_INTR_MASK_FIFO_OVERFLOW_Msk 0x2UL 198 #define PASS_FIFO_V2_INTR_MASK_FIFO_UNDERFLOW_Pos 2UL 199 #define PASS_FIFO_V2_INTR_MASK_FIFO_UNDERFLOW_Msk 0x4UL 200 /* PASS_FIFO.INTR_MASKED */ 201 #define PASS_FIFO_V2_INTR_MASKED_FIFO_LEVEL_Pos 0UL 202 #define PASS_FIFO_V2_INTR_MASKED_FIFO_LEVEL_Msk 0x1UL 203 #define PASS_FIFO_V2_INTR_MASKED_FIFO_OVERFLOW_Pos 1UL 204 #define PASS_FIFO_V2_INTR_MASKED_FIFO_OVERFLOW_Msk 0x2UL 205 #define PASS_FIFO_V2_INTR_MASKED_FIFO_UNDERFLOW_Pos 2UL 206 #define PASS_FIFO_V2_INTR_MASKED_FIFO_UNDERFLOW_Msk 0x4UL 207 208 209 /* PASS_AREFV2.AREF_CTRL */ 210 #define PASS_AREFV2_V2_AREF_CTRL_AREF_MODE_Pos 0UL 211 #define PASS_AREFV2_V2_AREF_CTRL_AREF_MODE_Msk 0x1UL 212 #define PASS_AREFV2_V2_AREF_CTRL_AREF_BIAS_SCALE_Pos 2UL 213 #define PASS_AREFV2_V2_AREF_CTRL_AREF_BIAS_SCALE_Msk 0xCUL 214 #define PASS_AREFV2_V2_AREF_CTRL_AREF_RMB_Pos 4UL 215 #define PASS_AREFV2_V2_AREF_CTRL_AREF_RMB_Msk 0x70UL 216 #define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_SCALE_Pos 7UL 217 #define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_SCALE_Msk 0x80UL 218 #define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos 8UL 219 #define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk 0xFF00UL 220 #define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SEL_Pos 16UL 221 #define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SEL_Msk 0x10000UL 222 #define PASS_AREFV2_V2_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos 19UL 223 #define PASS_AREFV2_V2_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk 0x80000UL 224 #define PASS_AREFV2_V2_AREF_CTRL_VREF_SEL_Pos 20UL 225 #define PASS_AREFV2_V2_AREF_CTRL_VREF_SEL_Msk 0x300000UL 226 #define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_MODE_Pos 28UL 227 #define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_MODE_Msk 0x30000000UL 228 #define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_ON_Pos 30UL 229 #define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL 230 #define PASS_AREFV2_V2_AREF_CTRL_ENABLED_Pos 31UL 231 #define PASS_AREFV2_V2_AREF_CTRL_ENABLED_Msk 0x80000000UL 232 233 234 /* PASS.INTR_CAUSE */ 235 #define PASS_V2_INTR_CAUSE_CTB0_INT_Pos 0UL 236 #define PASS_V2_INTR_CAUSE_CTB0_INT_Msk 0x1UL 237 #define PASS_V2_INTR_CAUSE_CTB1_INT_Pos 1UL 238 #define PASS_V2_INTR_CAUSE_CTB1_INT_Msk 0x2UL 239 #define PASS_V2_INTR_CAUSE_CTB2_INT_Pos 2UL 240 #define PASS_V2_INTR_CAUSE_CTB2_INT_Msk 0x4UL 241 #define PASS_V2_INTR_CAUSE_CTB3_INT_Pos 3UL 242 #define PASS_V2_INTR_CAUSE_CTB3_INT_Msk 0x8UL 243 #define PASS_V2_INTR_CAUSE_CTDAC0_INT_Pos 4UL 244 #define PASS_V2_INTR_CAUSE_CTDAC0_INT_Msk 0x10UL 245 #define PASS_V2_INTR_CAUSE_CTDAC1_INT_Pos 5UL 246 #define PASS_V2_INTR_CAUSE_CTDAC1_INT_Msk 0x20UL 247 #define PASS_V2_INTR_CAUSE_CTDAC2_INT_Pos 6UL 248 #define PASS_V2_INTR_CAUSE_CTDAC2_INT_Msk 0x40UL 249 #define PASS_V2_INTR_CAUSE_CTDAC3_INT_Pos 7UL 250 #define PASS_V2_INTR_CAUSE_CTDAC3_INT_Msk 0x80UL 251 #define PASS_V2_INTR_CAUSE_SAR0_INT_Pos 8UL 252 #define PASS_V2_INTR_CAUSE_SAR0_INT_Msk 0x100UL 253 #define PASS_V2_INTR_CAUSE_SAR1_INT_Pos 9UL 254 #define PASS_V2_INTR_CAUSE_SAR1_INT_Msk 0x200UL 255 #define PASS_V2_INTR_CAUSE_SAR2_INT_Pos 10UL 256 #define PASS_V2_INTR_CAUSE_SAR2_INT_Msk 0x400UL 257 #define PASS_V2_INTR_CAUSE_SAR3_INT_Pos 11UL 258 #define PASS_V2_INTR_CAUSE_SAR3_INT_Msk 0x800UL 259 #define PASS_V2_INTR_CAUSE_FIFO0_INT_Pos 12UL 260 #define PASS_V2_INTR_CAUSE_FIFO0_INT_Msk 0x1000UL 261 #define PASS_V2_INTR_CAUSE_FIFO1_INT_Pos 13UL 262 #define PASS_V2_INTR_CAUSE_FIFO1_INT_Msk 0x2000UL 263 #define PASS_V2_INTR_CAUSE_FIFO2_INT_Pos 14UL 264 #define PASS_V2_INTR_CAUSE_FIFO2_INT_Msk 0x4000UL 265 #define PASS_V2_INTR_CAUSE_FIFO3_INT_Pos 15UL 266 #define PASS_V2_INTR_CAUSE_FIFO3_INT_Msk 0x8000UL 267 /* PASS.DPSLP_CLOCK_SEL */ 268 #define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Pos 0UL 269 #define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Msk 0x1UL 270 #define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Pos 4UL 271 #define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Msk 0x70UL 272 /* PASS.ANA_PWR_CFG */ 273 #define PASS_V2_ANA_PWR_CFG_PWR_UP_DELAY_Pos 0UL 274 #define PASS_V2_ANA_PWR_CFG_PWR_UP_DELAY_Msk 0xFFUL 275 #define PASS_V2_ANA_PWR_CFG_DUTY_CYCLE_SAR_ACT_EN_Pos 8UL 276 #define PASS_V2_ANA_PWR_CFG_DUTY_CYCLE_SAR_ACT_EN_Msk 0xF00UL 277 /* PASS.CTBM_CLOCK_SEL */ 278 #define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Pos 0UL 279 #define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Msk 0x1UL 280 /* PASS.SAR_DPSLP_CTRL */ 281 #define PASS_V2_SAR_DPSLP_CTRL_ENABLED_Pos 31UL 282 #define PASS_V2_SAR_DPSLP_CTRL_ENABLED_Msk 0x80000000UL 283 /* PASS.SAR_CLOCK_SEL */ 284 #define PASS_V2_SAR_CLOCK_SEL_CLOCK_SEL_Pos 30UL 285 #define PASS_V2_SAR_CLOCK_SEL_CLOCK_SEL_Msk 0x40000000UL 286 /* PASS.SAR_TR_SCAN_CNT_STATUS */ 287 #define PASS_V2_SAR_TR_SCAN_CNT_STATUS_SCAN_CNT_STATUS_Pos 0UL 288 #define PASS_V2_SAR_TR_SCAN_CNT_STATUS_SCAN_CNT_STATUS_Msk 0xFFUL 289 /* PASS.SAR_TR_SCAN_CNT */ 290 #define PASS_V2_SAR_TR_SCAN_CNT_SCAN_CNT_Pos 0UL 291 #define PASS_V2_SAR_TR_SCAN_CNT_SCAN_CNT_Msk 0xFFUL 292 /* PASS.SAR_OVR_CTRL */ 293 #define PASS_V2_SAR_OVR_CTRL_HW_TR_TIMER_SEL_Pos 0UL 294 #define PASS_V2_SAR_OVR_CTRL_HW_TR_TIMER_SEL_Msk 0xFUL 295 #define PASS_V2_SAR_OVR_CTRL_TR_SCAN_CNT_SEL_Pos 4UL 296 #define PASS_V2_SAR_OVR_CTRL_TR_SCAN_CNT_SEL_Msk 0xF0UL 297 #define PASS_V2_SAR_OVR_CTRL_EOS_INTR_SCAN_CNT_SEL_Pos 8UL 298 #define PASS_V2_SAR_OVR_CTRL_EOS_INTR_SCAN_CNT_SEL_Msk 0xF00UL 299 /* PASS.SAR_SIMULT_CTRL */ 300 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_EN_Pos 0UL 301 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_EN_Msk 0xFUL 302 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_SRC_Pos 4UL 303 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_SRC_Msk 0x30UL 304 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_TIMER_SEL_Pos 8UL 305 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_TIMER_SEL_Msk 0x100UL 306 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_LEVEL_Pos 18UL 307 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_LEVEL_Msk 0x40000UL 308 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_SYNC_TR_Pos 19UL 309 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_SYNC_TR_Msk 0x80000UL 310 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_TR_SCAN_CNT_SEL_Pos 20UL 311 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_TR_SCAN_CNT_SEL_Msk 0x100000UL 312 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_EOS_INTR_SCAN_CNT_SEL_Pos 21UL 313 #define PASS_V2_SAR_SIMULT_CTRL_SIMULT_EOS_INTR_SCAN_CNT_SEL_Msk 0x200000UL 314 /* PASS.SAR_SIMULT_FW_START_CTRL */ 315 #define PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER_Pos 0UL 316 #define PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER_Msk 0xFUL 317 #define PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS_Pos 16UL 318 #define PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS_Msk 0xF0000UL 319 /* PASS.SAR_TR_OUT_CTRL */ 320 #define PASS_V2_SAR_TR_OUT_CTRL_SAR0_TR_OUT_SEL_Pos 0UL 321 #define PASS_V2_SAR_TR_OUT_CTRL_SAR0_TR_OUT_SEL_Msk 0x1UL 322 #define PASS_V2_SAR_TR_OUT_CTRL_SAR1_TR_OUT_SEL_Pos 1UL 323 #define PASS_V2_SAR_TR_OUT_CTRL_SAR1_TR_OUT_SEL_Msk 0x2UL 324 #define PASS_V2_SAR_TR_OUT_CTRL_SAR2_TR_OUT_SEL_Pos 2UL 325 #define PASS_V2_SAR_TR_OUT_CTRL_SAR2_TR_OUT_SEL_Msk 0x4UL 326 #define PASS_V2_SAR_TR_OUT_CTRL_SAR3_TR_OUT_SEL_Pos 3UL 327 #define PASS_V2_SAR_TR_OUT_CTRL_SAR3_TR_OUT_SEL_Msk 0x8UL 328 /* PASS.VREF_TRIM0 */ 329 #define PASS_V2_VREF_TRIM0_VREF_ABS_TRIM_Pos 0UL 330 #define PASS_V2_VREF_TRIM0_VREF_ABS_TRIM_Msk 0xFFUL 331 /* PASS.VREF_TRIM1 */ 332 #define PASS_V2_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos 0UL 333 #define PASS_V2_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk 0xFFUL 334 /* PASS.VREF_TRIM2 */ 335 #define PASS_V2_VREF_TRIM2_VREF_CURV_TRIM_Pos 0UL 336 #define PASS_V2_VREF_TRIM2_VREF_CURV_TRIM_Msk 0xFFUL 337 /* PASS.VREF_TRIM3 */ 338 #define PASS_V2_VREF_TRIM3_VREF_ATTEN_TRIM_Pos 0UL 339 #define PASS_V2_VREF_TRIM3_VREF_ATTEN_TRIM_Msk 0xFUL 340 /* PASS.IZTAT_TRIM0 */ 341 #define PASS_V2_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos 0UL 342 #define PASS_V2_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk 0xFFUL 343 /* PASS.IZTAT_TRIM1 */ 344 #define PASS_V2_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos 0UL 345 #define PASS_V2_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk 0xFFUL 346 /* PASS.IPTAT_TRIM0 */ 347 #define PASS_V2_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos 0UL 348 #define PASS_V2_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk 0xFUL 349 #define PASS_V2_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos 4UL 350 #define PASS_V2_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk 0xF0UL 351 /* PASS.ICTAT_TRIM0 */ 352 #define PASS_V2_ICTAT_TRIM0_ICTAT_TRIM_Pos 0UL 353 #define PASS_V2_ICTAT_TRIM0_ICTAT_TRIM_Msk 0xFUL 354 355 356 #endif /* _CYIP_PASS_V2_H_ */ 357 358 359 /* [] END OF FILE */ 360
