1 /***************************************************************************//** 2 * \file gpio_psoc6_02_100_wlcsp.h 3 * 4 * \brief 5 * PSoC6_02 device GPIO header for 100-WLCSP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_02_100_WLCSP_H_ 28 #define _GPIO_PSOC6_02_100_WLCSP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_WLCSP 44 #define CY_GPIO_PIN_COUNT 100u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ADFT0_VDDD, 50 AMUXBUS_ANALOG_VDDA, 51 AMUXBUS_ANALOG_VDDD, 52 AMUXBUS_CSD0, 53 AMUXBUS_CSD1, 54 AMUXBUS_MAIN, 55 AMUXBUS_NOISY, 56 AMUXBUS_SAR, 57 AMUXBUS_VDDIO_1, 58 }; 59 60 /* AMUX Splitter Controls */ 61 typedef enum 62 { 63 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 64 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 65 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_NOISY; Right = AMUXBUS_CSD0 */ 66 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 67 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 69 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 70 AMUX_SPLIT_CTL_7 = 0x0007u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 71 } cy_en_amux_split_t; 72 73 /* Port List */ 74 /* PORT 0 (GPIO) */ 75 #define P0_0_PORT GPIO_PRT0 76 #define P0_0_PIN 0u 77 #define P0_0_NUM 0u 78 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 79 #define P0_1_PORT GPIO_PRT0 80 #define P0_1_PIN 1u 81 #define P0_1_NUM 1u 82 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 83 #define P0_2_PORT GPIO_PRT0 84 #define P0_2_PIN 2u 85 #define P0_2_NUM 2u 86 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 87 #define P0_3_PORT GPIO_PRT0 88 #define P0_3_PIN 3u 89 #define P0_3_NUM 3u 90 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 91 #define P0_4_PORT GPIO_PRT0 92 #define P0_4_PIN 4u 93 #define P0_4_NUM 4u 94 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 95 #define P0_5_PORT GPIO_PRT0 96 #define P0_5_PIN 5u 97 #define P0_5_NUM 5u 98 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 99 100 /* PORT 1 (GPIO_OVT) */ 101 #define P1_0_PORT GPIO_PRT1 102 #define P1_0_PIN 0u 103 #define P1_0_NUM 0u 104 #define P1_0_AMUXSEGMENT AMUXBUS_NOISY 105 #define P1_1_PORT GPIO_PRT1 106 #define P1_1_PIN 1u 107 #define P1_1_NUM 1u 108 #define P1_1_AMUXSEGMENT AMUXBUS_NOISY 109 #define P1_4_PORT GPIO_PRT1 110 #define P1_4_PIN 4u 111 #define P1_4_NUM 4u 112 #define P1_4_AMUXSEGMENT AMUXBUS_NOISY 113 #define P1_5_PORT GPIO_PRT1 114 #define P1_5_PIN 5u 115 #define P1_5_NUM 5u 116 #define P1_5_AMUXSEGMENT AMUXBUS_NOISY 117 118 /* PORT 2 (GPIO) */ 119 #define P2_0_PORT GPIO_PRT2 120 #define P2_0_PIN 0u 121 #define P2_0_NUM 0u 122 #define P2_0_AMUXSEGMENT AMUXBUS_NOISY 123 #define P2_1_PORT GPIO_PRT2 124 #define P2_1_PIN 1u 125 #define P2_1_NUM 1u 126 #define P2_1_AMUXSEGMENT AMUXBUS_NOISY 127 #define P2_2_PORT GPIO_PRT2 128 #define P2_2_PIN 2u 129 #define P2_2_NUM 2u 130 #define P2_2_AMUXSEGMENT AMUXBUS_NOISY 131 #define P2_3_PORT GPIO_PRT2 132 #define P2_3_PIN 3u 133 #define P2_3_NUM 3u 134 #define P2_3_AMUXSEGMENT AMUXBUS_NOISY 135 #define P2_4_PORT GPIO_PRT2 136 #define P2_4_PIN 4u 137 #define P2_4_NUM 4u 138 #define P2_4_AMUXSEGMENT AMUXBUS_NOISY 139 #define P2_5_PORT GPIO_PRT2 140 #define P2_5_PIN 5u 141 #define P2_5_NUM 5u 142 #define P2_5_AMUXSEGMENT AMUXBUS_NOISY 143 #define P2_6_PORT GPIO_PRT2 144 #define P2_6_PIN 6u 145 #define P2_6_NUM 6u 146 #define P2_6_AMUXSEGMENT AMUXBUS_NOISY 147 #define P2_7_PORT GPIO_PRT2 148 #define P2_7_PIN 7u 149 #define P2_7_NUM 7u 150 #define P2_7_AMUXSEGMENT AMUXBUS_NOISY 151 152 /* PORT 5 (GPIO) */ 153 #define P5_0_PORT GPIO_PRT5 154 #define P5_0_PIN 0u 155 #define P5_0_NUM 0u 156 #define P5_0_AMUXSEGMENT AMUXBUS_CSD0 157 #define P5_1_PORT GPIO_PRT5 158 #define P5_1_PIN 1u 159 #define P5_1_NUM 1u 160 #define P5_1_AMUXSEGMENT AMUXBUS_CSD0 161 #define P5_2_PORT GPIO_PRT5 162 #define P5_2_PIN 2u 163 #define P5_2_NUM 2u 164 #define P5_2_AMUXSEGMENT AMUXBUS_CSD0 165 #define P5_3_PORT GPIO_PRT5 166 #define P5_3_PIN 3u 167 #define P5_3_NUM 3u 168 #define P5_3_AMUXSEGMENT AMUXBUS_CSD0 169 #define P5_4_PORT GPIO_PRT5 170 #define P5_4_PIN 4u 171 #define P5_4_NUM 4u 172 #define P5_4_AMUXSEGMENT AMUXBUS_CSD0 173 #define P5_5_PORT GPIO_PRT5 174 #define P5_5_PIN 5u 175 #define P5_5_NUM 5u 176 #define P5_5_AMUXSEGMENT AMUXBUS_CSD0 177 #define P5_6_PORT GPIO_PRT5 178 #define P5_6_PIN 6u 179 #define P5_6_NUM 6u 180 #define P5_6_AMUXSEGMENT AMUXBUS_CSD0 181 #define P5_7_PORT GPIO_PRT5 182 #define P5_7_PIN 7u 183 #define P5_7_NUM 7u 184 #define P5_7_AMUXSEGMENT AMUXBUS_CSD0 185 186 /* PORT 6 (GPIO) */ 187 #define P6_0_PORT GPIO_PRT6 188 #define P6_0_PIN 0u 189 #define P6_0_NUM 0u 190 #define P6_0_AMUXSEGMENT AMUXBUS_CSD0 191 #define P6_1_PORT GPIO_PRT6 192 #define P6_1_PIN 1u 193 #define P6_1_NUM 1u 194 #define P6_1_AMUXSEGMENT AMUXBUS_CSD0 195 #define P6_2_PORT GPIO_PRT6 196 #define P6_2_PIN 2u 197 #define P6_2_NUM 2u 198 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 199 #define P6_3_PORT GPIO_PRT6 200 #define P6_3_PIN 3u 201 #define P6_3_NUM 3u 202 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 203 #define P6_4_PORT GPIO_PRT6 204 #define P6_4_PIN 4u 205 #define P6_4_NUM 4u 206 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 207 #define P6_5_PORT GPIO_PRT6 208 #define P6_5_PIN 5u 209 #define P6_5_NUM 5u 210 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 211 #define P6_6_PORT GPIO_PRT6 212 #define P6_6_PIN 6u 213 #define P6_6_NUM 6u 214 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 215 #define P6_7_PORT GPIO_PRT6 216 #define P6_7_PIN 7u 217 #define P6_7_NUM 7u 218 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 219 220 /* PORT 7 (GPIO) */ 221 #define P7_0_PORT GPIO_PRT7 222 #define P7_0_PIN 0u 223 #define P7_0_NUM 0u 224 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 225 #define P7_1_PORT GPIO_PRT7 226 #define P7_1_PIN 1u 227 #define P7_1_NUM 1u 228 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 229 #define P7_2_PORT GPIO_PRT7 230 #define P7_2_PIN 2u 231 #define P7_2_NUM 2u 232 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 233 #define P7_3_PORT GPIO_PRT7 234 #define P7_3_PIN 3u 235 #define P7_3_NUM 3u 236 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 237 #define P7_7_PORT GPIO_PRT7 238 #define P7_7_PIN 7u 239 #define P7_7_NUM 7u 240 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 241 242 /* PORT 8 (GPIO) */ 243 #define P8_0_PORT GPIO_PRT8 244 #define P8_0_PIN 0u 245 #define P8_0_NUM 0u 246 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 247 #define P8_1_PORT GPIO_PRT8 248 #define P8_1_PIN 1u 249 #define P8_1_NUM 1u 250 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 251 #define P8_2_PORT GPIO_PRT8 252 #define P8_2_PIN 2u 253 #define P8_2_NUM 2u 254 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 255 #define P8_3_PORT GPIO_PRT8 256 #define P8_3_PIN 3u 257 #define P8_3_NUM 3u 258 #define P8_3_AMUXSEGMENT AMUXBUS_CSD0 259 #define P8_4_PORT GPIO_PRT8 260 #define P8_4_PIN 4u 261 #define P8_4_NUM 4u 262 #define P8_4_AMUXSEGMENT AMUXBUS_CSD0 263 264 /* PORT 9 (GPIO) */ 265 #define P9_0_PORT GPIO_PRT9 266 #define P9_0_PIN 0u 267 #define P9_0_NUM 0u 268 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 269 #define P9_1_PORT GPIO_PRT9 270 #define P9_1_PIN 1u 271 #define P9_1_NUM 1u 272 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 273 #define P9_2_PORT GPIO_PRT9 274 #define P9_2_PIN 2u 275 #define P9_2_NUM 2u 276 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 277 #define P9_3_PORT GPIO_PRT9 278 #define P9_3_PIN 3u 279 #define P9_3_NUM 3u 280 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 281 #define P9_4_PORT GPIO_PRT9 282 #define P9_4_PIN 4u 283 #define P9_4_NUM 4u 284 #define P9_4_AMUXSEGMENT AMUXBUS_SAR 285 #define P9_7_PORT GPIO_PRT9 286 #define P9_7_PIN 7u 287 #define P9_7_NUM 7u 288 #define P9_7_AMUXSEGMENT AMUXBUS_SAR 289 290 /* PORT 10 (GPIO) */ 291 #define P10_0_PORT GPIO_PRT10 292 #define P10_0_PIN 0u 293 #define P10_0_NUM 0u 294 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 295 #define P10_1_PORT GPIO_PRT10 296 #define P10_1_PIN 1u 297 #define P10_1_NUM 1u 298 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 299 #define P10_2_PORT GPIO_PRT10 300 #define P10_2_PIN 2u 301 #define P10_2_NUM 2u 302 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 303 #define P10_3_PORT GPIO_PRT10 304 #define P10_3_PIN 3u 305 #define P10_3_NUM 3u 306 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 307 #define P10_4_PORT GPIO_PRT10 308 #define P10_4_PIN 4u 309 #define P10_4_NUM 4u 310 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 311 #define P10_5_PORT GPIO_PRT10 312 #define P10_5_PIN 5u 313 #define P10_5_NUM 5u 314 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 315 #define P10_6_PORT GPIO_PRT10 316 #define P10_6_PIN 6u 317 #define P10_6_NUM 6u 318 #define P10_6_AMUXSEGMENT AMUXBUS_SAR 319 #define P10_7_PORT GPIO_PRT10 320 #define P10_7_PIN 7u 321 #define P10_7_NUM 7u 322 #define P10_7_AMUXSEGMENT AMUXBUS_SAR 323 324 /* PORT 11 (GPIO) */ 325 #define P11_0_PORT GPIO_PRT11 326 #define P11_0_PIN 0u 327 #define P11_0_NUM 0u 328 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 329 #define P11_1_PORT GPIO_PRT11 330 #define P11_1_PIN 1u 331 #define P11_1_NUM 1u 332 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 333 #define P11_2_PORT GPIO_PRT11 334 #define P11_2_PIN 2u 335 #define P11_2_NUM 2u 336 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 337 #define P11_3_PORT GPIO_PRT11 338 #define P11_3_PIN 3u 339 #define P11_3_NUM 3u 340 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 341 #define P11_4_PORT GPIO_PRT11 342 #define P11_4_PIN 4u 343 #define P11_4_NUM 4u 344 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 345 #define P11_5_PORT GPIO_PRT11 346 #define P11_5_PIN 5u 347 #define P11_5_NUM 5u 348 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 349 #define P11_6_PORT GPIO_PRT11 350 #define P11_6_PIN 6u 351 #define P11_6_NUM 6u 352 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 353 #define P11_7_PORT GPIO_PRT11 354 #define P11_7_PIN 7u 355 #define P11_7_NUM 7u 356 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 357 358 /* PORT 12 (GPIO) */ 359 #define P12_0_PORT GPIO_PRT12 360 #define P12_0_PIN 0u 361 #define P12_0_NUM 0u 362 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 363 #define P12_1_PORT GPIO_PRT12 364 #define P12_1_PIN 1u 365 #define P12_1_NUM 1u 366 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 367 #define P12_2_PORT GPIO_PRT12 368 #define P12_2_PIN 2u 369 #define P12_2_NUM 2u 370 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 371 #define P12_3_PORT GPIO_PRT12 372 #define P12_3_PIN 3u 373 #define P12_3_NUM 3u 374 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 375 #define P12_4_PORT GPIO_PRT12 376 #define P12_4_PIN 4u 377 #define P12_4_NUM 4u 378 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 379 #define P12_5_PORT GPIO_PRT12 380 #define P12_5_PIN 5u 381 #define P12_5_NUM 5u 382 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 383 #define P12_6_PORT GPIO_PRT12 384 #define P12_6_PIN 6u 385 #define P12_6_NUM 6u 386 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 387 #define P12_7_PORT GPIO_PRT12 388 #define P12_7_PIN 7u 389 #define P12_7_NUM 7u 390 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 391 392 /* PORT 13 (GPIO) */ 393 #define P13_0_PORT GPIO_PRT13 394 #define P13_0_PIN 0u 395 #define P13_0_NUM 0u 396 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 397 #define P13_1_PORT GPIO_PRT13 398 #define P13_1_PIN 1u 399 #define P13_1_NUM 1u 400 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 401 #define P13_2_PORT GPIO_PRT13 402 #define P13_2_PIN 2u 403 #define P13_2_NUM 2u 404 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 405 #define P13_3_PORT GPIO_PRT13 406 #define P13_3_PIN 3u 407 #define P13_3_NUM 3u 408 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 409 #define P13_4_PORT GPIO_PRT13 410 #define P13_4_PIN 4u 411 #define P13_4_NUM 4u 412 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 413 #define P13_5_PORT GPIO_PRT13 414 #define P13_5_PIN 5u 415 #define P13_5_NUM 5u 416 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 417 #define P13_6_PORT GPIO_PRT13 418 #define P13_6_PIN 6u 419 #define P13_6_NUM 6u 420 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 421 #define P13_7_PORT GPIO_PRT13 422 #define P13_7_PIN 7u 423 #define P13_7_NUM 7u 424 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 425 426 /* PORT 14 (AUX) */ 427 #define USBDP_PORT GPIO_PRT14 428 #define USBDP_PIN 0u 429 #define USBDP_NUM 0u 430 #define USBDP_AMUXSEGMENT AMUXBUS_NOISY 431 #define P14_0_PORT GPIO_PRT14 432 #define P14_0_PIN 0u 433 #define P14_0_NUM 0u 434 #define P14_0_AMUXSEGMENT AMUXBUS_NOISY 435 #define USBDM_PORT GPIO_PRT14 436 #define USBDM_PIN 1u 437 #define USBDM_NUM 1u 438 #define USBDM_AMUXSEGMENT AMUXBUS_NOISY 439 #define P14_1_PORT GPIO_PRT14 440 #define P14_1_PIN 1u 441 #define P14_1_NUM 1u 442 #define P14_1_AMUXSEGMENT AMUXBUS_NOISY 443 444 /* Analog Connections */ 445 #define CSD_CMODPADD_PORT 7u 446 #define CSD_CMODPADD_PIN 1u 447 #define CSD_CMODPADS_PORT 7u 448 #define CSD_CMODPADS_PIN 1u 449 #define CSD_CSH_TANKPADD_PORT 7u 450 #define CSD_CSH_TANKPADD_PIN 2u 451 #define CSD_CSH_TANKPADS_PORT 7u 452 #define CSD_CSH_TANKPADS_PIN 2u 453 #define CSD_CSHIELDPADS_PORT 7u 454 #define CSD_CSHIELDPADS_PIN 7u 455 #define CSD_VREF_EXT_PORT 7u 456 #define CSD_VREF_EXT_PIN 3u 457 #define IOSS_ADFT0_NET_PORT 10u 458 #define IOSS_ADFT0_NET_PIN 0u 459 #define IOSS_ADFT1_NET_PORT 10u 460 #define IOSS_ADFT1_NET_PIN 1u 461 #define LPCOMP_INN_COMP0_PORT 5u 462 #define LPCOMP_INN_COMP0_PIN 7u 463 #define LPCOMP_INN_COMP1_PORT 6u 464 #define LPCOMP_INN_COMP1_PIN 3u 465 #define LPCOMP_INP_COMP0_PORT 5u 466 #define LPCOMP_INP_COMP0_PIN 6u 467 #define LPCOMP_INP_COMP1_PORT 6u 468 #define LPCOMP_INP_COMP1_PIN 2u 469 #define PASS_AREF_EXT_VREF_PORT 9u 470 #define PASS_AREF_EXT_VREF_PIN 7u 471 #define PASS_SARMUX_PADS0_PORT 10u 472 #define PASS_SARMUX_PADS0_PIN 0u 473 #define PASS_SARMUX_PADS1_PORT 10u 474 #define PASS_SARMUX_PADS1_PIN 1u 475 #define PASS_SARMUX_PADS2_PORT 10u 476 #define PASS_SARMUX_PADS2_PIN 2u 477 #define PASS_SARMUX_PADS3_PORT 10u 478 #define PASS_SARMUX_PADS3_PIN 3u 479 #define PASS_SARMUX_PADS4_PORT 10u 480 #define PASS_SARMUX_PADS4_PIN 4u 481 #define PASS_SARMUX_PADS5_PORT 10u 482 #define PASS_SARMUX_PADS5_PIN 5u 483 #define PASS_SARMUX_PADS6_PORT 10u 484 #define PASS_SARMUX_PADS6_PIN 6u 485 #define PASS_SARMUX_PADS7_PORT 10u 486 #define PASS_SARMUX_PADS7_PIN 7u 487 #define SRSS_ADFT_PIN0_PORT 10u 488 #define SRSS_ADFT_PIN0_PIN 0u 489 #define SRSS_ADFT_PIN1_PORT 10u 490 #define SRSS_ADFT_PIN1_PIN 1u 491 #define SRSS_ECO_IN_PORT 12u 492 #define SRSS_ECO_IN_PIN 6u 493 #define SRSS_ECO_OUT_PORT 12u 494 #define SRSS_ECO_OUT_PIN 7u 495 #define SRSS_WCO_IN_PORT 0u 496 #define SRSS_WCO_IN_PIN 0u 497 #define SRSS_WCO_OUT_PORT 0u 498 #define SRSS_WCO_OUT_PIN 1u 499 500 /* HSIOM Connections */ 501 typedef enum 502 { 503 /* Generic HSIOM connections */ 504 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 505 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 506 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 507 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 508 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 509 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 510 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 511 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 512 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 513 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 514 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 515 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 516 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 517 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 518 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 519 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 520 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 521 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 522 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 523 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 524 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 525 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 526 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 527 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 528 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 529 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 530 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 531 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 532 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 533 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 534 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 535 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 536 537 /* P0.0 */ 538 P0_0_GPIO = 0, /* GPIO controls 'out' */ 539 P0_0_AMUXA = 4, /* Analog mux bus A */ 540 P0_0_AMUXB = 5, /* Analog mux bus B */ 541 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 542 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 543 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 544 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 545 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 546 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 547 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 548 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 549 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 550 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 551 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 552 553 /* P0.1 */ 554 P0_1_GPIO = 0, /* GPIO controls 'out' */ 555 P0_1_AMUXA = 4, /* Analog mux bus A */ 556 P0_1_AMUXB = 5, /* Analog mux bus B */ 557 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 558 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 559 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 560 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 561 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 562 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 563 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 564 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 565 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 566 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 567 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 568 569 /* P0.2 */ 570 P0_2_GPIO = 0, /* GPIO controls 'out' */ 571 P0_2_AMUXA = 4, /* Analog mux bus A */ 572 P0_2_AMUXB = 5, /* Analog mux bus B */ 573 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 574 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 575 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 576 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 577 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 578 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 579 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 580 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 581 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 582 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 583 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 584 585 /* P0.3 */ 586 P0_3_GPIO = 0, /* GPIO controls 'out' */ 587 P0_3_AMUXA = 4, /* Analog mux bus A */ 588 P0_3_AMUXB = 5, /* Analog mux bus B */ 589 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 590 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 591 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 592 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 593 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 594 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 595 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 596 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 597 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 598 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 599 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 600 601 /* P0.4 */ 602 P0_4_GPIO = 0, /* GPIO controls 'out' */ 603 P0_4_AMUXA = 4, /* Analog mux bus A */ 604 P0_4_AMUXB = 5, /* Analog mux bus B */ 605 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 606 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 607 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 608 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 609 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 610 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 611 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 612 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 613 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 614 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 615 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 616 617 /* P0.5 */ 618 P0_5_GPIO = 0, /* GPIO controls 'out' */ 619 P0_5_AMUXA = 4, /* Analog mux bus A */ 620 P0_5_AMUXB = 5, /* Analog mux bus B */ 621 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 622 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 623 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 624 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 625 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 626 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 627 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 628 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 629 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 630 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 631 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 632 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 633 634 /* P1.0 */ 635 P1_0_GPIO = 0, /* GPIO controls 'out' */ 636 P1_0_AMUXA = 4, /* Analog mux bus A */ 637 P1_0_AMUXB = 5, /* Analog mux bus B */ 638 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 639 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 640 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 641 P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 642 P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 643 P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 644 P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 645 P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 646 P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ 647 P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ 648 P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ 649 P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 650 651 /* P1.1 */ 652 P1_1_GPIO = 0, /* GPIO controls 'out' */ 653 P1_1_AMUXA = 4, /* Analog mux bus A */ 654 P1_1_AMUXB = 5, /* Analog mux bus B */ 655 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 656 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 657 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 658 P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 659 P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 660 P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 661 P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 662 P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 663 P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ 664 P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ 665 P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ 666 P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 667 668 /* P1.4 */ 669 P1_4_GPIO = 0, /* GPIO controls 'out' */ 670 P1_4_AMUXA = 4, /* Analog mux bus A */ 671 P1_4_AMUXB = 5, /* Analog mux bus B */ 672 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 673 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 674 P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ 675 P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ 676 P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 677 P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 678 P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 679 P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 680 P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ 681 682 /* P1.5 */ 683 P1_5_GPIO = 0, /* GPIO controls 'out' */ 684 P1_5_AMUXA = 4, /* Analog mux bus A */ 685 P1_5_AMUXB = 5, /* Analog mux bus B */ 686 P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 687 P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 688 P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ 689 P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 690 P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 691 P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 692 P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 693 P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 694 P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ 695 696 /* P2.0 */ 697 P2_0_GPIO = 0, /* GPIO controls 'out' */ 698 P2_0_AMUXA = 4, /* Analog mux bus A */ 699 P2_0_AMUXB = 5, /* Analog mux bus B */ 700 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 701 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 702 P2_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:4 */ 703 P2_0_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:1 */ 704 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 705 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 706 P2_0_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 707 P2_0_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 708 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 709 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 710 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 711 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 712 P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ 713 714 /* P2.1 */ 715 P2_1_GPIO = 0, /* GPIO controls 'out' */ 716 P2_1_AMUXA = 4, /* Analog mux bus A */ 717 P2_1_AMUXB = 5, /* Analog mux bus B */ 718 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 719 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 720 P2_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:4 */ 721 P2_1_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:1 */ 722 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 723 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 724 P2_1_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 725 P2_1_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 726 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 727 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 728 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 729 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 730 P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ 731 732 /* P2.2 */ 733 P2_2_GPIO = 0, /* GPIO controls 'out' */ 734 P2_2_AMUXA = 4, /* Analog mux bus A */ 735 P2_2_AMUXB = 5, /* Analog mux bus B */ 736 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 737 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 738 P2_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:4 */ 739 P2_2_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:1 */ 740 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 741 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 742 P2_2_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 743 P2_2_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 744 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 745 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 746 P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ 747 748 /* P2.3 */ 749 P2_3_GPIO = 0, /* GPIO controls 'out' */ 750 P2_3_AMUXA = 4, /* Analog mux bus A */ 751 P2_3_AMUXB = 5, /* Analog mux bus B */ 752 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 753 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 754 P2_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:4 */ 755 P2_3_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:1 */ 756 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 757 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 758 P2_3_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 759 P2_3_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 760 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 761 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 762 P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ 763 764 /* P2.4 */ 765 P2_4_GPIO = 0, /* GPIO controls 'out' */ 766 P2_4_AMUXA = 4, /* Analog mux bus A */ 767 P2_4_AMUXB = 5, /* Analog mux bus B */ 768 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 769 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 770 P2_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 771 P2_4_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:1 */ 772 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 773 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 774 P2_4_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 775 P2_4_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 776 P2_4_SCB9_UART_RX = 18, /* Digital Active - scb[9].uart_rx:0 */ 777 P2_4_SCB9_I2C_SCL = 19, /* Digital Active - scb[9].i2c_scl:0 */ 778 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 779 P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ 780 781 /* P2.5 */ 782 P2_5_GPIO = 0, /* GPIO controls 'out' */ 783 P2_5_AMUXA = 4, /* Analog mux bus A */ 784 P2_5_AMUXB = 5, /* Analog mux bus B */ 785 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 786 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 787 P2_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 788 P2_5_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ 789 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 790 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 791 P2_5_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 792 P2_5_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 793 P2_5_SCB9_UART_TX = 18, /* Digital Active - scb[9].uart_tx:0 */ 794 P2_5_SCB9_I2C_SDA = 19, /* Digital Active - scb[9].i2c_sda:0 */ 795 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 796 P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ 797 798 /* P2.6 */ 799 P2_6_GPIO = 0, /* GPIO controls 'out' */ 800 P2_6_AMUXA = 4, /* Analog mux bus A */ 801 P2_6_AMUXB = 5, /* Analog mux bus B */ 802 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 803 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 804 P2_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 805 P2_6_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:1 */ 806 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 807 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 808 P2_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 809 P2_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 810 P2_6_SCB9_UART_RTS = 18, /* Digital Active - scb[9].uart_rts:0 */ 811 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 812 P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ 813 814 /* P2.7 */ 815 P2_7_GPIO = 0, /* GPIO controls 'out' */ 816 P2_7_AMUXA = 4, /* Analog mux bus A */ 817 P2_7_AMUXB = 5, /* Analog mux bus B */ 818 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 819 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 820 P2_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 821 P2_7_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ 822 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 823 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 824 P2_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 825 P2_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 826 P2_7_SCB9_UART_CTS = 18, /* Digital Active - scb[9].uart_cts:0 */ 827 P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ 828 829 /* P5.0 */ 830 P5_0_GPIO = 0, /* GPIO controls 'out' */ 831 P5_0_AMUXA = 4, /* Analog mux bus A */ 832 P5_0_AMUXB = 5, /* Analog mux bus B */ 833 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 834 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 835 P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 836 P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 837 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 838 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 839 P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 840 P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 841 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 842 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 843 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 844 P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ 845 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 846 847 /* P5.1 */ 848 P5_1_GPIO = 0, /* GPIO controls 'out' */ 849 P5_1_AMUXA = 4, /* Analog mux bus A */ 850 P5_1_AMUXB = 5, /* Analog mux bus B */ 851 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 852 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 853 P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 854 P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 855 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 856 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 857 P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 858 P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 859 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 860 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 861 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 862 P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ 863 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 864 865 /* P5.2 */ 866 P5_2_GPIO = 0, /* GPIO controls 'out' */ 867 P5_2_AMUXA = 4, /* Analog mux bus A */ 868 P5_2_AMUXB = 5, /* Analog mux bus B */ 869 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 870 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 871 P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 872 P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 873 P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 874 P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 875 P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 876 P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 877 P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 878 P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 879 P5_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:0 */ 880 881 /* P5.3 */ 882 P5_3_GPIO = 0, /* GPIO controls 'out' */ 883 P5_3_AMUXA = 4, /* Analog mux bus A */ 884 P5_3_AMUXB = 5, /* Analog mux bus B */ 885 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 886 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 887 P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 888 P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 889 P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 890 P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 891 P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 892 P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 893 P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 894 P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 895 P5_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:0 */ 896 897 /* P5.4 */ 898 P5_4_GPIO = 0, /* GPIO controls 'out' */ 899 P5_4_AMUXA = 4, /* Analog mux bus A */ 900 P5_4_AMUXB = 5, /* Analog mux bus B */ 901 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 902 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 903 P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 904 P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 905 P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 906 P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 907 P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ 908 P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ 909 P5_4_SCB10_UART_RX = 18, /* Digital Active - scb[10].uart_rx:0 */ 910 P5_4_SCB10_I2C_SCL = 19, /* Digital Active - scb[10].i2c_scl:0 */ 911 P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 912 P5_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:0 */ 913 914 /* P5.5 */ 915 P5_5_GPIO = 0, /* GPIO controls 'out' */ 916 P5_5_AMUXA = 4, /* Analog mux bus A */ 917 P5_5_AMUXB = 5, /* Analog mux bus B */ 918 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 919 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 920 P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 921 P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 922 P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 923 P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 924 P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 925 P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 926 P5_5_SCB10_UART_TX = 18, /* Digital Active - scb[10].uart_tx:0 */ 927 P5_5_SCB10_I2C_SDA = 19, /* Digital Active - scb[10].i2c_sda:0 */ 928 P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 929 P5_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:0 */ 930 931 /* P5.6 */ 932 P5_6_GPIO = 0, /* GPIO controls 'out' */ 933 P5_6_AMUXA = 4, /* Analog mux bus A */ 934 P5_6_AMUXB = 5, /* Analog mux bus B */ 935 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 936 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 937 P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 938 P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 939 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 940 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 941 P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 942 P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 943 P5_6_SCB10_UART_RTS = 18, /* Digital Active - scb[10].uart_rts:0 */ 944 P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 945 P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ 946 947 /* P5.7 */ 948 P5_7_GPIO = 0, /* GPIO controls 'out' */ 949 P5_7_AMUXA = 4, /* Analog mux bus A */ 950 P5_7_AMUXB = 5, /* Analog mux bus B */ 951 P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 952 P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 953 P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 954 P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 955 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 956 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 957 P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 958 P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 959 P5_7_SCB10_UART_CTS = 18, /* Digital Active - scb[10].uart_cts:0 */ 960 P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */ 961 962 /* P6.0 */ 963 P6_0_GPIO = 0, /* GPIO controls 'out' */ 964 P6_0_AMUXA = 4, /* Analog mux bus A */ 965 P6_0_AMUXB = 5, /* Analog mux bus B */ 966 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 967 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 968 P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 969 P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ 970 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 971 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 972 P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 973 P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 974 P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ 975 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 976 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 977 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 978 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 979 P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ 980 981 /* P6.1 */ 982 P6_1_GPIO = 0, /* GPIO controls 'out' */ 983 P6_1_AMUXA = 4, /* Analog mux bus A */ 984 P6_1_AMUXB = 5, /* Analog mux bus B */ 985 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 986 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 987 P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 988 P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 989 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 990 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 991 P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 992 P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 993 P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ 994 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 995 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 996 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 997 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 998 P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ 999 1000 /* P6.2 */ 1001 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1002 P6_2_AMUXA = 4, /* Analog mux bus A */ 1003 P6_2_AMUXB = 5, /* Analog mux bus B */ 1004 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1005 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1006 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 1007 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 1008 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 1009 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 1010 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 1011 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 1012 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 1013 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 1014 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 1015 1016 /* P6.3 */ 1017 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1018 P6_3_AMUXA = 4, /* Analog mux bus A */ 1019 P6_3_AMUXB = 5, /* Analog mux bus B */ 1020 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1021 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1022 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 1023 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 1024 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 1025 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 1026 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 1027 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 1028 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 1029 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 1030 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 1031 1032 /* P6.4 */ 1033 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1034 P6_4_AMUXA = 4, /* Analog mux bus A */ 1035 P6_4_AMUXB = 5, /* Analog mux bus B */ 1036 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1037 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1038 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 1039 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 1040 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 1041 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 1042 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 1043 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 1044 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 1045 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 1046 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 1047 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 1048 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 1049 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 1050 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 1051 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 1052 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1053 1054 /* P6.5 */ 1055 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1056 P6_5_AMUXA = 4, /* Analog mux bus A */ 1057 P6_5_AMUXB = 5, /* Analog mux bus B */ 1058 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1059 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1060 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 1061 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 1062 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 1063 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 1064 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 1065 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 1066 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 1067 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 1068 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 1069 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 1070 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 1071 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 1072 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 1073 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 1074 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1075 1076 /* P6.6 */ 1077 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1078 P6_6_AMUXA = 4, /* Analog mux bus A */ 1079 P6_6_AMUXB = 5, /* Analog mux bus B */ 1080 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1081 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1082 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 1083 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 1084 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 1085 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 1086 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 1087 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 1088 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 1089 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 1090 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 1091 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 1092 1093 /* P6.7 */ 1094 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1095 P6_7_AMUXA = 4, /* Analog mux bus A */ 1096 P6_7_AMUXB = 5, /* Analog mux bus B */ 1097 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1098 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1099 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 1100 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1101 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 1102 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 1103 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 1104 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 1105 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 1106 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 1107 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 1108 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 1109 1110 /* P7.0 */ 1111 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1112 P7_0_AMUXA = 4, /* Analog mux bus A */ 1113 P7_0_AMUXB = 5, /* Analog mux bus B */ 1114 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1115 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1116 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 1117 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 1118 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1119 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1120 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1121 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1122 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 1123 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 1124 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 1125 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 1126 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 1127 1128 /* P7.1 */ 1129 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1130 P7_1_AMUXA = 4, /* Analog mux bus A */ 1131 P7_1_AMUXB = 5, /* Analog mux bus B */ 1132 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1133 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1134 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1135 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1136 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1137 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1138 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1139 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1140 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 1141 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 1142 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 1143 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 1144 1145 /* P7.2 */ 1146 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1147 P7_2_AMUXA = 4, /* Analog mux bus A */ 1148 P7_2_AMUXB = 5, /* Analog mux bus B */ 1149 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1150 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1151 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1152 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 1153 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1154 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1155 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1156 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1157 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 1158 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 1159 1160 /* P7.3 */ 1161 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1162 P7_3_AMUXA = 4, /* Analog mux bus A */ 1163 P7_3_AMUXB = 5, /* Analog mux bus B */ 1164 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1165 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1166 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1167 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1168 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1169 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1170 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1171 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1172 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 1173 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 1174 1175 /* P7.7 */ 1176 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1177 P7_7_AMUXA = 4, /* Analog mux bus A */ 1178 P7_7_AMUXB = 5, /* Analog mux bus B */ 1179 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1180 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1181 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1182 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 1183 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1184 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1185 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1186 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1187 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 1188 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 1189 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 1190 1191 /* P8.0 */ 1192 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1193 P8_0_AMUXA = 4, /* Analog mux bus A */ 1194 P8_0_AMUXB = 5, /* Analog mux bus B */ 1195 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1196 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1197 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 1198 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 1199 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1200 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1201 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1202 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1203 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 1204 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 1205 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 1206 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 1207 1208 /* P8.1 */ 1209 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1210 P8_1_AMUXA = 4, /* Analog mux bus A */ 1211 P8_1_AMUXB = 5, /* Analog mux bus B */ 1212 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1213 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1214 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 1215 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 1216 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1217 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1218 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1219 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1220 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 1221 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 1222 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 1223 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 1224 1225 /* P8.2 */ 1226 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1227 P8_2_AMUXA = 4, /* Analog mux bus A */ 1228 P8_2_AMUXB = 5, /* Analog mux bus B */ 1229 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1230 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1231 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 1232 P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ 1233 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1234 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1235 P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1236 P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1237 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 1238 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 1239 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 1240 1241 /* P8.3 */ 1242 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1243 P8_3_AMUXA = 4, /* Analog mux bus A */ 1244 P8_3_AMUXB = 5, /* Analog mux bus B */ 1245 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1246 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1247 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 1248 P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 1249 P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1250 P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1251 P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1252 P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1253 P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 1254 P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 1255 P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 1256 1257 /* P8.4 */ 1258 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1259 P8_4_AMUXA = 4, /* Analog mux bus A */ 1260 P8_4_AMUXB = 5, /* Analog mux bus B */ 1261 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1262 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1263 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 1264 P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ 1265 P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1266 P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1267 P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1268 P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1269 P8_4_SCB11_UART_RX = 18, /* Digital Active - scb[11].uart_rx:0 */ 1270 P8_4_SCB11_I2C_SCL = 19, /* Digital Active - scb[11].i2c_scl:0 */ 1271 P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ 1272 1273 /* P9.0 */ 1274 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1275 P9_0_AMUXA = 4, /* Analog mux bus A */ 1276 P9_0_AMUXB = 5, /* Analog mux bus B */ 1277 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1278 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1279 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 1280 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 1281 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1282 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1283 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 1284 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 1285 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 1286 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 1287 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 1288 P9_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:1 */ 1289 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 1290 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1291 1292 /* P9.1 */ 1293 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1294 P9_1_AMUXA = 4, /* Analog mux bus A */ 1295 P9_1_AMUXB = 5, /* Analog mux bus B */ 1296 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1297 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1298 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 1299 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 1300 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1301 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1302 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1303 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1304 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 1305 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 1306 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 1307 P9_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:1 */ 1308 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 1309 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1310 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1311 1312 /* P9.2 */ 1313 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1314 P9_2_AMUXA = 4, /* Analog mux bus A */ 1315 P9_2_AMUXB = 5, /* Analog mux bus B */ 1316 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1317 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1318 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 1319 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 1320 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 1321 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 1322 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1323 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1324 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1325 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1326 P9_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:1 */ 1327 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1328 1329 /* P9.3 */ 1330 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1331 P9_3_AMUXA = 4, /* Analog mux bus A */ 1332 P9_3_AMUXB = 5, /* Analog mux bus B */ 1333 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1334 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1335 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 1336 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1337 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 1338 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 1339 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1340 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1341 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1342 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1343 P9_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:1 */ 1344 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1345 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1346 1347 /* P9.4 */ 1348 P9_4_GPIO = 0, /* GPIO controls 'out' */ 1349 P9_4_AMUXA = 4, /* Analog mux bus A */ 1350 P9_4_AMUXB = 5, /* Analog mux bus B */ 1351 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1352 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1353 P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ 1354 P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ 1355 P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ 1356 P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ 1357 P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ 1358 P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ 1359 P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ 1360 P9_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:1 */ 1361 1362 /* P9.7 */ 1363 P9_7_GPIO = 0, /* GPIO controls 'out' */ 1364 P9_7_AMUXA = 4, /* Analog mux bus A */ 1365 P9_7_AMUXB = 5, /* Analog mux bus B */ 1366 P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1367 P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1368 P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1369 P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 1370 P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ 1371 P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ 1372 P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ 1373 P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ 1374 1375 /* P10.0 */ 1376 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1377 P10_0_AMUXA = 4, /* Analog mux bus A */ 1378 P10_0_AMUXB = 5, /* Analog mux bus B */ 1379 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1380 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1381 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 1382 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 1383 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 1384 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 1385 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 1386 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 1387 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1388 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1389 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1390 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1391 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1392 1393 /* P10.1 */ 1394 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1395 P10_1_AMUXA = 4, /* Analog mux bus A */ 1396 P10_1_AMUXB = 5, /* Analog mux bus B */ 1397 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1398 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1399 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 1400 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1401 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 1402 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 1403 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 1404 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 1405 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1406 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1407 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1408 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1409 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1410 1411 /* P10.2 */ 1412 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1413 P10_2_AMUXA = 4, /* Analog mux bus A */ 1414 P10_2_AMUXB = 5, /* Analog mux bus B */ 1415 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1416 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1417 P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ 1418 P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ 1419 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ 1420 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ 1421 P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ 1422 P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ 1423 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 1424 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 1425 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1426 1427 /* P10.3 */ 1428 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1429 P10_3_AMUXA = 4, /* Analog mux bus A */ 1430 P10_3_AMUXB = 5, /* Analog mux bus B */ 1431 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1432 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1433 P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ 1434 P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 1435 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ 1436 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ 1437 P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ 1438 P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ 1439 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 1440 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 1441 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1442 1443 /* P10.4 */ 1444 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1445 P10_4_AMUXA = 4, /* Analog mux bus A */ 1446 P10_4_AMUXB = 5, /* Analog mux bus B */ 1447 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1448 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1449 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 1450 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 1451 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ 1452 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ 1453 P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ 1454 P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ 1455 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1456 P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0 */ 1457 1458 /* P10.5 */ 1459 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1460 P10_5_AMUXA = 4, /* Analog mux bus A */ 1461 P10_5_AMUXB = 5, /* Analog mux bus B */ 1462 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1463 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1464 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 1465 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1466 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ 1467 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ 1468 P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ 1469 P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ 1470 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1471 P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0 */ 1472 1473 /* P10.6 */ 1474 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1475 P10_6_AMUXA = 4, /* Analog mux bus A */ 1476 P10_6_AMUXB = 5, /* Analog mux bus B */ 1477 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1478 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1479 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 1480 P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 1481 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ 1482 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ 1483 P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ 1484 P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ 1485 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 1486 1487 /* P10.7 */ 1488 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1489 P10_7_AMUXA = 4, /* Analog mux bus A */ 1490 P10_7_AMUXB = 5, /* Analog mux bus B */ 1491 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1492 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1493 P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ 1494 P10_7_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ 1495 P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:77 */ 1496 P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:77 */ 1497 P10_7_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:1 */ 1498 P10_7_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:1 */ 1499 1500 /* P11.0 */ 1501 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1502 P11_0_AMUXA = 4, /* Analog mux bus A */ 1503 P11_0_AMUXB = 5, /* Analog mux bus B */ 1504 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1505 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1506 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 1507 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 1508 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 1509 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 1510 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 1511 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 1512 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1513 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 1514 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 1515 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 1516 P11_0_AUDIOSS1_CLK_I2S_IF = 22, /* Digital Active - audioss[1].clk_i2s_if:1 */ 1517 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1518 1519 /* P11.1 */ 1520 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1521 P11_1_AMUXA = 4, /* Analog mux bus A */ 1522 P11_1_AMUXB = 5, /* Analog mux bus B */ 1523 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1524 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1525 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 1526 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1527 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 1528 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 1529 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 1530 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 1531 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1532 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 1533 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 1534 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 1535 P11_1_AUDIOSS1_TX_SCK = 22, /* Digital Active - audioss[1].tx_sck:1 */ 1536 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1537 1538 /* P11.2 */ 1539 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1540 P11_2_AMUXA = 4, /* Analog mux bus A */ 1541 P11_2_AMUXB = 5, /* Analog mux bus B */ 1542 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1543 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1544 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 1545 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 1546 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 1547 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 1548 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 1549 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 1550 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1551 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 1552 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 1553 P11_2_AUDIOSS1_TX_WS = 22, /* Digital Active - audioss[1].tx_ws:1 */ 1554 1555 /* P11.3 */ 1556 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1557 P11_3_AMUXA = 4, /* Analog mux bus A */ 1558 P11_3_AMUXB = 5, /* Analog mux bus B */ 1559 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1560 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1561 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 1562 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1563 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 1564 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 1565 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 1566 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 1567 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1568 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 1569 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 1570 P11_3_AUDIOSS1_TX_SDO = 22, /* Digital Active - audioss[1].tx_sdo:1 */ 1571 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1572 1573 /* P11.4 */ 1574 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1575 P11_4_AMUXA = 4, /* Analog mux bus A */ 1576 P11_4_AMUXB = 5, /* Analog mux bus B */ 1577 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1578 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1579 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 1580 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 1581 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 1582 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 1583 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 1584 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 1585 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1586 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 1587 P11_4_AUDIOSS1_RX_SCK = 22, /* Digital Active - audioss[1].rx_sck:1 */ 1588 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1589 1590 /* P11.5 */ 1591 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1592 P11_5_AMUXA = 4, /* Analog mux bus A */ 1593 P11_5_AMUXB = 5, /* Analog mux bus B */ 1594 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1595 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1596 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 1597 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1598 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 1599 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 1600 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 1601 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 1602 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1603 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 1604 P11_5_AUDIOSS1_RX_WS = 22, /* Digital Active - audioss[1].rx_ws:1 */ 1605 1606 /* P11.6 */ 1607 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1608 P11_6_AMUXA = 4, /* Analog mux bus A */ 1609 P11_6_AMUXB = 5, /* Analog mux bus B */ 1610 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1611 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1612 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 1613 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 1614 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 1615 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 1616 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1617 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 1618 P11_6_AUDIOSS1_RX_SDI = 22, /* Digital Active - audioss[1].rx_sdi:1 */ 1619 1620 /* P11.7 */ 1621 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1622 P11_7_AMUXA = 4, /* Analog mux bus A */ 1623 P11_7_AMUXB = 5, /* Analog mux bus B */ 1624 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1625 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1626 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1627 1628 /* P12.0 */ 1629 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1630 P12_0_AMUXA = 4, /* Analog mux bus A */ 1631 P12_0_AMUXB = 5, /* Analog mux bus B */ 1632 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1633 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1634 P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ 1635 P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 1636 P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ 1637 P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ 1638 P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ 1639 P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ 1640 P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 1641 P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 1642 P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 1643 P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 1644 P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 1645 P12_0_SDHC1_CARD_EMMC_RESET_N = 26, /* Digital Active - sdhc[1].card_emmc_reset_n */ 1646 1647 /* P12.1 */ 1648 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1649 P12_1_AMUXA = 4, /* Analog mux bus A */ 1650 P12_1_AMUXB = 5, /* Analog mux bus B */ 1651 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1652 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1653 P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ 1654 P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 1655 P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ 1656 P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ 1657 P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ 1658 P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ 1659 P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 1660 P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 1661 P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 1662 P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 1663 P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 1664 P12_1_SDHC1_CARD_DETECT_N = 26, /* Digital Active - sdhc[1].card_detect_n */ 1665 1666 /* P12.2 */ 1667 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1668 P12_2_AMUXA = 4, /* Analog mux bus A */ 1669 P12_2_AMUXB = 5, /* Analog mux bus B */ 1670 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1671 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1672 P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ 1673 P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 1674 P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ 1675 P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ 1676 P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ 1677 P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ 1678 P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 1679 P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 1680 P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 1681 P12_2_SDHC1_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[1].card_mech_write_prot */ 1682 1683 /* P12.3 */ 1684 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1685 P12_3_AMUXA = 4, /* Analog mux bus A */ 1686 P12_3_AMUXB = 5, /* Analog mux bus B */ 1687 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1688 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1689 P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ 1690 P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 1691 P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ 1692 P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ 1693 P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ 1694 P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ 1695 P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 1696 P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 1697 P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 1698 P12_3_SDHC1_LED_CTRL = 26, /* Digital Active - sdhc[1].led_ctrl */ 1699 1700 /* P12.4 */ 1701 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1702 P12_4_AMUXA = 4, /* Analog mux bus A */ 1703 P12_4_AMUXB = 5, /* Analog mux bus B */ 1704 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1705 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1706 P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ 1707 P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 1708 P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ 1709 P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ 1710 P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ 1711 P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ 1712 P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ 1713 P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 1714 P12_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:1 */ 1715 P12_4_SDHC1_CARD_CMD = 26, /* Digital Active - sdhc[1].card_cmd */ 1716 1717 /* P12.5 */ 1718 P12_5_GPIO = 0, /* GPIO controls 'out' */ 1719 P12_5_AMUXA = 4, /* Analog mux bus A */ 1720 P12_5_AMUXB = 5, /* Analog mux bus B */ 1721 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1722 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1723 P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ 1724 P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 1725 P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ 1726 P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ 1727 P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ 1728 P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ 1729 P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ 1730 P12_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:1 */ 1731 P12_5_SDHC1_CLK_CARD = 26, /* Digital Active - sdhc[1].clk_card */ 1732 1733 /* P12.6 */ 1734 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1735 P12_6_AMUXA = 4, /* Analog mux bus A */ 1736 P12_6_AMUXB = 5, /* Analog mux bus B */ 1737 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1738 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1739 P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ 1740 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 1741 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ 1742 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ 1743 P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ 1744 P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ 1745 P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 1746 P12_6_SDHC1_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[1].card_if_pwr_en */ 1747 1748 /* P12.7 */ 1749 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1750 P12_7_AMUXA = 4, /* Analog mux bus A */ 1751 P12_7_AMUXB = 5, /* Analog mux bus B */ 1752 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1753 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1754 P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ 1755 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 1756 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ 1757 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ 1758 P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ 1759 P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ 1760 P12_7_SDHC1_IO_VOLT_SEL = 26, /* Digital Active - sdhc[1].io_volt_sel */ 1761 1762 /* P13.0 */ 1763 P13_0_GPIO = 0, /* GPIO controls 'out' */ 1764 P13_0_AMUXA = 4, /* Analog mux bus A */ 1765 P13_0_AMUXB = 5, /* Analog mux bus B */ 1766 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1767 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1768 P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 1769 P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ 1770 P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ 1771 P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ 1772 P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ 1773 P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ 1774 P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ 1775 P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ 1776 P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ 1777 P13_0_AUDIOSS1_CLK_I2S_IF = 22, /* Digital Active - audioss[1].clk_i2s_if:0 */ 1778 P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ 1779 P13_0_SDHC1_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[1].card_dat_3to0[0] */ 1780 1781 /* P13.1 */ 1782 P13_1_GPIO = 0, /* GPIO controls 'out' */ 1783 P13_1_AMUXA = 4, /* Analog mux bus A */ 1784 P13_1_AMUXB = 5, /* Analog mux bus B */ 1785 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1786 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1787 P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 1788 P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 1789 P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ 1790 P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ 1791 P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ 1792 P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ 1793 P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ 1794 P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ 1795 P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ 1796 P13_1_AUDIOSS1_TX_SCK = 22, /* Digital Active - audioss[1].tx_sck:0 */ 1797 P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ 1798 P13_1_SDHC1_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[1].card_dat_3to0[1] */ 1799 1800 /* P13.2 */ 1801 P13_2_GPIO = 0, /* GPIO controls 'out' */ 1802 P13_2_AMUXA = 4, /* Analog mux bus A */ 1803 P13_2_AMUXB = 5, /* Analog mux bus B */ 1804 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1805 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1806 P13_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 1807 P13_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:1 */ 1808 P13_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:95 */ 1809 P13_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:95 */ 1810 P13_2_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:1 */ 1811 P13_2_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:1 */ 1812 P13_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:1 */ 1813 P13_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:1 */ 1814 P13_2_AUDIOSS1_TX_WS = 22, /* Digital Active - audioss[1].tx_ws:0 */ 1815 P13_2_SDHC1_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[1].card_dat_3to0[2] */ 1816 1817 /* P13.3 */ 1818 P13_3_GPIO = 0, /* GPIO controls 'out' */ 1819 P13_3_AMUXA = 4, /* Analog mux bus A */ 1820 P13_3_AMUXB = 5, /* Analog mux bus B */ 1821 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1822 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1823 P13_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 1824 P13_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:1 */ 1825 P13_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:96 */ 1826 P13_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:96 */ 1827 P13_3_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:1 */ 1828 P13_3_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:1 */ 1829 P13_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:1 */ 1830 P13_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:1 */ 1831 P13_3_AUDIOSS1_TX_SDO = 22, /* Digital Active - audioss[1].tx_sdo:0 */ 1832 P13_3_SDHC1_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[1].card_dat_3to0[3] */ 1833 1834 /* P13.4 */ 1835 P13_4_GPIO = 0, /* GPIO controls 'out' */ 1836 P13_4_AMUXA = 4, /* Analog mux bus A */ 1837 P13_4_AMUXB = 5, /* Analog mux bus B */ 1838 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1839 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1840 P13_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 1841 P13_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:1 */ 1842 P13_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:97 */ 1843 P13_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:97 */ 1844 P13_4_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:1 */ 1845 P13_4_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:1 */ 1846 P13_4_SCB12_UART_RX = 18, /* Digital Active - scb[12].uart_rx:0 */ 1847 P13_4_SCB12_I2C_SCL = 19, /* Digital Active - scb[12].i2c_scl:0 */ 1848 P13_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:1 */ 1849 P13_4_AUDIOSS1_RX_SCK = 22, /* Digital Active - audioss[1].rx_sck:0 */ 1850 P13_4_SDHC1_CARD_DAT_7TO40 = 26, /* Digital Active - sdhc[1].card_dat_7to4[0] */ 1851 1852 /* P13.5 */ 1853 P13_5_GPIO = 0, /* GPIO controls 'out' */ 1854 P13_5_AMUXA = 4, /* Analog mux bus A */ 1855 P13_5_AMUXB = 5, /* Analog mux bus B */ 1856 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1857 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1858 P13_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 1859 P13_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:1 */ 1860 P13_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:98 */ 1861 P13_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:98 */ 1862 P13_5_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:1 */ 1863 P13_5_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:1 */ 1864 P13_5_SCB12_UART_TX = 18, /* Digital Active - scb[12].uart_tx:0 */ 1865 P13_5_SCB12_I2C_SDA = 19, /* Digital Active - scb[12].i2c_sda:0 */ 1866 P13_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:1 */ 1867 P13_5_AUDIOSS1_RX_WS = 22, /* Digital Active - audioss[1].rx_ws:0 */ 1868 P13_5_SDHC1_CARD_DAT_7TO41 = 26, /* Digital Active - sdhc[1].card_dat_7to4[1] */ 1869 1870 /* P13.6 */ 1871 P13_6_GPIO = 0, /* GPIO controls 'out' */ 1872 P13_6_AMUXA = 4, /* Analog mux bus A */ 1873 P13_6_AMUXB = 5, /* Analog mux bus B */ 1874 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1875 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1876 P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ 1877 P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */ 1878 P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */ 1879 P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */ 1880 P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */ 1881 P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */ 1882 P13_6_SCB12_UART_RTS = 18, /* Digital Active - scb[12].uart_rts:0 */ 1883 P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */ 1884 P13_6_AUDIOSS1_RX_SDI = 22, /* Digital Active - audioss[1].rx_sdi:0 */ 1885 P13_6_SDHC1_CARD_DAT_7TO42 = 26, /* Digital Active - sdhc[1].card_dat_7to4[2] */ 1886 1887 /* P13.7 */ 1888 P13_7_GPIO = 0, /* GPIO controls 'out' */ 1889 P13_7_AMUXA = 4, /* Analog mux bus A */ 1890 P13_7_AMUXB = 5, /* Analog mux bus B */ 1891 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1892 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1893 P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ 1894 P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ 1895 P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ 1896 P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ 1897 P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ 1898 P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ 1899 P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ 1900 P13_7_SDHC1_CARD_DAT_7TO43 = 26, /* Digital Active - sdhc[1].card_dat_7to4[3] */ 1901 1902 /* USBDP */ 1903 USBDP_GPIO = 0, /* GPIO controls 'out' */ 1904 1905 /* USBDM */ 1906 USBDM_GPIO = 0 /* GPIO controls 'out' */ 1907 } en_hsiom_sel_t; 1908 1909 #endif /* _GPIO_PSOC6_02_100_WLCSP_H_ */ 1910 1911 1912 /* [] END OF FILE */ 1913
