1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file spi.cypersonality 6* \version 3.0 7* 8* \brief 9* SPI personality description file. It Supports CAT1A, CAT1B and CAT1C family of devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright 2022 Cypress Semiconductor Corporation 14* SPDX-License-Identifier: Apache-2.0 15* 16* Licensed under the Apache License, Version 2.0 (the "License"); 17* you may not use this file except in compliance with the License. 18* You may obtain a copy of the License at 19* 20* http://www.apache.org/licenses/LICENSE-2.0 21* 22* Unless required by applicable law or agreed to in writing, software 23* distributed under the License is distributed on an "AS IS" BASIS, 24* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25* See the License for the specific language governing permissions and 26* limitations under the License. 27*****************************************************************************--> 28 29<Personality id="spi" name="SPI" version="3.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 30 <Dependencies> 31 <IpBlock name="mxscb,mxscb_ver2_s40e,mxs22scb"> 32 <Version major="1"/> 33 <Version major="2" /> 34 <Version major="4" /> 35 <Param name="SPI" value="1" /> 36 </IpBlock> 37 <Resource name="scb" /> 38 </Dependencies> 39 <ExposedMembers /> 40 <Parameters> 41 <!-- PDL documentation --> 42 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__scb__spi.html" linkText="Open SPI SCB Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 43 44 <!-- Internal --> 45 <ParamString id="version" name="version number" group="Internal" default="`${getVersion()}`" visible="false" editable="false" desc="" /> 46 <ParamString id="ipName" name="IP name" group="Internal" default="`${getIpBlockName()}`" visible="false" editable="false" desc="" /> 47 48 <!-- IP Block property DeepSleepCapable --> 49 <ParamBool id="DeepSleepCapable" name="DeepSleepCapable" group="Internal" default="`${DEEPSLEEP eq 1}`" visible="false" editable="false" desc="This parameter specifies the visibility of EnableWakeup parameter." /> 50 <ParamBool id="SlaveCapable" name="SlaveCapable" group="Internal" default="`${SPI_S eq 1}`" visible="false" editable="false" desc="This parameter specifies if SCB block supports Slave mode." /> 51 <ParamBool id="MasterCapable" name="MasterCapable" group="Internal" default="`${SPI_M eq 1}`" visible="false" editable="false" desc="This parameter specifies if SCB block supports Master mode." /> 52 53 <!--General--> 54 <ParamChoice id="ModeUser" name="Mode" group="General" default="`${SlaveCapable ? "CY_SCB_SPI_SLAVE" : "CY_SCB_SPI_MASTER"}`" visible="true" editable="`${SlaveCapable && MasterCapable}`" desc="This parameter specifies the mode of the SPI operation as: the slave or master."> 55 <Entry name="Slave" value="CY_SCB_SPI_SLAVE" visible="`${SlaveCapable}`" /> 56 <Entry name="Master" value="CY_SCB_SPI_MASTER" visible="`${MasterCapable}`" /> 57 </ParamChoice> 58 <ParamBool id="MasterMode" name="Master Mode" group="Internal" default="`${ModeUser eq CY_SCB_SPI_MASTER}`" visible="false" editable="false" desc="This parameter returns true when the mode is an SPI and it is a master." /> 59 60 <ParamChoice id="SubModeUser" name="Sub Mode" group="General" default="CY_SCB_SPI_MOTOROLA" visible="true" editable="`${!DeepSleepCapable}`" desc="This parameter specifies the sub-mode of the SPI as: Motorola, TI (Start Coincides), TI (Start Precedes), or National Semiconductor (Microwire)."> 61 <Entry name="Motorola" value="CY_SCB_SPI_MOTOROLA" visible="true" /> 62 <Entry name="TI (Start Coincides)" value="CY_SCB_SPI_TI_COINCIDES" visible="`${!DeepSleepCapable}`" /> 63 <Entry name="TI (Start Precedes)" value="CY_SCB_SPI_TI_PRECEDES" visible="`${!DeepSleepCapable}`" /> 64 <Entry name="National Semiconductor (Microwire)" value="CY_SCB_SPI_NATIONAL" visible="`${!DeepSleepCapable}`" /> 65 </ParamChoice> 66 67 <ParamChoice id="SclkModeUser" name="SCLK Mode" group="General" default="CY_SCB_SPI_CPHA0_CPOL0" visible="`${(SubModeUser eq CY_SCB_SPI_MOTOROLA)}`" editable="true" desc="This parameter specifies the serial clock phase (CPHA) and polarity (CPOL) combination."> 68 <Entry name="CPHA = 0, CPOL = 0" value="CY_SCB_SPI_CPHA0_CPOL0" visible="true" /> 69 <Entry name="CPHA = 0, CPOL = 1" value="CY_SCB_SPI_CPHA0_CPOL1" visible="true" /> 70 <Entry name="CPHA = 1, CPOL = 0" value="CY_SCB_SPI_CPHA1_CPOL0" visible="true" /> 71 <Entry name="CPHA = 1, CPOL = 1" value="CY_SCB_SPI_CPHA1_CPOL1" visible="true" /> 72 </ParamChoice> 73 <ParamChoice id="SclkMode" name="SCLK Mode" group="General" default="`${(SubModeUser eq CY_SCB_SPI_MOTOROLA) ? SclkModeUser : (SubModeUser eq CY_SCB_SPI_NATIONAL) ? "CY_SCB_SPI_CPHA0_CPOL0" : "CY_SCB_SPI_CPHA1_CPOL0"}`" visible="`${!(SubModeUser eq CY_SCB_SPI_MOTOROLA)}`" editable="false" desc="This parameter specifies the serial clock phase (CPHA) and polarity (CPOL) combination."> 74 <Entry name="CPHA = 0, CPOL = 0" value="CY_SCB_SPI_CPHA0_CPOL0" visible="true" /> 75 <Entry name="CPHA = 0, CPOL = 1" value="CY_SCB_SPI_CPHA0_CPOL1" visible="true" /> 76 <Entry name="CPHA = 1, CPOL = 0" value="CY_SCB_SPI_CPHA1_CPOL0" visible="true" /> 77 <Entry name="CPHA = 1, CPOL = 1" value="CY_SCB_SPI_CPHA1_CPOL1" visible="true" /> 78 </ParamChoice> 79 <ParamRange id="DataRate" name="Data Rate (kbps)" group="General" default="1000" min="1" max="`${hasConnection("spi_miso", 0) ? 25000 : 50000}`" resolution="1" visible="true" editable="true" desc="Data rate that SPI operates. The actual data rate may differ based on the available clock frequency and SPI settings. The range: 1-25000 kbps." /> 80 <!--Oversample--> 81 <ParamRange id="OvsFactor" name="Oversample" group="General" default="16" min="`${hasConnection("spi_miso", 0) ? 4 : 2}`" max="16" resolution="1" visible="`${MasterMode}`" editable="true" desc="This parameter defines how many SCB clocks are used to generate the SCLK period (only applicable for the master mode). When the oversample is even the first and second phase of the clock period are the same. Otherwise the first phase of the clock signal period is one SCB clock cycle longer than the second phase. The range: 4-16 (MISO utilized) and 2-16 (MISO is not utilized)." /> 82 83 <ParamBool id="EnableInputFilter" name="Enable Input Glitch Filter" group="General" default="false" visible="true" editable="true" desc="This parameter applies a digital 3-tap median filter to the SPI input lines." /> 84 <ParamBool id="EnableLateMisoSample" name="Enable MISO Late Sampling" group="General" default="true" visible="`${MasterMode}`" editable="true" desc="This option allows the master to sample the MISO signal by half of the SCLK period later (on the alternate serial clock edge). Late sampling addresses the round-trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master." /> 85 <ParamBool id="EnableFreeRunSclk" name="SCLK Free Running" group="General" default="false" visible="`${MasterMode}`" editable="true" desc="This parameter allows the master to generate SCLK continually. It is useful when the master SCLK is connected to the slave device which uses it for functional operation rather than only the SPI functionality." /> 86 <ParamChoice id="Parity" name="Parity" group="General" default="CY_SCB_SPI_PARITY_NONE" visible="`${((version > 1) || (ipName eq "mxs22scb")) && (SubModeUser eq CY_SCB_SPI_MOTOROLA)}`" editable="true" desc="This parameter specifies the parity ( None, Even, Odd )."> 87 <Entry name="No Parity" value="CY_SCB_SPI_PARITY_NONE" visible="true" /> 88 <Entry name="Even Parity" value="CY_SCB_SPI_PARITY_EVEN" visible="true" /> 89 <Entry name="Odd Parity" value="CY_SCB_SPI_PARITY_ODD" visible="true" /> 90 </ParamChoice> 91 <ParamBool id="DropOnParityError" name="Drop On Parity Error" group="General" default="false" visible="`${(((version > 1) || (ipName eq "mxs22scb"))|| (ipName eq "mxs22scb")) && ((Parity eq CY_SCB_SPI_PARITY_EVEN) || (Parity eq CY_SCB_SPI_PARITY_ODD))}`" editable="true" desc="This parameter enables the hardware to drop data in the RX FIFO when a parity error is detected." /> 92 <ParamBool id="EnableWakeup" name="Enable Wakeup from Deep Sleep Mode" group="General" default="false" visible="`${DeepSleepCapable}`" editable="true" desc="This parameter enables wake-up from Deep Sleep on an SPI slave-select event." /> 93 94 <!--Data Configuration--> 95 <ParamChoice id="BitsOrder" name="Bit Order" group="Data Configuration" default="MSB_FIRST" visible="true" editable="true" desc="This parameter defines the direction in which the serial data is transmitted. When set to the MSB first, the most-significant bit is transmitted first. When set to the LSB first, the least-significant bit is transmitted first."> 96 <Entry name="MSB First" value="MSB_FIRST" visible="true" /> 97 <Entry name="LSB First" value="LSB_FIRST" visible="true" /> 98 </ParamChoice> 99 <ParamRange id="RxDataWidth" name="RX Data Width" group="Data Configuration" default="8" min="4" max="`${((version eq 1) && (ipName ne "mxs22scb")) ? 16 : 32}`" resolution="1" visible="true" editable="true" desc="This option defines the width of a single data element for the RX direction in bits. This number must match with TX Word Width for all SPI sub-modes except National Semiconductor (Microwire)." /> 100 <ParamRange id="TxDataWidth" name="TX Data Width" group="Data Configuration" default="8" min="4" max="`${((version eq 1) && (ipName ne "mxs22scb")) ? 16 : 32}`" resolution="1" visible="true" editable="true" desc="This option defines the width of a single data element for the TX direction in bits. This number must match with RX Word Width for all SPI sub-modes except National Semiconductor (Microwire)." /> 101 <ParamRange id="DataWidth" name="Data Width" group="Internal" default="`${(RxDataWidth > TxDataWidth) ? RxDataWidth : TxDataWidth}`" min="4" max="`${((version eq 1) && (ipName ne "mxs22scb")) ? 16 : 32}`" resolution="1" visible="false" editable="false" desc="This option defines the data width." /> 102 103 <!--Slave Select--> 104 <ParamBool id="DeassertSelectLine" name="Deassert SS Between Data Element" group="Slave Select" default="false" visible="`${MasterMode}`" editable="true" desc="This parameter determines if individual data transfers are separated by the slave select de-selection." /> 105 <ParamChoice id="SetupDelay" name="Setup Delay" group="Slave Select" default="false" visible="`${((version > 1) || (ipName eq "mxs22scb")) && ((MasterMode) ? ((SubModeUser eq CY_SCB_SPI_MOTOROLA) ? ((OvsFactor > 2) ? (!EnableFreeRunSclk) : false) : false) : false)}`" editable="true" desc="This parameter indicates the SPI SELECT setup delay."> 106 <Entry name="0.75 Clock Cycles" value="false" visible="true" /> 107 <Entry name="1.75 Clock Cycles" value="true" visible="true" /> 108 </ParamChoice> 109 <ParamChoice id="HoldDelay" name="Hold Delay" group="Slave Select" default="false" visible="`${((version > 1) || (ipName eq "mxs22scb")) && ((MasterMode) ? ((SubModeUser eq CY_SCB_SPI_MOTOROLA) ? ((OvsFactor > 2) ? (!EnableFreeRunSclk) : false) : false) : false)}`" editable="true" desc="This parameter indicates the SPI SELECT hold delay."> 110 <Entry name="0.75 Clock Cycles" value="false" visible="true" /> 111 <Entry name="1.75 Clock Cycles" value="true" visible="true" /> 112 </ParamChoice> 113 <ParamChoice id="InterdataframeDelay" name="Inter-dataframe Delay" group="Slave Select" default="false" visible="`${((version > 1) || (ipName eq "mxs22scb")) && ((MasterMode) ? ((SubModeUser eq CY_SCB_SPI_MOTOROLA) ? ((OvsFactor > 2) ? (!EnableFreeRunSclk) : false) : false) : false)}`" editable="true" desc="This parameter indicates the SPI SELECT inter-dataframe delay."> 114 <Entry name="1.5 Clock Cycles" value="false" visible="true" /> 115 <Entry name="2.5 Clock Cycles" value="true" visible="true" /> 116 </ParamChoice> 117 118 <!-- SS visible options --> 119 <ParamBool id="isConnectableSel0" name="isConnectableSel0" group="Internal" default="`${hasVisibleOption("spi_select0[0]")}`" visible="false" editable="false" desc="This parameter determines if SS0 has valid connections." /> 120 <ParamBool id="isConnectableSel1" name="isConnectableSel1" group="Internal" default="`${hasVisibleOption("spi_select1[0]")}`" visible="false" editable="false" desc="This parameter determines if SS1 has valid connections." /> 121 <ParamBool id="isConnectableSel2" name="isConnectableSel2" group="Internal" default="`${hasVisibleOption("spi_select2[0]")}`" visible="false" editable="false" desc="This parameter determines if SS2 has valid connections." /> 122 <ParamBool id="isConnectableSel3" name="isConnectableSel3" group="Internal" default="`${hasVisibleOption("spi_select3[0]")}`" visible="false" editable="false" desc="This parameter determines if SS3 has valid connections." /> 123 124 <!-- Slave Select polarities --> 125 <ParamChoice id="Ss0Polarity" name="SS0 Polarity" group="Slave Select" default="CY_SCB_SPI_ACTIVE_LOW" visible="`${isConnectableSel0}`" editable="true" desc="This parameter defines the active polarity of the slave-select 0 signal as Active Low or Active High."> 126 <Entry name="Active Low" value="CY_SCB_SPI_ACTIVE_LOW" visible="true" /> 127 <Entry name="Active High" value="CY_SCB_SPI_ACTIVE_HIGH" visible="true" /> 128 </ParamChoice> 129 <ParamChoice id="Ss1Polarity" name="SS1 Polarity" group="Slave Select" default="CY_SCB_SPI_ACTIVE_LOW" visible="`${isConnectableSel1}`" editable="true" desc="This parameter defines the active polarity of the slave-select 1 signal as Active Low or Active High."> 130 <Entry name="Active Low" value="CY_SCB_SPI_ACTIVE_LOW" visible="true" /> 131 <Entry name="Active High" value="CY_SCB_SPI_ACTIVE_HIGH" visible="true" /> 132 </ParamChoice> 133 <ParamChoice id="Ss2Polarity" name="SS2 Polarity" group="Slave Select" default="CY_SCB_SPI_ACTIVE_LOW" visible="`${isConnectableSel2}`" editable="true" desc="This parameter defines the active polarity of the slave-select 2 signal as Active Low or Active High."> 134 <Entry name="Active Low" value="CY_SCB_SPI_ACTIVE_LOW" visible="true" /> 135 <Entry name="Active High" value="CY_SCB_SPI_ACTIVE_HIGH" visible="true" /> 136 </ParamChoice> 137 <ParamChoice id="Ss3Polarity" name="SS3 Polarity" group="Slave Select" default="CY_SCB_SPI_ACTIVE_LOW" visible="`${isConnectableSel3}`" editable="true" desc="This parameter defines the active polarity of the slave-select 3 signal as Active Low or Active High."> 138 <Entry name="Active Low" value="CY_SCB_SPI_ACTIVE_LOW" visible="true" /> 139 <Entry name="Active High" value="CY_SCB_SPI_ACTIVE_HIGH" visible="true" /> 140 </ParamChoice> 141 142 <!-- SPI Slave data rate calculation parameters --> 143 <ParamRange id="TDSO" name="TDSO" group="Internal" default="50" min="0" max="255" resolution="1" visible="false" editable="false" desc="TDSO, 002-10490 Rev. *C: SID171 (units ns)." /> 144 <ParamRange id="F_SPI_SLAVE_IC" name="F_SPI_SLAVE_IC" group="Internal" default="15" min="0" max="255" resolution="1" visible="false" editable="false" desc="002-10490 Rev. *C: SID166A (units MHz)." /> 145 <ParamRange id="T_DSO_INTERNAL" name="T_DSO_INTERNAL" group="Internal" default="`${TDSO - 3 * 10}`" min="0" max="255" resolution="1" visible="false" editable="true" desc="Tdso = Tdso_internal + (3 * Tscbclk), where Tscbclk = 10ns (units ns)." /> 146 <ParamRange id="T_MASTER_DELAYS" name="T_MASTER_DELAYS" group="Internal" default="`${(1000.0 / F_SPI_SLAVE_IC) - TDSO}`" min="0" max="1000" resolution="0.000001" visible="false" editable="false" desc="Calculate time left for master delays to meet SID166A FSPI_IC." /> 147 <ParamRange id="scbClocksToOutput" name="scbClocksToOutput" group="Internal" default="`${EnableInputFilter ? 4 : 3}`" min="0" max="255" resolution="1" visible="false" editable="false" desc="The number of scb clocks to output." /> 148 <ParamRange id="spiClkPeriod" name="spiClkPeriod" group="Internal" default="`${1000000 / DataRate}`" min="0" max="1000000" resolution="1" visible="false" editable="false" desc="SPI SCLK period (units ns)." /> 149 150 <!-- Get SPI Slave desired clock --> 151 <ParamString id="hfclockperi" name="PCLK Destination Clock" group="Internal" default="srss[0].clock[0].periclk[0]" visible="false" editable="false" desc="String variable used for source peri clock." /> 152 <ParamString id="hfclock1" name="PCLK Destination Clock" group="Internal" default="srss[0].clock[0].hfclk[1]" visible="false" editable="false" desc="String variable used for source HF clock1." /> 153 <ParamString id="hfclock2" name="PCLK Destination Clock" group="Internal" default="srss[0].clock[0].hfclk[2]" visible="false" editable="false" desc="String variable used for source HF clock2." /> 154 155 <ParamString id="hfclocksource" name="PCLK Destination" group="Internal" default="`${((ipName ne "mxs22scb") ? ((version eq 1) ? hfclockperi : ((version eq 4) ? hfclock1 : hfclock2)) : hfclock1) }`" visible="false" editable="false" desc="Generates PCLK connection define." /> 156 157 <ParamString id="ClkPeri" name="ClkPeri" group="Internal" default="`${hfclocksource}`" visible="false" editable="false" desc="" /> 158 <ParamBool id="isClkPeriUsed" name="isClkPeriUsed" group="Internal" default="`${isBlockUsed(ClkPeri)}`" visible="false" editable="false" desc="" /> 159 <ParamRange id="ClkPeriHz" name="ClkPeriHz" group="Internal" default="`${isClkPeriUsed ? getExposedMember(ClkPeri, "frequency") : 0}`" min="0" max="200000000" resolution="1" visible="false" editable="false" desc="ClkPeri frequency in Hz." /> 160 <ParamRange id="spiTdso" name="spiTdso" group="Internal" default="`${(spiClkPeriod / 2) - T_DSO_INTERNAL - T_MASTER_DELAYS}`" min="-67" max="1000000" resolution="0.000001" visible="false" editable="false" desc="Time left for tDSO (units ns) that is function of SCB clock." /> 161 <ParamRange id="SlaveClkHzTmp" name="SlaveClkHzTmp" group="Internal" default="`${(spiTdso > 0) ? ((1000000000 * scbClocksToOutput) / spiTdso) : ClkPeriHz}`" min="1" max="4294967295" resolution="1" visible="false" editable="false" desc="Slave clock to operate with desired baud rate in Hz (not adjusted)." /> 162 <ParamRange id="SlaveClkHz" name="SlaveClkHz" group="Internal" default="`${(SlaveClkHzTmp > ClkPeriHz) ? ClkPeriHz : SlaveClkHzTmp}`" min="0" max="200000000" resolution="1" visible="false" editable="false" desc="Slave SCB clock to operate with desired baud rate in Hz." /> 163 164 <!-- Get SPI Master desired clock --> 165 <ParamRange id="MasterClkHz" name="MasterClkHz" group="Internal" default="`${DataRate * OvsFactor * 1000}`" min="1" max="400000000" resolution="1" visible="false" editable="false" desc="Master clock to operate with desired baud rate in kHz." /> 166 167 <!-- Connections --> 168 <ParamSignal port="clock[0]" name="Clock" group="Connections" visible="`${hasVisibleOption("clock[0]")}`" desc="Clock that operates this block." canBeEmpty="false" > 169 <Constraint type="REQUIRE" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_.*" valid="`${!MasterMode}`" > 170 <Parameter id="intDivider" severity="ERROR" reason="The clock frequency must be `${SlaveClkHz / 1000}` kHz to operate with data rate `${DataRate}` kbps." valid="true"> 171 <Fixed 172 value= "`${isClkPeriUsed ? floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / SlaveClkHz) : 1}`" /> 173 </Parameter> 174 </Constraint> 175 <Constraint type="REQUIRE" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_.*" valid="`${MasterMode}`" > 176 <Parameter id="intDivider" severity="ERROR" reason="The clock frequency must be `${MasterClkHz / 1000}` kHz to operate with data rate `${DataRate}` kbps." valid="true"> 177 <Fixed 178 value= "`${ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / MasterClkHz)}`" /> 179 </Parameter> 180 </Constraint> 181 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_(16.5|24.5).*" valid="true" > 182 <Parameter id="fracDivider" severity="ERROR" reason="Fractional divider must be 0 for SPI interface."> 183 <Fixed value= "0" /> 184 </Parameter> 185 </Constraint> 186 </ParamSignal> 187 188 <ParamSignal port="clock_scb_en[0]" name="Clock" group="Connections" visible="`${hasVisibleOption("clock_scb_en[0]")}`" desc="Clock that operates this block." canBeEmpty="false" > 189 <Constraint type="REQUIRE" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_.*" valid="`${!MasterMode}`" > 190 <Parameter id="intDivider" severity="ERROR" reason="The clock frequency must be `${SlaveClkHz / 1000}` kHz to operate with data rate `${DataRate}` kbps." valid="true"> 191 <Fixed 192 value= "`${isClkPeriUsed ? floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / SlaveClkHz) : 1}`" /> 193 </Parameter> 194 </Constraint> 195 <Constraint type="REQUIRE" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_.*" valid="`${MasterMode}`" > 196 <Parameter id="intDivider" severity="ERROR" reason="The clock frequency must be `${MasterClkHz / 1000}` kHz to operate with data rate `${DataRate}` kbps." valid="true"> 197 <Fixed 198 value= "`${ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / MasterClkHz)}`" /> 199 </Parameter> 200 </Constraint> 201 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_(16.5|24.5).*" valid="true" > 202 <Parameter id="fracDivider" severity="ERROR" reason="Fractional divider must be 0 for SPI interface."> 203 <Fixed value= "0" /> 204 </Parameter> 205 </Constraint> 206 </ParamSignal> 207 208 <!-- Drive mode selection --> 209 <ParamString id="DmMOSI" name="DmMOSI" group="Internal" default="`${MasterMode ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" visible="false" editable="false" desc="Drive mode " /> 210 <ParamString id="DmMOSIMsg" name="sourceClock" group="Internal" default="Drive Mode must be set to '`${MasterMode ? "Strong Drive. Input buffer off" : "Digital High-Z. Input buffer on"}`'" visible="false" editable="false" desc="Drive mode error message." /> 211 <ParamString id="DmMISO" name="DmMOSI" group="Internal" default="`${!MasterMode ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" visible="false" editable="false" desc="Drive mode " /> 212 <ParamString id="DmMISOMsg" name="sourceClock" group="Internal" default="Drive Mode must be set to '`${!MasterMode ? "Strong Drive. Input buffer off" : "Digital High-Z. Input buffer on"}`'" visible="false" editable="false" desc="Drive mode error message." /> 213 214 <!-- SCLK, MOSI and MISO connections --> 215 <ParamBool id="hasConnectionSclk" name="hasConnectionSclk" group="Internal" default="`${hasVisibleOption("spi_clk[0]")}`" visible="false" editable="false" desc="This parameter determines if SCLK has valid connections." /> 216 <ParamBool id="hasConnectionMosi" name="hasConnectionMosi" group="Internal" default="`${hasVisibleOption("spi_mosi[0]")}`" visible="false" editable="false" desc="This parameter determines if MOSI has valid connections." /> 217 <ParamBool id="hasConnectionMiso" name="hasConnectionMiso" group="Internal" default="`${hasVisibleOption("spi_miso[0]")}`" visible="false" editable="false" desc="This parameter determines if MISO has valid connections." /> 218 219 <ParamSignal port="spi_clk[0]" name="SCLK" group="Connections" visible="`${MasterMode ? hasConnectionSclk : true}`" desc="The Serial Clock (SCLK) from the master to slave device." canBeEmpty="`${MasterMode}`"> 220 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 221 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 222 <Fixed value="`${DmMOSI}`" /> 223 </Parameter> 224 </Constraint> 225 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 226 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 227 <Fixed value="`${DmMOSI}`" /> 228 </Parameter> 229 </Constraint> 230 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 231 </ParamSignal> 232 233 <ParamSignal port="spi_mosi[0]" name="MOSI" group="Connections" visible="`${hasConnectionMosi}`" desc="The Master Output Slave Input (MOSI) signal between the master and slave devices." canBeEmpty="true" > 234 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 235 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 236 <Fixed value="`${DmMOSI}`" /> 237 </Parameter> 238 </Constraint> 239 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 240 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 241 <Fixed value="`${DmMOSI}`" /> 242 </Parameter> 243 </Constraint> 244 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 245 </ParamSignal> 246 247 <ParamSignal port="spi_miso[0]" name="MISO" group="Connections" visible="`${hasConnectionMiso}`" desc="The Master Input Slave Output (MOSI) signal between the slave and master devices." canBeEmpty="true" > 248 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 249 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 250 <Fixed value="`${DmMISO}`" /> 251 </Parameter> 252 </Constraint> 253 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 254 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 255 <Fixed value="`${DmMISO}`" /> 256 </Parameter> 257 </Constraint> 258 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 259 </ParamSignal> 260 261 <ParamSignal port="spi_select0[0]" name="SS0" group="Connections" visible="`${isConnectableSel0}`" desc="The Master Output / Slave Input Slave Select (SS) signal. The master uses SS signal to enable Slave for the following communication." canBeEmpty="true" > 262 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 263 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 264 <Fixed value="`${DmMOSI}`" /> 265 </Parameter> 266 </Constraint> 267 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 268 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 269 <Fixed value="`${DmMOSI}`" /> 270 </Parameter> 271 </Constraint> 272 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 273 </ParamSignal> 274 275 <ParamSignal port="spi_select1[0]" name="SS1" group="Connections" visible="`${isConnectableSel1}`" desc="The Master Output / Slave Input Slave Select (SS) signal. The master uses SS signal to enable Slave for the following communication." canBeEmpty="true" > 276 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 277 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 278 <Fixed value="`${DmMOSI}`" /> 279 </Parameter> 280 </Constraint> 281 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 282 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 283 <Fixed value="`${DmMOSI}`" /> 284 </Parameter> 285 </Constraint> 286 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 287 </ParamSignal> 288 289 <ParamSignal port="spi_select2[0]" name="SS2" group="Connections" visible="`${isConnectableSel2}`" desc="The Master Output / Slave Input Slave Select (SS) signal. The master uses SS signal to enable Slave for the following communication." canBeEmpty="true" > 290 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 291 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 292 <Fixed value="`${DmMOSI}`" /> 293 </Parameter> 294 </Constraint> 295 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 296 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 297 <Fixed value="`${DmMOSI}`" /> 298 </Parameter> 299 </Constraint> 300 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 301 </ParamSignal> 302 303 <ParamSignal port="spi_select3[0]" name="SS3" group="Connections" visible="`${isConnectableSel3}`" desc="The Master Output / Slave Input Slave Select (SS) signal. The master uses SS signal to enable Slave for the following communication." canBeEmpty="true" > 304 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 305 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 306 <Fixed value="`${DmMOSI}`" /> 307 </Parameter> 308 </Constraint> 309 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 310 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 311 <Fixed value="`${DmMOSI}`" /> 312 </Parameter> 313 </Constraint> 314 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 315 </ParamSignal> 316 317 <ParamSignal port="tr_rx_req[0]" name="RX Trigger Output" group="Connections" visible="`${MasterMode ? hasConnectionMiso : hasConnectionMosi}`" desc="Connects SCB RX trigger output to the DMA. Configure RX FIFO Level to define this output behavior." canBeEmpty="true" > 318 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 319 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 320 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 321 </Parameter> 322 </Constraint> 323 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 324 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 325 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 326 </Parameter> 327 </Constraint> 328 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 329 </ParamSignal> 330 331 <ParamSignal port="tr_tx_req[0]" name="TX Trigger Output" group="Connections" visible="`${MasterMode ? hasConnectionMosi : hasConnectionMiso}`" desc="Connects SCB TX trigger output to the DMA. Configure TX FIFO Level to define this output behavior." canBeEmpty="true" > 332 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 333 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 334 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 335 </Parameter> 336 </Constraint> 337 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 338 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 339 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 340 </Parameter> 341 </Constraint> 342 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 343 </ParamSignal> 344 345 <!-- Clock Frequency --> 346 <ParamString id="sourceClock" name="sourceClock" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? (getBlockFromSignal("clock[0]")) : (getBlockFromSignal("clock_scb_en[0]"))}`" visible="false" editable="false" desc="Source Clock Resource" /> 347 <ParamRange id="scbClkHz" name="scbClkHz" group="Internal" default="`${isClkPeriUsed ? getExposedMember(sourceClock, "frequency") : 0}`" min="0" max="200000000" resolution="1" visible="false" editable="false" desc="SCB clock frequency in kHz" /> 348 349 <!-- Actual data rate notes --> 350 <ParamString id="SlaveActDataRateNote" name="ActualDataRateNoteSlave" group="Internal" default="This is the theoretical data rate calculated with the assumption that the master captures data on a half SCLK period after the driving edge (normal sample). If the master captures data a half SCLK period later (late sampling) then the actual data rate is twice what is displayed. To determine the data rate for your system, consult the selected device TRM." visible="false" editable="false" desc="Actual Data Rate Note Slave" /> 351 <ParamString id="MasterActDataRateNote" name="ActualDataRateNoteMaster" group="Internal" default="The actual data rate is calculated based only on the master configuration. To determine the data rate for your system, consult the selected device TRM." visible="false" editable="false" desc="Actual Data Rate Note Master." /> 352 353 <!-- Slave actual data rate calculations --> 354 <ParamRange id="tDSO_SCB" name="tDSO" group="Internal" default="`${isClkPeriUsed ? scbClocksToOutput * (1000000000 / scbClkHz) : 0}`" min="0" max="4294967295" resolution="0.000001" visible="false" editable="false" desc="Get tDSO based on SCB clock (units ns)." /> 355 <ParamRange id="spiRoundTripDelay" name="spiRoundTripDelay" group="Internal" default="`${tDSO_SCB + T_DSO_INTERNAL + T_MASTER_DELAYS}`" min="0" max="4294967295" resolution="0.000001" visible="false" editable="false" desc="Get SCL to MISO round trip delay (units ns)." /> 356 357 <ParamRange id="SlaveActualDataRate" name="Actual Slave data rate (kbps)" group="Internal" default="`${isClkPeriUsed ? 1000000 / (2 * spiRoundTripDelay) : 0}`" min="0" max="4294967295" resolution="0.001" visible="false" editable="false" desc="Actual Slave data rate (kbps)." /> 358 359 <!-- Master actual data rate calculations --> 360 <ParamRange id="MasterActualDataRate" name="MasterActualDataRate" group="Internal" default="`${(scbClkHz / OvsFactor) / 1000.0}`" min="0" max="4294967295" resolution="0.001" visible="false" editable="false" desc="Actual Master data rate (kbps)." /> 361 362 <!-- Data Rate and Clock output--> 363 <ParamRange id="actualDataRate" name="Actual Data Rate (kbps)" group="Data Rate" default="`${MasterMode ? MasterActualDataRate : SlaveActualDataRate}`" min="0" max="4294967295" resolution="0.001" visible="true" editable="false" desc="`${MasterMode ? MasterActDataRateNote : SlaveActDataRateNote}`" /> 364 365 <ParamString id="ClkFreq" name="Clock Frequency" group="Data Rate" default="`${(scbClkHz < 1000000) ? (scbClkHz / 1000.0) . " kHz" : (scbClkHz / 1000000.0) . " MHz"}`" visible="true" editable="false" desc="Frequency of the connected clock" /> 366 367 <!-- Hardware buffer size (defines FIFO size) --> 368 <ParamRange id="hwBufferSize" name="Hardware Buffer Size" group="Internal" default="`${lookupExpression("EZ_DATA_NR")}`" min="0" max="512" resolution="1" visible="false" editable="false" desc="Hardware buffer size." /> 369 <ParamRange id="FifoLevelByte" name="FIFO Level (Byte)" group="Internal" default="`${(hwBufferSize / 2) - 1}`" min="1" max="512" resolution="1" visible="false" editable="false" desc="FIFO Level for byte entry." /> 370 <ParamRange id="FifoLevelHalfword" name="FIFO Level (Halfword)" group="Internal" default="`${(hwBufferSize / 4) - 1}`" min="1" max="512" resolution="1" visible="false" editable="false" desc="FIFO Level for halfword /byte entry." /> 371 <ParamRange id="FifoLevelWord" name="FIFO Level (Word)" group="Internal" default="`${(hwBufferSize / 8) - 1}`" min="1" max="512" resolution="1" visible="false" editable="false" desc="FIFO Level for word entry." /> 372 <ParamRange id="FifoLevelMax" name="FIFO Level Max" group="Internal" default="`${(DataWidth <= 8) ? FifoLevelByte : ((DataWidth <= 16) ? FifoLevelHalfword : FifoLevelWord)}`" min="1" max="512" resolution="1" visible="false" editable="false" desc="FIFO Level for byte entry." /> 373 374 <!--Trigger Level--> 375 <ParamRange id="RxTriggerLevel" name="RX FIFO Level" group="Trigger Level" default="63" min="0" max="`${FifoLevelMax}`" resolution="1" visible="true" editable="true" desc="This parameter determines behavior of signal which drives the RX FIFO Above Level interrupt source and RX trigger output as follows: the signal remains active until the number of data elements in the RX FIFO is greater than the value of RX FIFO Level. For example, the RX FIFO has 8 data elements and the RX FIFO level is 0. The signal remains active until all data elements are read from the RX FIFO. The range: 0 – `${FifoLevelByte}` (when TX/RX Data Width less or equal 8), and 0 - `${FifoLevelHalfword}` otherwise." /> 376 377 <ParamRange id="TxTriggerLevel" name="TX FIFO Level" group="Trigger Level" default="63" min="0" max="`${FifoLevelMax}`" resolution="1" visible="true" editable="true" desc="This parameter determines the behavior of the signal which drives the TX FIFO Below Level interrupt source and TX trigger output as follows: until the number of data elements in the TX FIFO is less than the value of the TX FIFO level. For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level is 7. The signal remains active until TX FIFO has 7 data elements. The range: 0 – `${FifoLevelByte}` (when TX/RX Data Width less or equal 8), and 0 - `${FifoLevelHalfword}` otherwise." /> 378 379 <!-- API Mode --> 380 <ParamChoice id="ApiMode" name="API Mode" group="API Mode" default="HIGH_LEVEL" visible="true" editable="true" desc="This parameter defines which API set will be used during driver operation. High Level means driver controls interrupt sources and Cy_SCB_SPI_Interrupt function must be called in the interrupt handler hooked to NVIC. Low Level means that the user configures interrupt sources and implements own interrupt handler or do not use interrupt at all."> 381 <Entry name="High Level" value="HIGH_LEVEL" visible="true" /> 382 <Entry name="Low Level" value="LOW_LEVEL" visible="true" /> 383 </ParamChoice> 384 <ParamBool id="ConfigIntr" name="ConfigIntr" group="Internal" default="`${ApiMode eq LOW_LEVEL}`" visible="false" editable="false" desc="This parameter specifies the visibility of all RX Interrupt Sources parameter." /> 385 386 <!--RX Interrupt Sources--> 387 <ParamBool id="IntrRxNotEmpty" name="RX FIFO not Empty" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO not-empty interrupt source to trigger the interrupt output." /> 388 <ParamBool id="IntrRxTrigger" name="RX FIFO Above Level" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO above-level interrupt source to trigger the interrupt output." /> 389 <ParamBool id="IntrRxFull" name="RX FIFO Full" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO full interrupt source to trigger the interrupt output." /> 390 <ParamBool id="IntrRxOverflow" name="RX FIFO Overflow" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO overflow interrupt source to trigger the interrupt output." /> 391 <ParamBool id="IntrRxUnderflow" name="RX FIFO Underflow" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO underflow interrupt source to trigger the interrupt output." /> 392 393 <ParamRange id="IntrRxMask" name="INTR_RX_MASK" group="Internal" default="`${ConfigIntr ? (IntrRxTrigger ? 0x1 : 0) + (IntrRxNotEmpty ? 0x4 : 0) + (IntrRxFull ? 0x8 : 0) + (IntrRxOverflow ? 0x20 : 0) + (IntrRxUnderflow ? 0x40 : 0) : 0}`" min="0" max="4294967295" resolution="1" visible="false" editable="false" desc="This parameter defines the SPI RX interrupt mask to be written into the SCB.INTR_RX_MASK register." /> 394 395 <!--TX Interrupt Sources--> 396 <ParamBool id="IntrTxEmpty" name="TX FIFO Empty" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO empty interrupt source to trigger the interrupt output." /> 397 <ParamBool id="IntrTxTrigger" name="TX FIFO Below Level" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO below-level interrupt source to trigger the interrupt output." /> 398 <ParamBool id="IntrTxNotFull" name="TX FIFO not Full" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO not-full interrupt source to trigger the interrupt output." /> 399 <ParamBool id="IntrTxOverflow" name="TX FIFO Overflow" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO overflow interrupt source to trigger the interrupt output." /> 400 <ParamBool id="IntrTxUnderflow" name="TX FIFO Underflow" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO underflow interrupt source to trigger the interrupt output." /> 401 402 <ParamRange id="IntrTxMask" name="INTR_TX_MASK" group="Internal" default="`${ConfigIntr ? (IntrTxTrigger ? 0x1 : 0) + (IntrTxNotFull ? 0x2 : 0) + (IntrTxEmpty ? 0x10 : 0) + (IntrTxOverflow ? 0x20 : 0) + (IntrTxUnderflow ? 0x40 : 0) : 0}`" min="0" max="4294967295" resolution="1" visible="false" editable="false" desc="This parameter defines the SPI TX interrupt mask to be written into the SCB.INTR_TX_MASK register." /> 403 404 <!--Master / Slave Interrupt Source--> 405 <ParamBool id="IntrMasterSpiDone" name="SPI Done" group="Master Interrupt Source" default="false" visible="`${ConfigIntr && MasterMode}`" editable="true" desc="This parameter enables the SPI done interrupt source to trigger the interrupt output." /> 406 <ParamBool id="IntrSlaveBusError" name="SPI Bus Error" group="Slave Interrupt Source" default="false" visible="`${ConfigIntr && !MasterMode}`" editable="true" desc="This parameter enables the SPI bus error interrupt source to trigger the interrupt output." /> 407 408 <ParamRange id="IntrMasterSlaveMask" name="INTR_MS_MASK" group="Internal" default="`${ConfigIntr ? (((MasterMode && IntrMasterSpiDone) ? 0x200 : 0) + ((!MasterMode && IntrSlaveBusError) ? 0x800 : 0)) : 0}`" min="0" max="4294967295" resolution="1" visible="false" editable="false" desc="This parameter defines the SPI slave or master interrupt mask to be written into the SCB.INTR_M_MASK or SCB.INTR_S_MASK register." /> 409 410 <!-- Advanced --> 411 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 412 413 <!-- SCB instance number --> 414 <ParamString id="InstNumber" name="InstNumber" group="Internal" default="`${getInstNumber("scb")}`" visible="false" editable="false" desc="SCB Instance name number." /> 415 416 <!-- Peripheral clock divider connection --> 417 <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? (hasConnection("clock", 0) && isBlockUsed(sourceClock)) : (hasConnection("clock_scb_en", 0) && isBlockUsed(sourceClock)) }`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 418 419 <ParamString id="pclkSCBClockString" name="PCLK Destination Clock" group="Internal" default="PCLK_SCB`${InstNumber}`_CLOCK" visible="false" editable="false" desc="String variable used for PCLK_SCB_CLOCK." /> 420 <ParamString id="pclkSCBClockSCBENString" name="PCLK Destination Clock" group="Internal" default="PCLK_SCB`${InstNumber}`_CLOCK_SCB_EN" visible="false" editable="false" desc="String variable used only for PCLK_SCB_CLOCK_SCB_EN." /> 421 422 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? pclkSCBClockString : pclkSCBClockSCBENString }`" visible="false" editable="false" desc="Generates PCLK connection define." /> 423 </Parameters> 424 425 <DRCs> 426 <!--RxDataWidth and $TxDataWidth DRCs--> 427 <DRC type="ERROR" text="The RX and TX Data Width must be equal for the selected Sub Mode." paramId="TxDataWidth" condition="`${((SubModeUser ne CY_SCB_SPI_NATIONAL) && (RxDataWidth ne TxDataWidth)) ? true : false}`" /> 428 429 <!--EnableWakeup DRCs--> 430 <DRC type="ERROR" text="The API Mode must be High Level to support wakeup capability (the Cy_SCB_SPI_Interrupt function must be called in the interrupt handler hooked to NVIC)." paramId="ApiMode" condition="`${(DeepSleepCapable && EnableWakeup) ? ConfigIntr : false}`" /> 431 432 <!-- Check Master valid connections --> 433 <DRC type="ERROR" text="The SCLK and MOSI connections are not available for the selected device. The SPI Master can not operate on this SCB." paramId="ModeUser" condition="`${MasterMode && !hasConnectionSclk && !hasConnectionMosi}`" /> 434 435 <!-- Check data rate value --> 436 <DRC type="ERROR" text="Data rate upto 50000 kbps is allowed only if MISO is not used. Otherwise only upto 25000 kbps data rate is allowed." paramId="DataRate" condition="`${MasterMode ? ((!hasConnection("spi_miso", 0)) ? ((DataRate < 50001) ? false : true) : ((DataRate < 25001) ? false : true)) : false}`" /> 437 438 <!-- Check oversample value --> 439 <DRC type="ERROR" text="Oversample between 2-16 is allowed only if MISO is not used. Otherwise oversample only between 4-16 is allowed." paramId="OvsFactor" condition="`${MasterMode ? ((!hasConnection("spi_miso", 0)) ? ((OvsFactor < 2) ? true : false) : ((OvsFactor < 4) ? true : false)) : false}`" /> 440 441 </DRCs> 442 443 <ConfigFirmware> 444 <ConfigInclude value="cy_scb_spi.h" include="true" /> 445 <ConfigInclude value="cy_sysclk.h" include="`${pclkOk}`" /> 446 <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" /> 447 448 <ConfigDefine name="`${INST_NAME}`_HW" value="SCB`${InstNumber}`" public="true" include="true" /> 449 <ConfigDefine name="`${INST_NAME}`_IRQ" value="scb_`${InstNumber}`_interrupt_IRQn" public="true" include="true" /> 450 <ConfigStruct name="`${INST_NAME}`_config" type="cy_stc_scb_spi_config_t" const="`${inFlash}`" public="true" include="true" > 451 <Member name="spiMode" value="`${ModeUser}`" /> 452 <Member name="subMode" value="`${SubModeUser}`" /> 453 <Member name="sclkMode" value="`${SclkMode}`" /> 454 455 <Member name="parity" value="`${Parity}`" include="`${((version > 1) || (ipName eq "mxs22scb"))}`" /> 456 <Member name="dropOnParityError" value="`${DropOnParityError}`" include="`${((version > 1) || (ipName eq "mxs22scb"))}`" /> 457 458 <Member name="oversample" value="`${MasterMode ? OvsFactor : "0UL"}`" /> 459 460 <Member name="rxDataWidth" value="`${RxDataWidth}`UL" /> 461 <Member name="txDataWidth" value="`${TxDataWidth}`UL" /> 462 <Member name="enableMsbFirst" value="`${(BitsOrder eq MSB_FIRST) ? "true" : "false"}`" /> 463 <Member name="enableInputFilter" value="`${EnableInputFilter}`" /> 464 465 <Member name="enableFreeRunSclk" value="`${(MasterMode && EnableFreeRunSclk) ? "true" : "false"}`" /> 466 <Member name="enableMisoLateSample" value="`${(MasterMode && EnableLateMisoSample) ? "true" : "false"}`" /> 467 <Member name="enableTransferSeperation" value="`${(MasterMode && DeassertSelectLine) ? "true" : "false"}`" /> 468 469 <Member name="ssPolarity" value="(`${"(" . Ss0Polarity}` << CY_SCB_SPI_SLAVE_SELECT0) | \
 470 `${"(" . Ss1Polarity}` << CY_SCB_SPI_SLAVE_SELECT1) | \
 471 `${"(" . Ss2Polarity}` << CY_SCB_SPI_SLAVE_SELECT2) | \
 472 `${"(" . Ss3Polarity}` << CY_SCB_SPI_SLAVE_SELECT3))"/> 473 474 <Member name="ssSetupDelay" value="`${SetupDelay}`" include="`${((version > 1) || (ipName eq "mxs22scb"))}`" /> 475 <Member name="ssHoldDelay" value="`${HoldDelay}`" include="`${((version > 1) || (ipName eq "mxs22scb"))}`" /> 476 <Member name="ssInterFrameDelay" value="`${InterdataframeDelay}`" include="`${((version > 1) || (ipName eq "mxs22scb"))}`" /> 477 478 <Member name="enableWakeFromSleep" value="`${EnableWakeup}`" /> 479 480 <Member name="rxFifoTriggerLevel" value="`${RxTriggerLevel}`UL" /> 481 <Member name="rxFifoIntEnableMask" value="`${IntrRxMask}`UL" /> 482 483 <Member name="txFifoTriggerLevel" value="`${TxTriggerLevel}`UL" /> 484 <Member name="txFifoIntEnableMask" value="`${IntrTxMask}`UL" /> 485 486 <Member name="masterSlaveIntEnableMask" value="`${IntrMasterSlaveMask}`UL" /> 487 </ConfigStruct> 488 489 <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL)"> 490 <Member name="type" value="CYHAL_RSC_SCB" /> 491 <Member name="block_num" value="`${getInstNumber("scb")}`U" /> 492 <Member name="channel_num" value="0U" /> 493 </ConfigStruct> 494 495 <ConfigInstruction value="Cy_SysClk_PeriPclkAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${(((version > 1) || (ipName eq "mxs22scb")) && pclkOk)}`" /> 496 <ConfigInstruction value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${(((version eq 1) && (ipName ne "mxs22scb")) && pclkOk)}`" /> 497 498 <ConfigInstruction value="cyhal_hwmgr_reserve(&`${INST_NAME}`_obj);" include="true" guard="defined (CY_USING_HAL)" /> 499 </ConfigFirmware> 500</Personality> 501
