1 /***************************************************************************//** 2 * \file cyhal_pin_package.h 3 * 4 * Description: 5 * Provides definitions for the pinout for each supported device. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 /** 28 * \addtogroup group_hal_impl_pin_package Pins 29 * \ingroup group_hal_impl 30 * \{ 31 * Definitions for the pinout for each supported device 32 */ 33 34 #pragma once 35 36 #include "cy_gpio.h" 37 38 #if defined(__cplusplus) 39 extern "C" { 40 #endif /* __cplusplus */ 41 42 /** Port definitions that individual pins can belong to. */ 43 typedef enum { 44 CYHAL_PORT_0 = 0x00, 45 CYHAL_PORT_1 = 0x01, 46 CYHAL_PORT_2 = 0x02, 47 CYHAL_PORT_3 = 0x03, 48 CYHAL_PORT_4 = 0x04, 49 CYHAL_PORT_5 = 0x05, 50 CYHAL_PORT_6 = 0x06, 51 CYHAL_PORT_7 = 0x07, 52 CYHAL_PORT_8 = 0x08, 53 CYHAL_PORT_9 = 0x09, 54 CYHAL_PORT_10 = 0x0A, 55 CYHAL_PORT_11 = 0x0B, 56 CYHAL_PORT_12 = 0x0C, 57 CYHAL_PORT_13 = 0x0D, 58 CYHAL_PORT_14 = 0x0E, 59 CYHAL_PORT_15 = 0x0F, 60 CYHAL_PORT_16 = 0x10, 61 CYHAL_PORT_17 = 0x11, 62 CYHAL_PORT_18 = 0x12, 63 CYHAL_PORT_19 = 0x13, 64 CYHAL_PORT_20 = 0x14, 65 CYHAL_PORT_21 = 0x15, 66 CYHAL_PORT_22 = 0x16, 67 CYHAL_PORT_23 = 0x17, 68 CYHAL_PORT_24 = 0x18, 69 CYHAL_PORT_25 = 0x19, 70 CYHAL_PORT_26 = 0x1A, 71 CYHAL_PORT_27 = 0x1B, 72 CYHAL_PORT_28 = 0x1C, 73 CYHAL_PORT_29 = 0x1D, 74 CYHAL_PORT_30 = 0x1E, 75 CYHAL_PORT_31 = 0x1F, 76 CYHAL_PORT_32 = 0x20, 77 CYHAL_PORT_33 = 0x21, 78 CYHAL_PORT_34 = 0x22, 79 } cyhal_port_t; 80 81 /** \cond INTERNAL */ 82 /* The items in this cond block are DEPRECATED. They are only provided for mbed usage. */ 83 84 typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode 85 86 /** Extract the GPIO mode setting from a cyhal_gpio_mapping_cfg_t */ 87 #define CY_GPIO_CFG_GET_MODE(x) ((uint8_t)((x) & 0xFF)) 88 /** Extract the HSIOM selection from a cyhal_gpio_mapping_cfg_t */ 89 #define CY_GPIO_CFG_GET_HSIOM(x) ((en_hsiom_sel_t)(((x) >> 8) & 0xFF)) 90 91 #define CY_GPIO_CFG_CREATE(hsiom, mode) ((cyhal_gpio_mapping_cfg_t)(((hsiom) << 8) + (mode))) 92 93 #define CYHAL_PIN_OUT_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_STRONG_IN_OFF) 94 #define CYHAL_PIN_OUT_BUF_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_STRONG) 95 #define CYHAL_PIN_OD_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_OD_DRIVESLOW) 96 #define CYHAL_PIN_IN_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_HIGHZ) 97 #define CYHAL_PIN_PULLUP_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_PULLUP) 98 #define CYHAL_PIN_ANALOG_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(HSIOM_SEL_GPIO, CY_GPIO_DM_ANALOG) 99 #define CYHAL_PIN_AUX_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(HSIOM_SEL_GPIO, CY_GPIO_DM_ANALOG) 100 101 /** \endcond */ 102 103 #include "cy_device.h" 104 105 #if defined(_GPIO_PSOC6_01_104_M_CSP_BLE_H_) 106 #include "pin_packages/cyhal_psoc6_01_104_m_csp_ble.h" 107 #elif defined(_GPIO_PSOC6_01_104_M_CSP_BLE_USB_H_) 108 #include "pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h" 109 #elif defined(_GPIO_PSOC6_01_116_BGA_BLE_H_) 110 #include "pin_packages/cyhal_psoc6_01_116_bga_ble.h" 111 #elif defined(_GPIO_PSOC6_01_116_BGA_USB_H_) 112 #include "pin_packages/cyhal_psoc6_01_116_bga_usb.h" 113 #elif defined(_GPIO_PSOC6_01_124_BGA_H_) 114 #include "pin_packages/cyhal_psoc6_01_124_bga.h" 115 #elif defined(_GPIO_PSOC6_01_124_BGA_SIP_H_) 116 #include "pin_packages/cyhal_psoc6_01_124_bga_sip.h" 117 #elif defined(_GPIO_PSOC6_01_43_SMT_H_) 118 #include "pin_packages/cyhal_psoc6_01_43_smt.h" 119 #elif defined(_GPIO_PSOC6_01_68_QFN_BLE_H_) 120 #include "pin_packages/cyhal_psoc6_01_68_qfn_ble.h" 121 #elif defined(_GPIO_PSOC6_01_80_WLCSP_H_) 122 #include "pin_packages/cyhal_psoc6_01_80_wlcsp.h" 123 #elif defined(_GPIO_PSOC6_02_100_WLCSP_H_) 124 #include "pin_packages/cyhal_psoc6_02_100_wlcsp.h" 125 #elif defined(_GPIO_PSOC6_02_124_BGA_H_) 126 #include "pin_packages/cyhal_psoc6_02_124_bga.h" 127 #elif defined(_GPIO_PSOC6_02_128_TQFP_H_) 128 #include "pin_packages/cyhal_psoc6_02_128_tqfp.h" 129 #elif defined(_GPIO_PSOC6_02_68_QFN_H_) 130 #include "pin_packages/cyhal_psoc6_02_68_qfn.h" 131 #elif defined(_GPIO_PSOC6_03_100_TQFP_H_) 132 #include "pin_packages/cyhal_psoc6_03_100_tqfp.h" 133 #elif defined(_GPIO_PSOC6_03_49_WLCSP_H_) 134 #include "pin_packages/cyhal_psoc6_03_49_wlcsp.h" 135 #elif defined(_GPIO_PSOC6_03_68_QFN_H_) 136 #include "pin_packages/cyhal_psoc6_03_68_qfn.h" 137 #elif defined (_GPIO_PSOC6_04_64_TQFP_H_) 138 #include "pin_packages/cyhal_psoc6_04_64_tqfp.h" 139 #elif defined (_GPIO_PSOC6_04_68_QFN_H_) 140 #include "pin_packages/cyhal_psoc6_04_68_qfn.h" 141 #elif defined (_GPIO_PSOC6_04_80_M_CSP_H_) 142 #include "pin_packages/cyhal_psoc6_04_80_m_csp.h" 143 #elif defined (_GPIO_PSOC6_04_80_TQFP_H_) 144 #include "pin_packages/cyhal_psoc6_04_80_tqfp.h" 145 #elif defined(_GPIO_CYW20829A0_40_QFN_H_) 146 #include "pin_packages/cyhal_cyw20829a0_40_qfn.h" 147 #elif defined(_GPIO_CYW20829A0_56_QFN_H_) 148 #include "pin_packages/cyhal_cyw20829a0_56_qfn.h" 149 #elif defined(_GPIO_CYW20829B0_40_QFN_H_) 150 #include "pin_packages/cyhal_cyw20829_40_qfn.h" 151 #elif defined(_GPIO_CYW20829B0_56_QFN_H_) 152 #include "pin_packages/cyhal_cyw20829_56_qfn.h" 153 #elif defined(_GPIO_XMC7100_100_TEQFP_H_) 154 #include "pin_packages/cyhal_xmc7100_100_teqfp.h" 155 #elif defined(_GPIO_XMC7100_144_TEQFP_H_) 156 #include "pin_packages/cyhal_xmc7100_144_teqfp.h" 157 #elif defined(_GPIO_XMC7100_176_TEQFP_H_) 158 #include "pin_packages/cyhal_xmc7100_176_teqfp.h" 159 #elif defined(_GPIO_XMC7100_272_BGA_H_) 160 #include "pin_packages/cyhal_xmc7100_272_bga.h" 161 #elif defined(_GPIO_XMC7200_176_TEQFP_H_) 162 #include "pin_packages/cyhal_xmc7200_176_teqfp.h" 163 #elif defined(_GPIO_XMC7200_272_BGA_H_) 164 #include "pin_packages/cyhal_xmc7200_272_bga.h" 165 #else 166 #error "Unhandled Device/PinPackage combination" 167 #endif 168 169 #if defined(__cplusplus) 170 } 171 #endif /* __cplusplus */ 172 173 /** \} group_hal_impl */ 174
