1 /***************************************************************************//** 2 * \file cy_smif_memslot.h 3 * \version 2.20 4 * 5 * \brief 6 * This file provides the constants and parameter values for the memory-level 7 * APIs of the SMIF driver. 8 * 9 * Note: 10 * 11 ******************************************************************************** 12 * \copyright 13 * Copyright 2016-2021 Cypress Semiconductor Corporation 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the "License"); 17 * you may not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * http://www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an "AS IS" BASIS, 24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 *******************************************************************************/ 28 29 #if !defined (CY_SMIF_MEMORYSLOT_H) 30 #define CY_SMIF_MEMORYSLOT_H 31 32 #include "cy_device.h" 33 34 #if defined (CY_IP_MXSMIF) 35 36 #include <stdint.h> 37 #include <stdbool.h> 38 #include "cy_syslib.h" 39 #include "cy_smif.h" 40 41 #if defined(__cplusplus) 42 extern "C" { 43 #endif 44 45 46 /** 47 * \addtogroup group_smif_macros_status 48 * \{ 49 */ 50 51 /*************************************** 52 * Constants 53 ****************************************/ 54 #define CY_SMIF_DEVICE_BUSY (1U) /**< The external memory is busy */ 55 #define CY_SMIF_DEVICE_READY (0U) /**< The external memory is ready */ 56 57 /** \} group_smif_macros_status */ 58 59 /** 60 * \addtogroup group_smif_macros_cmd 61 * \{ 62 */ 63 #define CY_SMIF_CMD_WITHOUT_PARAM (0U) /**< No parameter */ 64 #define CY_SMIF_TX_LAST_BYTE (1U) /**< The last byte in the command transmission 65 * (SS is set high after the transmission) 66 */ 67 #define CY_SMIF_TX_NOT_LAST_BYTE (0U) /**< Not the last byte in the command transmission 68 * (SS remains low after the transmission) 69 */ 70 #define CY_SMIF_READ_ONE_BYTE (1U) /**< Read 1 byte */ 71 #define CY_SMIF_WRITE_ONE_BYTE (1U) /**< Write 1 byte */ 72 #define CY_SMIF_WRITE_TWO_BYTES (2U) /**< Write 2 bytes */ 73 #define CY_SMIF_ONE_WORD (4U) /**< 4 bytes */ 74 75 #define CY_SMIF_DUAL_QUAD_DISABLED (0U) /**< The dual quad transmission mode is disabled */ 76 #define CY_SMIF_DUAL_QUAD_ENABLED (1U) /**< The dual quad transmission mode is enabled */ 77 78 79 /** \} group_smif_macros_status */ 80 81 /** 82 * \addtogroup group_smif_macros_flags 83 * \{ 84 */ 85 86 #define CY_SMIF_FLAG_ALL_DISABLED (0U) /**< All memory configuration flags are disabled */ 87 /** Enables the write capability for the memory slave in the memory-mapped 88 * mode. Valid when the memory-mapped mode is enabled */ 89 #define CY_SMIF_FLAG_WRITE_ENABLE (SMIF_DEVICE_CTL_WR_EN_Msk) 90 /** Determines if the device is memory-mapped. If enabled, this memory slot will 91 * be initialized in System init */ 92 #define CY_SMIF_FLAG_MEMORY_MAPPED (2U) 93 #define CY_SMIF_FLAG_DETECT_SFDP (4U) /**< Enables the Autodetect using the SFDP */ 94 /** Enables the crypto support for this memory slave. All access to the 95 * memory device goes through the encryption/decryption 96 * Valid when the memory-mapped mode is enabled */ 97 #define CY_SMIF_FLAG_CRYPTO_ENABLE (SMIF_DEVICE_CTL_CRYPTO_EN_Msk) 98 99 #if (CY_IP_MXSMIF_VERSION>=3) || defined (CY_DOXYGEN) 100 /** 101 * \note 102 * This macro is available for CAT1B devices. 103 **/ 104 /** Enables IP version 3 features such as octal SPI/DDR mode/ 2 byte addressing 105 */ 106 #define CY_SMIF_FLAG_SMIF_REV_3 (8U) 107 #endif /* CY_IP_MXSMIF_VERSION */ 108 109 /** \} group_smif_macros_flags */ 110 111 /** 112 * \addtogroup group_smif_macros_sfdp 113 * \{ 114 */ 115 116 /*************************************** 117 * SFDP constants 118 ****************************************/ 119 #define CY_SMIF_SFDP_ADDRESS_LENGTH (0x03U) /**< The length of the SFDP address */ 120 #define CY_SMIF_SFDP_PARAM_HEADER_LENGTH (0x8U) /**< The length of the Parameter header */ 121 #define CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH (0x64U) /**< The length of the Parameter table */ 122 #define CY_SMIF_SFDP_LENGTH (CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH) /**< The length of the SFDP */ 123 #define CY_SMIF_SFDP_SIGNATURE_BYTE_00 (0x00U) /**< The SFDP Signature byte 0x00. Should be "S" */ 124 #define CY_SMIF_SFDP_SIGNATURE_BYTE_01 (0x01U) /**< The SFDP Signature byte 0x01. Should be "F" */ 125 #define CY_SMIF_SFDP_SIGNATURE_BYTE_02 (0x02U) /**< The SFDP Signature byte 0x02. Should be "D" */ 126 #define CY_SMIF_SFDP_SIGNATURE_BYTE_03 (0x03U) /**< The SFDP Signature byte 0x03. Should be "P" */ 127 #define CY_SMIF_SFDP_MINOR_REV (0x04U) /**< The SFDP Header byte 0x04. Defines the JEDEC JESD216 Revision */ 128 #define CY_SMIF_SFDP_MAJOR_REV (0x05U) /**< The SFDP Header byte 0x05. Defines the SFDP Major Revision */ 129 #define CY_SMIF_SFDP_MAJOR_REV_1 (0x01U) /**< The SFDP Major Revision is 1 */ 130 #define CY_SMIF_SFDP_JEDEC_REV_B (0x06U) /**< The JEDEC JESD216 Revision is B */ 131 #define CY_SMIF_SFDP_PARAM_TABLE_PTR (0x0CU) /**< Specifies the start of the JEDEC Basic Flash 132 * Parameter Table in the SFDP structure 133 */ 134 #define CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE (0x00U) /**< Code for the SFDP Address Bytes Number 3 */ 135 #define CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE (0x01U) /**< Code for the SFDP Address Bytes Number 3 or 4 */ 136 #define CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE (0x02U) /**< Code for the SFDP Address Bytes Number 4 */ 137 #define CY_SMIF_THREE_BYTES_ADDR (0x03U) /**< The address Bytes Number is 3 */ 138 #define CY_SMIF_FOUR_BYTES_ADDR (0x04U) /**< The address Bytes Number is 4 */ 139 #define CY_SMIF_READ_MODE_BYTE (0x5AU) /**< The mode byte for the SMIF read */ 140 #define CY_SMIF_WRITE_STATUS_REG1_CMD (0x01U) /**< The write status register 1 command */ 141 #define CY_SMIF_SINGLE_PROGRAM_CMD (0x02U) /**< The command for a single SMIF program */ 142 #define CY_SMIF_SINGLE_READ_CMD (0x03U) /**< The command for a single SMIF read */ 143 #define CY_SMIF_WRITE_DISABLE_CMD (0x04U) /**< The Write Disable command */ 144 #define CY_SMIF_READ_STATUS_REG1_CMD (0x05U) /**< The read status register 1 command */ 145 #define CY_SMIF_WRITE_ENABLE_CMD (0x06U) /**< The Write Enable command */ 146 #define CY_SMIF_READ_STATUS_REG2_T1_CMD (0x35U) /**< The read status register 2 type 1 command */ 147 #define CY_SMIF_WRITE_STATUS_REG2_CMD (0x3EU) /**< The write status register 2 command */ 148 #define CY_SMIF_READ_STATUS_REG2_T2_CMD (0x3FU) /**< The read status register 2 type 2 command */ 149 #define CY_SMIF_CHIP_ERASE_CMD (0x60U) /**< The Chip Erase command */ 150 #define CY_SMIF_QE_BIT_STATUS_REG2_T1 (0x02U) /**< The QE bit is in status register 2 type 1. 151 * It should be written as the second byte. 152 */ 153 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_1S (0x0CU) /**< The command for a 1S-1S-1S SMIF fast read with 4-byte addressing */ 154 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_2S (0x3CU) /**< The command for a 1S-1S-2S SMIF fast read with 4-byte addressing */ 155 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_2S_2S (0xBCU) /**< The command for a 1S-2S-2S SMIF fast read with 4-byte addressing */ 156 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_4S (0x6CU) /**< The command for a 1S-1S-4S SMIF fast read with 4-byte addressing */ 157 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_4S_4S (0xECU) /**< The command for a 1S-4S-4S SMIF fast read with 4-byte addressing */ 158 159 #if (CY_IP_MXSMIF_VERSION>=3) || defined (CY_DOXYGEN) 160 /** 161 * \note 162 * This macro is available for CAT1B devices. 163 **/ 164 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_4D_4D (0xEEU) /**< The command for a 1S-4D-4D SMIF fast read with 4-byte addressing */ 165 #endif /* CY_IP_MXSMIF_VERSION */ 166 167 #define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_1S (0x12U) /**< The command for a 1S-1S-1S SMIF page program with 4-byte addressing */ 168 #define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_4S (0x34U) /**< The command for a 1S-1S-4S SMIF page program with 4-byte addressing */ 169 #define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_4S_4S (0x3EU) /**< The command for a 1S-4S-4S SMIF page program with 4-byte addressing */ 170 171 172 #define CY_SMIF_BRWR_EXTADD_MASK (0x80U) /**< The Extended Address Enable (EXTADD) mask */ 173 174 #define CY_SMIF_SFDP_ERASE_TIME_1MS (1U) /**< Units of Erase Typical Time in ms */ 175 #define CY_SMIF_SFDP_ERASE_TIME_16MS (16U) /**< Units of Erase Typical Time in ms */ 176 #define CY_SMIF_SFDP_ERASE_TIME_128MS (128U) /**< Units of Erase Typical Time in ms */ 177 #define CY_SMIF_SFDP_ERASE_TIME_1S (1000U) /**< Units of Erase Typical Time in ms */ 178 179 #define CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS (16U) /**< Units of Chip Erase Typical Time in ms */ 180 #define CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS (256U) /**< Units of Chip Erase Typical Time in ms */ 181 #define CY_SMIF_SFDP_CHIP_ERASE_TIME_4S (4000U) /**< Units of Chip Erase Typical Time in ms */ 182 #define CY_SMIF_SFDP_CHIP_ERASE_TIME_64S (64000U) /**< Units of Chip Erase Typical Time in ms */ 183 184 #define CY_SMIF_SFDP_PROG_TIME_8US (8U) /**< Units of Page Program Typical Time in us */ 185 #define CY_SMIF_SFDP_PROG_TIME_64US (64U) /**< Units of Page Program Typical Time in us */ 186 187 #define CY_SMIF_SFDP_UNIT_0 (0U) /**< Units of Basic Flash Parameter Table Time Parameters */ 188 #define CY_SMIF_SFDP_UNIT_1 (1U) /**< Units of Basic Flash Parameter Table Time Parameters */ 189 #define CY_SMIF_SFDP_UNIT_2 (2U) /**< Units of Basic Flash Parameter Table Time Parameters */ 190 #define CY_SMIF_SFDP_UNIT_3 (3U) /**< Units of Basic Flash Parameter Table Time Parameters */ 191 192 193 #define CY_SMIF_STATUS_REG_BUSY_MASK (0x01U) /**< The busy mask for the status registers */ 194 #define CY_SMIF_NO_COMMAND_OR_MODE (0xFFFFFFFFUL) /**< No command or mode present */ 195 #define CY_SMIF_SFDP_QER_0 (0x00UL) /**< The quad Enable Requirements case 0 */ 196 #define CY_SMIF_SFDP_QER_1 (0x01UL) /**< The quad Enable Requirements case 1 */ 197 #define CY_SMIF_SFDP_QER_2 (0x02UL) /**< The quad Enable Requirements case 2 */ 198 #define CY_SMIF_SFDP_QER_3 (0x03UL) /**< The quad Enable Requirements case 3 */ 199 #define CY_SMIF_SFDP_QER_4 (0x04UL) /**< The quad Enable Requirements case 4 */ 200 #define CY_SMIF_SFDP_QER_5 (0x05UL) /**< The quad Enable Requirements case 5 */ 201 #define CY_SMIF_SFDP_QE_BIT_1_OF_SR_2 (0x02UL) /**< The QE is bit 1 of the status register 2 */ 202 #define CY_SMIF_SFDP_QE_BIT_6_OF_SR_1 (0x40UL) /**< The QE is bit 6 of the status register 1 */ 203 #define CY_SMIF_SFDP_QE_BIT_7_OF_SR_2 (0x80UL) /**< The QE is bit 7 of the status register 2 */ 204 #define CY_SMIF_SFDP_BFPT_BYTE_02 (0x02U) /**< The byte 0x02 of the JEDEC Basic Flash Parameter Table */ 205 #define CY_SMIF_SFDP_BFPT_BYTE_04 (0x04U) /**< The byte 0x04 of the JEDEC Basic Flash Parameter Table */ 206 #define CY_SMIF_SFDP_BFPT_BYTE_05 (0x05U) /**< The byte 0x05 of the JEDEC Basic Flash Parameter Table */ 207 #define CY_SMIF_SFDP_BFPT_BYTE_06 (0x06U) /**< The byte 0x06 of the JEDEC Basic Flash Parameter Table: 208 * number of Parameter Headers (zero based, 05h = 6 parameters) 209 */ 210 #define CY_SMIF_SFDP_BFPT_BYTE_08 (0x08U) /**< The byte 0x08 of the JEDEC Basic Flash Parameter Table */ 211 #define CY_SMIF_SFDP_BFPT_BYTE_09 (0x09U) /**< The byte 0x09 of the JEDEC Basic Flash Parameter Table */ 212 #define CY_SMIF_SFDP_BFPT_BYTE_0A (0x0AU) /**< The byte 0x0A of the JEDEC Basic Flash Parameter Table */ 213 #define CY_SMIF_SFDP_BFPT_BYTE_0B (0x0BU) /**< The byte 0x0B of the JEDEC Basic Flash Parameter Table */ 214 #define CY_SMIF_SFDP_BFPT_BYTE_0C (0x0CU) /**< The byte 0x0C of the JEDEC Basic Flash Parameter Table */ 215 #define CY_SMIF_SFDP_BFPT_BYTE_0D (0x0DU) /**< The byte 0x0D of the JEDEC Basic Flash Parameter Table */ 216 #define CY_SMIF_SFDP_BFPT_BYTE_0E (0x0EU) /**< The byte 0x0E of the JEDEC Basic Flash Parameter Table */ 217 #define CY_SMIF_SFDP_BFPT_BYTE_0F (0x0FU) /**< The byte 0x0F of the JEDEC Basic Flash Parameter Table */ 218 #define CY_SMIF_SFDP_BFPT_BYTE_1C (0x1CU) /**< The byte 0x1C of the JEDEC Basic Flash Parameter Table */ 219 #define CY_SMIF_SFDP_BFPT_BYTE_1D (0x1DU) /**< The byte 0x1D of the JEDEC Basic Flash Parameter Table */ 220 #define CY_SMIF_SFDP_BFPT_BYTE_23 (0x23U) /**< The byte 0x23 of the JEDEC Basic Flash Parameter Table */ 221 #define CY_SMIF_SFDP_BFPT_BYTE_28 (0x28U) /**< The byte 0x28 of the JEDEC Basic Flash Parameter Table */ 222 #define CY_SMIF_SFDP_BFPT_BYTE_3A (0x3AU) /**< The byte 0x3A of the JEDEC Basic Flash Parameter Table */ 223 #define CY_SMIF_SFDP_BFPT_BYTE_3C (0x3CU) /**< The byte 0x3C of the JEDEC Basic Flash Parameter Table */ 224 #define CY_SMIF_SFDP_BFPT_ERASE_BYTE (36U) /**< The byte 36 of the JEDEC Basic Flash Parameter Table */ 225 226 #define CY_SMIF_JEDEC_BFPT_10TH_DWORD (9U) /**< Offset to JEDEC Basic Flash Parameter Table: 10th DWORD */ 227 #define CY_SMIF_JEDEC_BFPT_11TH_DWORD (10U) /**< Offset to JEDEC Basic Flash Parameter Table: 11th DWORD */ 228 229 230 #define CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET (1UL) /**< The offset for the detection command instruction in the Sector Map command descriptor */ 231 #define CY_SMIF_SFDP_SECTOR_MAP_ADDR_CODE_OFFSET (2UL) /**< The offset for the detection command address length in the Sector Map command descriptor */ 232 #define CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET (3UL) /**< The offset for the read data mask in the Sector Map command descriptor */ 233 #define CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET (4UL) /**< The offset for the detection command address in the Sector Map command descriptor */ 234 #define CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET (2UL) /**< The offset for the regions count in the Sector Map descriptor */ 235 #define CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET (2UL) /**< The offset for the configuration ID in the Sector Map descriptor */ 236 #define CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK (0xFU) /**< The mask for the supported erase type code in the Sector Map descriptor */ 237 #define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Msk (0xC0UL) /**< The mask for the configuration detection command address bytes in the Sector Map descriptor */ 238 #define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Pos (6UL) /**< The position of the configuration detection command address bytes in the Sector Map descriptor */ 239 240 241 /* ---------------------------- 1st DWORD ---------------------------- */ 242 #define CY_SMIF_SFDP_FAST_READ_1_1_4_Pos (6UL) /**< The SFDP 1-1-4 fast read support (Bit 6) */ 243 #define CY_SMIF_SFDP_FAST_READ_1_1_4_Msk (0x40UL) /**< The SFDP 1-1-4 fast read support (Bitfield-Mask: 0x01) */ 244 #define CY_SMIF_SFDP_FAST_READ_1_4_4_Pos (5UL) /**< The SFDP 1-4-4 fast read support (Bit 5) */ 245 #define CY_SMIF_SFDP_FAST_READ_1_4_4_Msk (0x20UL) /**< The SFDP 1-4-4 fast read support (Bitfield-Mask: 0x01) */ 246 #define CY_SMIF_SFDP_FAST_READ_1_2_2_Pos (4UL) /**< The SFDP 1-2-2 fast read support (Bit 4) */ 247 #define CY_SMIF_SFDP_FAST_READ_1_2_2_Msk (0x10UL) /**< The SFDP 1-2-2 fast read support (Bitfield-Mask: 0x01) */ 248 249 #if (CY_IP_MXSMIF_VERSION>=3) || defined (CY_DOXYGEN) 250 /** 251 * \note 252 * This macro is available for CAT1B devices. 253 **/ 254 #define CY_SMIF_SFDP_DTR_SUPPORT_Pos (3UL) /**< The SFDP DTR support (Bit 3) */ 255 /** 256 * \note 257 * This macro is available for CAT1B devices. 258 **/ 259 #define CY_SMIF_SFDP_DTR_SUPPORT_Msk (0x08UL) /**< The SFDP DTR support (Bitfield-Mask: 0x08) */ 260 #endif /* CY_IP_MXSMIF_VERSION */ 261 262 #define CY_SMIF_SFDP_ADDRESS_BYTES_Pos (1UL) /**< The SFDP number of address bytes (Bit 1) */ 263 #define CY_SMIF_SFDP_ADDRESS_BYTES_Msk (0x06UL) /**< The SFDP number of address bytes (Bitfield-Mask: 0x03) */ 264 #define CY_SMIF_SFDP_FAST_READ_1_1_2_Pos (0UL) /**< The SFDP 1-1-2 fast read support (Bit 0) */ 265 #define CY_SMIF_SFDP_FAST_READ_1_1_2_Msk (0x01UL) /**< The SFDP 1-1-2 fast read support (Bitfield-Mask: 0x01) */ 266 267 /* ---------------------------- 2nd DWORD ---------------------------- */ 268 #define CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk (0x80000000UL) /**< Flash memory density bit define if it >= 4 Gbit or <= 2Gbit */ 269 270 /* ---------------------------- 3rd DWORD ---------------------------- */ 271 #define CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1-4-4 fast read dummy cycles (Bit 0) */ 272 #define CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1-4-4 fast read dummy cycles (Bitfield-Mask: 0x1F) */ 273 #define CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1-4-4 fast read mode cycles (Bit 5) */ 274 #define CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1-4-4 fast read mode cycles (Bitfield-Mask: 0x07) */ 275 #define CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1-1-4 fast read dummy cycles (Bit 0) */ 276 #define CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1-1-4 fast read dummy cycles (Bitfield-Mask: 0x1F) */ 277 #define CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1-1-4 fast read mode cycles (Bit 5) */ 278 #define CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1-1-4 fast read mode cycles (Bitfield-Mask: 0x07) */ 279 280 /* ---------------------------- 4th DWORD ---------------------------- */ 281 #define CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1_1_2 fast read dummy cycles (Bit 0) */ 282 #define CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1_1_2 fast read dummy cycles (Bitfield-Mask: 0x1F) */ 283 #define CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1_1_2 fast read mode cycles (Bit 5) */ 284 #define CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1_1_2 fast read mode cycles (Bitfield-Mask: 0x07) */ 285 #define CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1_2_2 fast read dummy cycles (Bit 0) */ 286 #define CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1_2_2 fast read dummy cycles (Bitfield-Mask: 0x1F) */ 287 #define CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1_2_2 fast read mode cycles (Bit 5) */ 288 #define CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1_2_2 fast read mode cycles (Bitfield-Mask: 0x07) */ 289 290 /* ---------------------------- 10th DWORD --------------------------- */ 291 #define CY_SMIF_SFDP_ERASE_T1_COUNT_Pos (4UL) /**< Erase Type 1 Erase, Typical time: count (Bits 8:4) */ 292 #define CY_SMIF_SFDP_ERASE_T1_COUNT_Msk (0x1F0UL) /**< Erase Type 1 Erase, Typical time: count (Bitfield-Mask ) */ 293 #define CY_SMIF_SFDP_ERASE_T1_UNITS_Pos (9UL) /**< Erase Type 1 Erase, Typical time: units (Bits 10:9) */ 294 #define CY_SMIF_SFDP_ERASE_T1_UNITS_Msk (0x600UL) /**< Erase Type 1 Erase, Typical time: units (Bitfield-Mask ) */ 295 #define CY_SMIF_SFDP_ERASE_MUL_COUNT_Pos (0UL) /**< Multiplier from typical erase time to maximum erase time (Bits 3:0) */ 296 #define CY_SMIF_SFDP_ERASE_MUL_COUNT_Msk (0x0FUL) /**< Multiplier from typical erase time to maximum erase time (Bitfield-Mask ) */ 297 298 299 /* ---------------------------- 11th DWORD --------------------------- */ 300 #define CY_SMIF_SFDP_PAGE_SIZE_Pos (4UL) /**< The SFDP page size (Bit 4) */ 301 #define CY_SMIF_SFDP_PAGE_SIZE_Msk (0xF0UL) /**< The SFDP page size (Bitfield-Mask: 0x0F) */ 302 #define CY_SMIF_SFDP_PAGE_PROG_COUNT_Pos (8UL) /**< The SFDP Chip Page Program Typical time: count (Bits 12:8) */ 303 #define CY_SMIF_SFDP_PAGE_PROG_COUNT_Msk (0x1F00UL) /**< The SFDP Chip Page Program Typical time: count (Bitfield-Mask)*/ 304 #define CY_SMIF_SFDP_PAGE_PROG_UNITS_Pos (13UL) /**< The SFDP Chip Page Program Typical time: units (Bit 13) */ 305 #define CY_SMIF_SFDP_PAGE_PROG_UNITS_Msk (0x2000UL) /**< The SFDP Chip Page Program Typical time: units (Bitfield-Mask)*/ 306 #define CY_SMIF_SFDP_CHIP_ERASE_COUNT_Pos (24UL) /**< The SFDP Chip Erase Typical time: count (Bits 28:24) */ 307 #define CY_SMIF_SFDP_CHIP_ERASE_COUNT_Msk (0x1F000000UL) /**< The SFDP Chip Erase Typical time: count (Bitfield-Mask) */ 308 #define CY_SMIF_SFDP_CHIP_ERASE_UNITS_Pos (29UL) /**< The SFDP Chip Erase Typical time: units (Bits 29:30) */ 309 #define CY_SMIF_SFDP_CHIP_ERASE_UNITS_Msk (0x60000000UL) /**< The SFDP Chip Erase Typical time: units (Bitfield-Mask) */ 310 #define CY_SMIF_SFDP_PROG_MUL_COUNT_Pos (0UL) /**< Multiplier from typical time to max time for Page or byte program (Bits 3:0) */ 311 #define CY_SMIF_SFDP_PROG_MUL_COUNT_Msk (0x0FUL) /**< Multiplier from typical time to max time for Page or byte program (Bitfield-Mask) */ 312 313 /* ---------------------------- 15th DWORD --------------------------- */ 314 #define CY_SMIF_SFDP_QE_REQUIREMENTS_Pos (4UL) /**< The SFDP quad enable requirements field (Bit 4) */ 315 #define CY_SMIF_SFDP_QE_REQUIREMENTS_Msk (0x70UL) /**< The SFDP quad enable requirements field (Bitfield-Mask: 0x07) */ 316 317 318 /* ---------------------------- 16th DWORD --------------------------- */ 319 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7 (1U) /**< Issue 0xB7 instruction */ 320 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7 (2U) /**< Issue write enable instruction followed with 0xB7 */ 321 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE (0x40U) /**< Memory always operates in 4-byte mode */ 322 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD (0xB7U) /**< The instruction required to enter 4-byte addressing mode */ 323 324 325 /** \cond INTERNAL */ 326 /******************************************************************************* 327 * These are legacy constants and API. They are left here just 328 * for backward compatibility. 329 * Do not use them in new designs. 330 *******************************************************************************/ 331 332 #define CY_SMIF_FLAG_WR_EN CY_SMIF_FLAG_WRITE_ENABLE 333 #define CY_SMIF_FLAG_CRYPTO_EN CY_SMIF_FLAG_CRYPTO_ENABLE 334 #define CY_SMIF_SFDP_SING_BYTE_00 CY_SMIF_SFDP_SIGNATURE_BYTE_00 335 #define CY_SMIF_SFDP_SING_BYTE_01 CY_SMIF_SFDP_SIGNATURE_BYTE_01 336 #define CY_SMIF_SFDP_SING_BYTE_02 CY_SMIF_SFDP_SIGNATURE_BYTE_02 337 #define CY_SMIF_SFDP_SING_BYTE_03 CY_SMIF_SFDP_SIGNATURE_BYTE_03 338 #define CY_SMIF_WR_STS_REG1_CMD CY_SMIF_WRITE_STATUS_REG1_CMD 339 #define CY_SMIF_WR_DISABLE_CMD CY_SMIF_WRITE_DISABLE_CMD 340 #define CY_SMIF_RD_STS_REG1_CMD CY_SMIF_READ_STATUS_REG1_CMD 341 #define CY_SMIF_WR_ENABLE_CMD CY_SMIF_WRITE_ENABLE_CMD 342 #define CY_SMIF_RD_STS_REG2_T1_CMD CY_SMIF_READ_STATUS_REG2_T1_CMD 343 #define CY_SMIF_WR_STS_REG2_CMD CY_SMIF_WRITE_STATUS_REG2_CMD 344 #define CY_SMIF_RD_STS_REG2_T2_CMD CY_SMIF_READ_STATUS_REG2_T2_CMD 345 #define CY_SMIF_QE_BIT_STS_REG2_T1 CY_SMIF_QE_BIT_STATUS_REG2_T1 346 #define CY_SMIF_STS_REG_BUSY_MASK CY_SMIF_STATUS_REG_BUSY_MASK 347 348 #define Cy_SMIF_Memslot_Init Cy_SMIF_MemInit 349 #define Cy_SMIF_Memslot_DeInit Cy_SMIF_MemDeInit 350 #define Cy_SMIF_Memslot_CmdWriteEnable Cy_SMIF_MemCmdWriteEnable 351 #define Cy_SMIF_Memslot_CmdWriteDisable Cy_SMIF_MemCmdWriteDisable 352 #define Cy_SMIF_Memslot_IsBusy Cy_SMIF_MemIsBusy 353 #define Cy_SMIF_Memslot_QuadEnable Cy_SMIF_MemQuadEnable 354 #define Cy_SMIF_Memslot_CmdReadSts Cy_SMIF_MemCmdReadStatus 355 #define Cy_SMIF_Memslot_CmdWriteSts Cy_SMIF_MemCmdWriteStatus 356 #define Cy_SMIF_Memslot_CmdChipErase Cy_SMIF_MemCmdChipErase 357 #define Cy_SMIF_Memslot_CmdSectorErase Cy_SMIF_MemCmdSectorErase 358 #define Cy_SMIF_Memslot_SfdpDetect Cy_SMIF_MemSfdpDetect 359 #define Cy_SMIF_Memslot_CmdProgram Cy_SMIF_MemCmdProgram 360 #define Cy_SMIF_Memslot_CmdRead Cy_SMIF_MemCmdRead 361 362 /** \endcond */ 363 /** \} group_smif_macros_sfdp */ 364 365 366 /** 367 * \addtogroup group_smif_data_structures_memslot 368 * \{ 369 */ 370 371 /** This command structure is used to store the Read/Write command 372 * configuration. */ 373 typedef struct 374 { 375 uint32_t command; /**< The 8-bit command. This value is 0xFFFFFFFF when there is no command present */ 376 cy_en_smif_txfr_width_t cmdWidth; /**< The width of the command transfer */ 377 cy_en_smif_txfr_width_t addrWidth; /**< The width of the address transfer */ 378 uint32_t mode; /**< The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ 379 cy_en_smif_txfr_width_t modeWidth; /**< The width of the mode transfer */ 380 uint32_t dummyCycles; /**< The number of the dummy cycles. A zero value suggests no dummy cycles */ 381 cy_en_smif_txfr_width_t dataWidth; /**< The width of the data transfer */ 382 #if (CY_IP_MXSMIF_VERSION>=3) || defined (CY_DOXYGEN) 383 /** 384 * \note 385 * This parameter is available for CAT1B devices. 386 **/ 387 cy_en_smif_data_rate_t dataRate; /**< The Data rate of data */ 388 /** 389 * \note 390 * This parameter is available for CAT1B devices. 391 **/ 392 cy_en_smif_field_presence_t dummyCyclesPresence; /**< This specifies the presence of the dummy field */ 393 /** 394 * \note 395 * This parameter is available for CAT1B devices. 396 **/ 397 cy_en_smif_field_presence_t modePresence; /**< This specifies the presence of the mode field */ 398 /** 399 * \note 400 * This parameter is available for CAT1B devices. 401 **/ 402 uint32_t modeH; /**< The 8-bit command. This value is 0x0 when there is no higher byte mode present */ 403 /** 404 * \note 405 * This parameter is available for CAT1B devices. 406 **/ 407 cy_en_smif_data_rate_t modeRate; /**< The Data rate of mode */ 408 /** 409 * \note 410 * This parameter is available for CAT1B devices. 411 **/ 412 cy_en_smif_data_rate_t addrRate; /**< The Data rate of address */ 413 /** 414 * \note 415 * This parameter is available for CAT1B devices. 416 **/ 417 cy_en_smif_field_presence_t cmdPresence; /**< This specifies the presence of the command field */ 418 /** 419 * \note 420 * This parameter is available for CAT1B devices. 421 **/ 422 uint32_t commandH; /**< The 8-bit command. This value is 0x0 when there is no higher byte command present */ 423 /** 424 * \note 425 * This parameter is available for CAT1B devices. 426 **/ 427 cy_en_smif_data_rate_t cmdRate; /**< The Data rate of command */ 428 #endif /* CY_IP_MXSMIF_VERSION */ 429 } cy_stc_smif_mem_cmd_t; 430 431 /** This structure specifies data used for memory with hybrid sectors */ 432 typedef struct 433 { 434 uint32_t regionAddress; /**< This specifies the address where a region starts */ 435 uint32_t sectorsCount; /**< This specifies the number of sectors in the region */ 436 uint32_t eraseCmd; /**< This specifies the region specific erase instruction */ 437 uint32_t eraseSize; /**< This specifies the size of one sector */ 438 uint32_t eraseTime; /**< Max time for sector erase type 1 cycle time in ms */ 439 } cy_stc_smif_hybrid_region_info_t; 440 441 442 /** 443 * 444 * This configuration structure of the SMIF memory device is used to store 445 * device-specific parameters. 446 * These parameters are used to set up the memory mode initialization and the 447 * memory API. 448 */ 449 typedef struct 450 { 451 uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the 452 * memory slave device, valid values 1-4 */ 453 uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes; 454 * For densities 4 gigabits and above - bit-31 is set to 1b to define that 455 * this memory is 4 gigabits and above; and other 30:0 bits define N where 456 * the density is computed as 2^N bytes. 457 * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. 458 */ 459 cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */ 460 cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */ 461 cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */ 462 cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */ 463 uint32_t eraseSize; /**< This specifies the sector size of each Erase */ 464 cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */ 465 cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */ 466 uint32_t programSize; /**< This specifies the page size for programming */ 467 cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */ 468 cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */ 469 cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */ 470 cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */ 471 uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */ 472 uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */ 473 uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */ 474 uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */ 475 uint32_t programTime; /**< Max time for page program cycle time in us */ 476 uint32_t hybridRegionCount; /**< This specifies the number of regions for memory with hybrid sectors */ 477 cy_stc_smif_hybrid_region_info_t** hybridRegionInfo; /**< This specifies data for memory with hybrid sectors */ 478 } cy_stc_smif_mem_device_cfg_t; 479 480 481 /** 482 * 483 * This SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation. 484 * This data structure is stored in a fixed location in the flash. The data structure is required 485 * for the initialization of the SMIF in the SystemInit. 486 */ 487 typedef struct 488 { 489 /** Determines the slave select where the memory device is placed */ 490 cy_en_smif_slave_select_t slaveSelect; 491 /** Determines if the device is memory-mapped, enables the Autodetect 492 * using the SFDP, enables the write capability, or enables the crypto 493 * support for this memory slave */ 494 uint32_t flags; 495 /** The data-line selection options for a slave device */ 496 cy_en_smif_data_select_t dataSelect; 497 /** The base address the memory slave is mapped to in the PSoC memory map. 498 * This address must be a multiple of the SMIF XIP memory size/capacity. The 499 * SMIF XIP memory region should NOT overlap with other memory regions 500 * (with exception to dual quad mode). Valid when the memory-mapped mode is 501 * enabled. 502 */ 503 uint32_t baseAddress; 504 /** The size/capacity allocated in the PSoC memory map for the memory slave 505 * device. The capacity is allocated from the base address. The capacity 506 * must be a power of 2 and greater or equal than 64 KB. Valid when 507 * memory-mapped mode is enabled 508 */ 509 uint32_t memMappedSize; 510 /** Defines if this memory device is one of the devices in the dual quad SPI 511 * configuration. Equals the sum of the slave-slot numbers. */ 512 uint32_t dualQuadSlots; 513 cy_stc_smif_mem_device_cfg_t* deviceCfg; /**< The configuration of the device */ 514 } cy_stc_smif_mem_config_t; 515 516 517 /** 518 * 519 * This SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation. 520 * This data structure is stored in a fixed location in the flash. The data structure is required 521 * for the initialization of the SMIF in the SystemInit. 522 */ 523 typedef struct 524 { 525 uint32_t memCount; /**< The number of SMIF memory defined */ 526 cy_stc_smif_mem_config_t** memConfig; /**< The pointer to the array of the memory configuration structures of size Memory_count */ 527 uint32_t majorVersion; /**< The version of the SMIF driver */ 528 uint32_t minorVersion; /**< The version of the SMIF Driver */ 529 } cy_stc_smif_block_config_t; 530 531 532 /** \} group_smif_data_structures_memslot */ 533 534 535 /** 536 * \addtogroup group_smif_mem_slot_functions 537 * \{ 538 */ 539 cy_en_smif_status_t Cy_SMIF_MemInit(SMIF_Type *base, 540 cy_stc_smif_block_config_t const * blockConfig, 541 cy_stc_smif_context_t *context); 542 void Cy_SMIF_MemDeInit(SMIF_Type *base); 543 cy_en_smif_status_t Cy_SMIF_MemCmdWriteEnable( SMIF_Type *base, 544 cy_stc_smif_mem_config_t const *memDevice, 545 cy_stc_smif_context_t const *context); 546 cy_en_smif_status_t Cy_SMIF_MemCmdWriteDisable(SMIF_Type *base, 547 cy_stc_smif_mem_config_t const *memDevice, 548 cy_stc_smif_context_t const *context); 549 bool Cy_SMIF_MemIsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t const *memDevice, 550 cy_stc_smif_context_t const *context); 551 cy_en_smif_status_t Cy_SMIF_MemQuadEnable(SMIF_Type *base, 552 cy_stc_smif_mem_config_t const *memDevice, 553 cy_stc_smif_context_t const *context); 554 cy_en_smif_status_t Cy_SMIF_MemCmdReadStatus(SMIF_Type *base, 555 cy_stc_smif_mem_config_t const *memDevice, 556 uint8_t *status, uint8_t command, 557 cy_stc_smif_context_t const *context); 558 cy_en_smif_status_t Cy_SMIF_MemCmdWriteStatus(SMIF_Type *base, 559 cy_stc_smif_mem_config_t const *memDevice, 560 void const *status, uint8_t command, 561 cy_stc_smif_context_t const *context); 562 cy_en_smif_status_t Cy_SMIF_MemCmdChipErase(SMIF_Type *base, 563 cy_stc_smif_mem_config_t const *memDevice, 564 cy_stc_smif_context_t const *context); 565 cy_en_smif_status_t Cy_SMIF_MemCmdSectorErase(SMIF_Type *base, 566 cy_stc_smif_mem_config_t const *memDevice, 567 uint8_t const *sectorAddr, 568 cy_stc_smif_context_t const *context); 569 cy_en_smif_status_t Cy_SMIF_MemCmdProgram(SMIF_Type *base, 570 cy_stc_smif_mem_config_t const *memDevice, 571 uint8_t const *addr, 572 uint8_t const *writeBuff, 573 uint32_t size, 574 cy_smif_event_cb_t cmdCompleteCb, 575 cy_stc_smif_context_t *context); 576 cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base, 577 cy_stc_smif_mem_config_t const *memDevice, 578 uint8_t const *addr, 579 uint8_t *readBuff, 580 uint32_t size, 581 cy_smif_event_cb_t cmdCompleteCb, 582 cy_stc_smif_context_t *context); 583 cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, 584 cy_stc_smif_mem_device_cfg_t *device, 585 cy_en_smif_slave_select_t slaveSelect, 586 cy_en_smif_data_select_t dataSelect, 587 cy_stc_smif_context_t *context); 588 589 cy_en_smif_status_t Cy_SMIF_MemIsReady(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, 590 uint32_t timeoutUs, cy_stc_smif_context_t const *context); 591 cy_en_smif_status_t Cy_SMIF_MemIsQuadEnabled(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, 592 bool *isQuadEnabled, cy_stc_smif_context_t const *context); 593 cy_en_smif_status_t Cy_SMIF_MemEnableQuadMode(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, 594 uint32_t timeoutUs, cy_stc_smif_context_t const *context); 595 cy_en_smif_status_t Cy_SMIF_MemRead(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, 596 uint32_t address, uint8_t rxBuffer[], 597 uint32_t length, cy_stc_smif_context_t const *context); 598 cy_en_smif_status_t Cy_SMIF_MemWrite(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, 599 uint32_t address, uint8_t const txBuffer[], 600 uint32_t length, cy_stc_smif_context_t const *context); 601 cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, 602 uint32_t address, uint32_t length, 603 cy_stc_smif_context_t const *context); 604 cy_en_smif_status_t Cy_SMIF_MemEraseChip(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, 605 cy_stc_smif_context_t const *context); 606 cy_en_smif_status_t Cy_SMIF_MemLocateHybridRegion(cy_stc_smif_mem_config_t const *memDevice, 607 cy_stc_smif_hybrid_region_info_t** regionInfo, uint32_t address); 608 /** \} group_smif_mem_slot_functions */ 609 610 611 #if defined(__cplusplus) 612 } 613 #endif 614 615 #endif /* CY_IP_MXSMIF */ 616 617 #endif /* (CY_SMIF_MEMORYSLOT_H) */ 618 619 620 /* [] END OF FILE */ 621
