1 /***************************************************************************//**
2 * \file cy_mcwdt.h
3 * \version 1.50.1
4 *
5 * Provides an API declaration of the Cypress PDL 3.0 MCWDT driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_mcwdt
27 * \{
28 * A MCWDT has two 16-bit counters and one 32-bit counter.
29 *
30 * The functions and other declarations used in this driver are in cy_mcwdt.h.
31 * You can include cy_pdl.h to get access to all functions
32 * and declarations in the PDL.
33 *
34 * You can use this driver to create a free-running
35 * timer or generate periodic interrupts. The driver also
36 * includes support for the watchdog function to recover from CPU or
37 * firmware failures.
38 *
39 * There are two primary use cases for MCWDT: generating periodic CPU interrupts;
40 * and implementing a free-running timer. Both have many applications in
41 * embedded systems:
42 * * Measuring time between events
43 * * Generating periodic events
44 * * Synchronizing actions
45 * * Real-time clocking
46 * * Polling
47 *
48 * An additional use case is to implement a watchdog used for recovering from a CPU or
49 * firmware failure.
50 *
51 * \section group_mcwdt_configuration Configuration Considerations
52 *
53 * Each MCWDT may be configured for a particular product.
54 * One MCWDT block can be associated with only one CPU during runtime.
55 * A single MCWDT is not intended to be used by multiple CPUs simultaneously.
56 * Each block contains three sub-counters, each of which can be configured for
57 * various system utility functions - free running counter, periodic interrupts,
58 * watchdog reset, or three interrupts followed by a watchdog reset.
59 * All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded
60 * counter.
61 * A simplified diagram of the MCWDT hardware is shown below:
62 * \image html mcwdt.png
63 * The frequency of the periodic interrupts can be configured using the Match
64 * value with combining Clear on match option, which can be set individually
65 * for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option
66 * is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur
67 * after 65535 counts and the match value defines the shift between interrupts
68 * (see the figure below). The enabled Clear on match option
69 * resets the counter when the interrupt occurs.
70 * \image html mcwdt_counters.png
71 * 32-bit sub-counter C2 does not have Clear on match option.
72 * The interrupt of counter C2 occurs when the counts equal
73 * 2<sup>Toggle bit</sup> value.
74 * \image html mcwdt_subcounters.png
75 * To set up an MCWDT, provide the configuration parameters in the
76 * cy_stc_mcwdt_config_t structure. Then call
77 * Cy_MCWDT_Init() to initialize the driver.
78 * Call Cy_MCWDT_Enable() to enable all specified counters.
79 *
80 * You can also set the mode of operation for any counter. If you choose
81 * interrupt mode, use Cy_MCWDT_SetInterruptMask() with the
82 * parameter for the masks described in Macro Section. All counter interrupts
83 * are OR'd together to from a single combined MCWDT interrupt.
84 * Additionally, enable the Global interrupts and initialize the referenced
85 * interrupt by setting the priority and the interrupt vector using
86 * \ref Cy_SysInt_Init() of the sysint driver.
87 *
88 * The values of the MCWDT counters can be monitored using
89 * Cy_MCWDT_GetCount().
90 *
91 * \note In addition to the MCWDTs, each device has a separate watchdog timer
92 * (WDT) that can also be used to generate a watchdog reset or periodic
93 * interrupts. For more information on the WDT, see the appropriate section
94 * of the PDL.
95 *
96 * \section group_mcwdt_more_information More Information
97 *
98 * For more information on the MCWDT peripheral, refer to
99 * the technical reference manual (TRM).
100 *
101 * \section group_mcwdt_changelog Changelog
102 * <table class="doxtable">
103 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
104 * <tr>
105 * <td>1.50.1</td>
106 * <td>Minor documentation updates.</td>
107 * <td>Documentation enhancement.</td>
108 * </tr>
109 * <tr>
110 * <td>1.50</td>
111 * <td>Added support for new family of devices.</td>
112 * <td>New device support.</td>
113 * </tr>
114 * <tr>
115 * <td>1.40</td>
116 * <td>Fixed/documented MISRA 2012 violations.</td>
117 * <td>MISRA 2012 compliance.</td>
118 * </tr>
119 * <tr>
120 * <td>1.30.1</td>
121 * <td>Minor documentation updates.</td>
122 * <td>Documentation enhancement.</td>
123 * </tr>
124 * <tr>
125 * <td>1.30</td>
126 * <td>In version 1.20 the Cy_MCWDT_GetCountCascaded() function
127 * returned the wrong value when counter#1 overflowed.
128 * This bug is corrected in version 1.30.
129 * </td>
130 * <td>Defect fixes.
131 * </td>
132 * </tr>
133 * <tr>
134 * <td rowspan="2">1.20</td>
135 * <td>Flattened the organization of the driver source code into the single
136 * source directory and the single include directory.
137 * </td>
138 * <td>Driver library directory-structure simplification.</td>
139 * </tr>
140 * <tr>
141 * <td>Added register access layer. Use register access macros instead
142 * of direct register access using dereferenced pointers.</td>
143 * <td>Makes register access device-independent, so that the PDL does
144 * not need to be recompiled for each supported part number.</td>
145 * </tr>
146 * <tr>
147 * <td>1.10.1</td>
148 * <td>Updated description of the \ref cy_stc_mcwdt_config_t structure type</td>
149 * <td>Documentation update and clarification</td>
150 * </tr>
151 * <tr>
152 * <td>1.10</td>
153 * <td>Added input parameter validation to the API functions.<br>
154 * Added API function GetCountCascaded()</td>
155 * <td></td>
156 * </tr>
157 * <tr>
158 * <td>1.0</td>
159 * <td>Initial version</td>
160 * <td></td>
161 * </tr>
162 * </table>
163 *
164 * \defgroup group_mcwdt_macros Macros
165 * \defgroup group_mcwdt_functions Functions
166 * \defgroup group_mcwdt_data_structures Data Structures
167 * \defgroup group_mcwdt_enums Enumerated Types
168 */
169
170 #ifndef CY_MCWDT_H
171 #define CY_MCWDT_H
172
173 #if defined(__cplusplus)
174 extern "C" {
175 #endif
176
177 #include "cy_device.h"
178
179 #if defined (CY_IP_MXS40SRSS_MCWDT) || defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS)
180
181 #include <stdbool.h>
182 #include <stddef.h>
183 #include "cy_syslib.h"
184
185 /**
186 * \addtogroup group_mcwdt_data_structures
187 * \{
188 */
189
190 /** The MCWDT component configuration structure. */
191 typedef struct
192 {
193 uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout.
194 Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for
195 c0ClearOnMatch = 1. */
196 uint16_t c1Match; /**< The sub-counter#1 match comparison value, for interrupt or watchdog timeout.
197 Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for
198 c1ClearOnMatch = 1. */
199 uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
200 \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */
201 uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
202 \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */
203 uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value.
204 Range: 0 - 31. */
205 uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE
206 and \ref CY_MCWDT_MODE_INT. */
207 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS)
208 /**
209 * \note
210 * This parameter is available for CAT1B devices.
211 **/
212 uint16_t c0LowerLimit; /**< Lower limit for sub-counter 0 of this MCWDT.
213 Range: 0 - 65535. */
214 /**
215 * \note
216 * This parameter is available for CAT1B devices.
217 **/
218 uint16_t c1LowerLimit; /**< Lower limit for sub-counter 0 of this MCWDT.
219 Range: 0 - 65535. */
220 /**
221 * \note
222 * This parameter is available for CAT1B devices.
223 **/
224 uint16_t c0LowerLimitMode; /**< Watchdog Counter Action on service before lower limit.
225 Range: 0 - 2., 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset */
226 /**
227 * \note
228 * This parameter is available for CAT1B devices.
229 **/
230 uint16_t c1LowerLimitMode; /**< Watchdog Counter Action on service before lower limit.
231 Range: 0 - 2., 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset */
232 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS */
233
234 /**
235 * \note
236 * This parameter is available for devices having MXS40SSRSS IP.
237 **/
238
239 #if defined (CY_IP_MXS40SSRSS)
240 uint8_t c0c1carryoutconfig; /**< Carryout behaviour that applies when counter 0 and 1 are cascaded
241 0: carry out on counter 0 match, 1: carry out on counter 0 roll-over */
242 uint8_t c0c1matchconfig; /**< Matching behaviour that applies when counter 0 and 1 are cascaded
243 0: Match based on counter 1 alone, 1: Match based on counter 1 and 0 simulataneously */
244 uint8_t c1c2carryoutconfig; /**< Carryout behaviour that applies when counter 1 and 2 are cascaded
245 0: carry out on counter 1 match, 1: carry out on counter 1 roll-over */
246 uint8_t c1c2matchconfig; /**< Matching behaviour that applies when counter 1 and 2 are cascaded
247 0: Match based on counter 1 alone, 1: Match based on counter 2 and 1 simulataneously */
248 #endif /* CY_IP_MXS40SSRSS */
249 bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. */
250 bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. */
251 bool c0c1Cascade; /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade. */
252 bool c1c2Cascade; /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. */
253 } cy_stc_mcwdt_config_t;
254
255 /** \} group_mcwdt_data_structures */
256
257 /**
258 * \addtogroup group_mcwdt_macros
259 * \{
260 */
261
262 /** Driver major version */
263 #define CY_MCWDT_DRV_VERSION_MAJOR 1
264
265 /** Driver minor version */
266 #define CY_MCWDT_DRV_VERSION_MINOR 50
267
268 /** \cond INTERNAL_MACROS */
269
270 /***************************************
271 * Registers Constants
272 ***************************************/
273
274 #define CY_MCWDT_LOCK_CLR0 (1u)
275 #define CY_MCWDT_LOCK_CLR1 (2u)
276 #define CY_MCWDT_LOCK_SET01 (3u)
277
278 #define CY_MCWDT_BYTE_SHIFT (8u)
279 #define CY_MCWDT_C0C1_MODE_MASK (3u)
280 #define CY_MCWDT_C2_MODE_MASK (1u)
281
282
283 /***************************************
284 * API Constants
285 ***************************************/
286
287 #define CY_MCWDT_ALL_WDT_ENABLE_Msk (MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk | MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk | \
288 MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk)
289
290 #define CY_MCWDT_CTR0_Pos (0u)
291 #define CY_MCWDT_CTR1_Pos (1u)
292 #define CY_MCWDT_CTR2_Pos (2u)
293 #define CY_MCWDT_CTR_Pos (0UL)
294
295 /** \endcond */
296
297 #define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */
298
299 #define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions
300 that handle multiple counters, including Cy_MCWDT_Enable(),
301 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
302 #define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions
303 that handle multiple counters, including Cy_MCWDT_Enable(),
304 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
305 #define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions
306 that handle multiple counters, including Cy_MCWDT_Enable(),
307 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
308 #define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions
309 that handle multiple counters, including Cy_MCWDT_Enable(),
310 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
311
312 /** \} group_mcwdt_macros */
313
314
315 /**
316 * \addtogroup group_mcwdt_enums
317 * \{
318 */
319
320 /** The mcwdt sub-counter identifiers. */
321 typedef enum
322 {
323 CY_MCWDT_COUNTER0, /**< Sub-counter#0 identifier. */
324 CY_MCWDT_COUNTER1, /**< Sub-counter#1 identifier. */
325 CY_MCWDT_COUNTER2 /**< Sub-counter#2 identifier. */
326 } cy_en_mcwdtctr_t;
327
328 /** The mcwdt modes. */
329 typedef enum
330 {
331 CY_MCWDT_MODE_NONE, /**< The No action mode. It is used for Set/GetMode functions. */
332 CY_MCWDT_MODE_INT, /**< The Interrupt mode. It is used for Set/GetMode functions. */
333 CY_MCWDT_MODE_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */
334 CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for
335 Set/GetMode functions. */
336 } cy_en_mcwdtmode_t;
337
338 /** The mcwdt cascading. */
339 typedef enum
340 {
341 CY_MCWDT_CASCADE_NONE, /**< The cascading is disabled. It is used for Set/GetCascade functions. */
342 CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade.
343 It is used for Set/GetCascade functions. */
344 CY_MCWDT_CASCADE_C1C2, /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
345 It is used for Set/GetCascade functions. */
346 CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade
347 and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
348 It is used for Set/GetCascade functions. */
349 } cy_en_mcwdtcascade_t;
350
351 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS)
352 /** The mcwdt lower limit identifiers. */
353 /**
354 * \note
355 * This enum is available for CAT1B devices.
356 **/
357 typedef enum
358 {
359 CY_MCWDT_LOWER_LIMIT0, /**< Lower limit for Sub-counter#0 identifier. */
360 CY_MCWDT_LOWER_LIMIT1, /**< Lower limit for Sub-counter#1 identifier. */
361 } cy_en_mcwdtlowerlimit_t;
362
363 /** The mcwdt lower limit mode identifiers. */
364 /**
365 * \note
366 * This enum is available for CAT1B devices.
367 **/
368 typedef enum
369 {
370 CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, /**< Do nothing. */
371 CY_MCWDT_LOWER_LIMIT_MODE_INT, /**< Assert WDT_INTx. */
372 CY_MCWDT_LOWER_LIMIT_MODE_RESET, /**< Assert WDT Reset. */
373 } cy_en_mcwdtlowerlimitmode_t;
374 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS*/
375
376 #if defined (CY_IP_MXS40SSRSS)
377 /** The mcwdt carryout config used during cascading. */
378 /**
379 * \note
380 * This enum is available for CAT1B devices.
381 **/
382 typedef enum
383 {
384 CY_MCWDT_CASCADE_CARRYOUT_CONFIG_MATCH, /**< For CY_MCWDT_CASCADE_C0C1: carry out on counter 0 match,
385 For CY_MCWDT_CASCADE_C1C2: carry out on counter 1 match */
386 CY_MCWDT_CASCADE_CARRYOUT_CONFIG_ROLLOVER, /**< For CY_MCWDT_CASCADE_C0C1: carry out on counter 0 rollover,
387 For CY_MCWDT_CASCADE_C1C2: carry out on counter 1 rollover */
388 } cy_en_mcwdtcascadecarryoutconfig_t ;
389
390 /** The mcwdt match config used during cascading. */
391 /**
392 * \note
393 * This enum is available for CAT1B devices.
394 **/
395 typedef enum
396 {
397 CY_MCWDT_CASCADE_MATCH_CONFIG_COUNTER, /**< For CY_MCWDT_CASCADE_C0C1: Based on counter 1 alone,
398 For CY_MCWDT_CASCADE_C1C2: Based on counter 2 alone */
399 CY_MCWDT_CASCADE_MATCH_CONFIG_CASCADE, /**< For CY_MCWDT_CASCADE_C0C1: Based on counter 1 and 0 simulataneously,
400 For CY_MCWDT_CASCADE_C1C2: Based on counter 2 and 1 simulataneously */
401 } cy_en_mcwdtcascadematchconfig_t ;
402
403 #endif /* CY_IP_MXS40SSRSS*/
404 /** The MCWDT error codes. */
405 typedef enum
406 {
407 CY_MCWDT_SUCCESS = 0x00u, /**< Successful */
408 CY_MCWDT_BAD_PARAM = CY_MCWDT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
409 } cy_en_mcwdt_status_t;
410
411 /** \} group_mcwdt_enums */
412
413
414 /** \cond PARAM_CHECK_MACROS */
415
416 /** Parameter check macros */
417 #define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk))
418
419 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS)
420 #define CY_MCWDT_IS_LOWER_LIMIT_VALID(counter) ((CY_MCWDT_LOWER_LIMIT0 == (counter)) || \
421 (CY_MCWDT_LOWER_LIMIT1 == (counter)))
422
423 #define CY_MCWDT_IS_LOWER_LIMIT_MODE_VALID(mode) ((CY_MCWDT_LOWER_LIMIT_MODE_NOTHING == (mode)) || \
424 (CY_MCWDT_LOWER_LIMIT_MODE_INT == (mode)) || \
425 (CY_MCWDT_LOWER_LIMIT_MODE_RESET == (mode)))
426 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS */
427 #if defined (CY_IP_MXS40SSRSS)
428 #define CY_MCWDT_IS_CASCADE_CARRYOUT_CONFIG_VALID(mode) ((CY_MCWDT_CASCADE_CARRYOUT_CONFIG_MATCH == (mode)) || \
429 (CY_MCWDT_CASCADE_CARRYOUT_CONFIG_ROLLOVER == (mode)))
430
431 #define CY_MCWDT_IS_CASCADE_MATCH_CONFIG_VALID(mode) ((CY_MCWDT_CASCADE_MATCH_CONFIG_COUNTER == (mode)) || \
432 (CY_MCWDT_CASCADE_MATCH_CONFIG_CASCADE == (mode)))
433
434 #endif /* CY_IP_MXS40SSRSS */
435 #define CY_MCWDT_IS_CNT_NUM_VALID(counter) ((CY_MCWDT_COUNTER0 == (counter)) || \
436 (CY_MCWDT_COUNTER1 == (counter)) || \
437 (CY_MCWDT_COUNTER2 == (counter)))
438
439 #define CY_MCWDT_IS_MODE_VALID(mode) ((CY_MCWDT_MODE_NONE == (mode)) || \
440 (CY_MCWDT_MODE_INT == (mode)) || \
441 (CY_MCWDT_MODE_RESET == (mode)) || \
442 (CY_MCWDT_MODE_INT_RESET == (mode)))
443
444 #define CY_MCWDT_IS_ENABLE_VALID(enable) (1UL >= (enable))
445
446
447 #define CY_MCWDT_IS_CASCADE_VALID(cascade) ((CY_MCWDT_CASCADE_NONE == (cascade)) || \
448 (CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
449 (CY_MCWDT_CASCADE_C1C2 == (cascade)) || \
450 (CY_MCWDT_CASCADE_BOTH == (cascade)))
451
452 #define CY_MCWDT_IS_MATCH_VALID(clearOnMatch, match) ((clearOnMatch) ? (1UL <= (match)) : true)
453
454 #define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit))
455
456
457 /** \endcond */
458
459
460 /*******************************************************************************
461 * Function Prototypes
462 *******************************************************************************/
463
464 /**
465 * \addtogroup group_mcwdt_functions
466 * \{
467 */
468 cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config);
469 void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base);
470 __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
471 __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
472 __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
473 __STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base);
474 __STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base);
475 __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base);
476 __STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode);
477 __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
478 __STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
479 __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
480 __STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade);
481 __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base);
482 __STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs);
483 __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
484 __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit);
485 __STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base);
486 __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
487 __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
488 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base);
489 __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
490 __STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
491 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base);
492 __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters);
493 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base);
494 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS)
495 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter);
496 __STATIC_INLINE void Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, uint32_t lowerLimit, uint16_t waitUs);
497 __STATIC_INLINE cy_en_mcwdtlowerlimitmode_t Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter);
498 __STATIC_INLINE void Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, cy_en_mcwdtlowerlimitmode_t mode);
499 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const *base);
500 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS */
501
502 #if defined (CY_IP_MXS40SSRSS)
503 __STATIC_INLINE uint32_t Cy_MCWDT_GetCascadeCarryOutMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter);
504 __STATIC_INLINE void Cy_MCWDT_SetCascadeCarryOutMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, cy_en_mcwdtcascadecarryoutconfig_t carryoutconfig);
505
506 __STATIC_INLINE uint32_t Cy_MCWDT_GetCascadeMatchMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter);
507 __STATIC_INLINE void Cy_MCWDT_SetCascadeMatchMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, cy_en_mcwdtcascadematchconfig_t matchconfig);
508
509
510 #endif /* CY_IP_MXS40SSRSS */
511 uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base);
512
513
514 /*******************************************************************************
515 * Function Name: Cy_MCWDT_Enable
516 ****************************************************************************//**
517 *
518 * Enables all specified counters.
519 *
520 * \param base
521 * The base pointer to a structure that describes registers.
522 *
523 * \param counters
524 * OR of all counters to enable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
525 * CY_MCWDT_CTR2 macros.
526 *
527 * \param waitUs
528 * The function waits for some delay in microseconds before returning,
529 * because the counter begins counting after two lf_clk cycles pass.
530 * The recommended value is 93 us.
531 * \note
532 * Setting this parameter to a zero means No wait. In this case, it is
533 * the user's responsibility to check whether the selected counters were enabled
534 * immediately after the function call. This can be done by the
535 * Cy_MCWDT_GetEnabledStatus() API.
536 *
537 *******************************************************************************/
Cy_MCWDT_Enable(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)538 __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
539 {
540 uint32_t enableCounters;
541
542 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
543
544 /* Extract particular counters for enable */
545 enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
546 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
547 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
548
549 MCWDT_STRUCT_MCWDT_CTL(base) |= enableCounters;
550
551 Cy_SysLib_DelayUs(waitUs);
552 }
553
554
555 /*******************************************************************************
556 * Function Name: Cy_MCWDT_Disable
557 ****************************************************************************//**
558 *
559 * Disables all specified counters.
560 *
561 * \param base
562 * The base pointer to a structure describing registers.
563 *
564 * \param counters
565 * OR of all counters to disable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
566 * CY_MCWDT_CTR2 macros.
567 *
568 * \param waitUs
569 * The function waits for some delay in microseconds before returning,
570 * because the counter stops counting after two lf_clk cycles pass.
571 * The recommended value is 93 us.
572 * \note
573 * Setting this parameter to a zero means No wait. In this case, it is
574 * the user's responsibility to check whether the selected counters were disabled
575 * immediately after the function call. This can be done by the
576 * Cy_MCWDT_GetEnabledStatus() API.
577 *
578 *******************************************************************************/
Cy_MCWDT_Disable(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)579 __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
580 {
581 uint32_t disableCounters;
582
583 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
584
585 /* Extract particular counters for disable */
586 disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
587 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
588 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
589
590 MCWDT_STRUCT_MCWDT_CTL(base) &= ~disableCounters;
591
592 Cy_SysLib_DelayUs(waitUs);
593 }
594
595
596 /*******************************************************************************
597 * Function Name: Cy_MCWDT_GetEnabledStatus
598 ****************************************************************************//**
599 *
600 * Reports the enabled status of the specified counter.
601 *
602 * \param base
603 * The base pointer to a structure that describes registers.
604 *
605 * \param counter
606 * The number of the MCWDT counter. The valid range is [0-2].
607 *
608 * \return
609 * The status of the MCWDT counter: 0 = disabled, 1 = enabled.
610 *
611 *******************************************************************************/
Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)612 __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
613 {
614 uint32_t status = 0u;
615
616 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
617
618 switch (counter)
619 {
620 case CY_MCWDT_COUNTER0:
621 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0, MCWDT_STRUCT_MCWDT_CTL(base));
622 break;
623 case CY_MCWDT_COUNTER1:
624 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1, MCWDT_STRUCT_MCWDT_CTL(base));
625 break;
626 case CY_MCWDT_COUNTER2:
627 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2, MCWDT_STRUCT_MCWDT_CTL(base));
628 break;
629
630 default:
631 CY_ASSERT(0u != 0u);
632 break;
633 }
634
635 return (status);
636 }
637
638
639 /*******************************************************************************
640 * Function Name: Cy_MCWDT_Lock
641 ****************************************************************************//**
642 *
643 * Locks out configuration changes to all MCWDT registers.
644 *
645 * \param base
646 * The base pointer to a structure that describes registers.
647 *
648 *******************************************************************************/
Cy_MCWDT_Lock(MCWDT_STRUCT_Type * base)649 __STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base)
650 {
651 uint32_t interruptState;
652
653 interruptState = Cy_SysLib_EnterCriticalSection();
654
655 MCWDT_STRUCT_MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_SET01);
656
657 Cy_SysLib_ExitCriticalSection(interruptState);
658 }
659
660
661 /*******************************************************************************
662 * Function Name: Cy_MCWDT_Unlock
663 ****************************************************************************//**
664 *
665 * Unlocks the MCWDT configuration registers.
666 *
667 * \param base
668 * The base pointer to a structure that describes registers.
669 *
670 *******************************************************************************/
Cy_MCWDT_Unlock(MCWDT_STRUCT_Type * base)671 __STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base)
672 {
673 uint32_t interruptState;
674
675 interruptState = Cy_SysLib_EnterCriticalSection();
676
677 MCWDT_STRUCT_MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR0);
678 MCWDT_STRUCT_MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR1);
679
680 Cy_SysLib_ExitCriticalSection(interruptState);
681 }
682
683
684 /*******************************************************************************
685 * Function Name: Cy_MCWDT_GetLockStatus
686 ****************************************************************************//**
687 *
688 * Reports the locked/unlocked state of the MCWDT.
689 *
690 * \param base
691 * The base pointer to a structure that describes registers.
692 *
693 * \return
694 * The state of the MCWDT counter: 0 = unlocked, 1 = locked.
695 *
696 *******************************************************************************/
Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const * base)697 __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base)
698 {
699 return ((0UL != (MCWDT_STRUCT_MCWDT_LOCK(base) & MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk)) ? 1UL : 0UL);
700 }
701
702
703 /*******************************************************************************
704 * Function Name: Cy_MCWDT_SetMode
705 ****************************************************************************//**
706 *
707 * Sets the mode of the specified counter.
708 *
709 * \param base
710 * The base pointer to a structure that describes registers.
711 *
712 * \param counter
713 * The number of the WDT counter. The valid range is [0-2].
714 *
715 * \param mode
716 * The mode of operation for the counter. See enum typedef cy_en_mcwdtmode_t.
717 *
718 * \note
719 * The mode for Counter 2 can be set only to CY_MCWDT_MODE_NONE or CY_MCWDT_MODE_INT.
720 *
721 * \note
722 * This API must not be called while the counters are running.
723 * Prior to calling this API, the counter must be disabled.
724 *
725 *******************************************************************************/
Cy_MCWDT_SetMode(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,cy_en_mcwdtmode_t mode)726 __STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode)
727 {
728 uint32_t mask, shift;
729
730 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
731 CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID(mode));
732
733 shift = CY_MCWDT_BYTE_SHIFT * ((uint32_t)counter);
734 mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
735 mask = mask << shift;
736
737 MCWDT_STRUCT_MCWDT_CONFIG(base) = (MCWDT_STRUCT_MCWDT_CONFIG(base) & ~mask) | ((uint32_t) mode << shift);
738 }
739
740
741 /*******************************************************************************
742 * Function Name: Cy_MCWDT_GetMode
743 ****************************************************************************//**
744 *
745 * Reports the mode of the specified counter.
746 *
747 * \param base
748 * The base pointer to a structure that describes registers.
749 *
750 * \param counter
751 * The number of the WDT counter. The valid range is [0-2].
752 *
753 * \return
754 * The current mode of the counter. See enum typedef cy_en_mcwdtmode_t.
755 *
756 *******************************************************************************/
Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)757 __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
758 {
759 uint32_t mode, mask;
760
761 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
762
763 mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
764 mode = (MCWDT_STRUCT_MCWDT_CONFIG(base) >> (CY_MCWDT_BYTE_SHIFT * ((uint32_t)counter))) & mask;
765
766 return ((cy_en_mcwdtmode_t) mode);
767 }
768
769
770 /*******************************************************************************
771 * Function Name: Cy_MCWDT_SetClearOnMatch
772 ****************************************************************************//**
773 *
774 * Sets the Clear on match option for the specified counter.
775 *
776 * \param base
777 * The base pointer to a structure that describes registers.
778 *
779 * \param counter
780 * The number of the WDT counter. The valid range is [0-1].
781 *
782 * \note
783 * The match values are not supported by Counter 2.
784 *
785 * \param enable
786 * Set 0 to disable; 1 to enable.
787 *
788 * \note
789 * This API must not be called while the counters are running.
790 * Prior to calling this API, the counter must be disabled.
791 *
792 *******************************************************************************/
Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,uint32_t enable)793 __STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
794 {
795 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
796 CY_ASSERT_L2(CY_MCWDT_IS_ENABLE_VALID(enable));
797
798 if (CY_MCWDT_COUNTER0 == counter)
799 {
800 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, enable);
801 }
802 else
803 {
804 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, enable);
805 }
806 }
807
808
809 /*******************************************************************************
810 * Function Name: Cy_MCWDT_GetClearOnMatch
811 ****************************************************************************//**
812 *
813 * Reports the Clear on match setting for the specified counter.
814 *
815 * \param base
816 * The base pointer to a structure that describes registers.
817 *
818 * \param counter
819 * The number of the WDT counter. The valid range is [0-1].
820 *
821 * \return
822 * The Clear on match status: 1 = enabled, 0 = disabled.
823 *
824 * \note
825 * The match value is not supported by Counter 2.
826 *
827 *******************************************************************************/
Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)828 __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
829 {
830 uint32_t getClear;
831
832 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
833
834 if (CY_MCWDT_COUNTER0 == counter)
835 {
836 getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, MCWDT_STRUCT_MCWDT_CONFIG(base));
837 }
838 else
839 {
840 getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, MCWDT_STRUCT_MCWDT_CONFIG(base));
841 }
842
843 return (getClear);
844 }
845
846
847 /*******************************************************************************
848 * Function Name: Cy_MCWDT_SetCascade
849 ****************************************************************************//**
850 *
851 * Sets all the counter cascade options.
852 *
853 * \param base
854 * The base pointer to a structure that describes registers.
855 *
856 * \param cascade
857 * Sets or clears each of the cascade options.
858 *
859 * \note
860 * This API must not be called when the counters are running.
861 * Prior to calling this API, the counter must be disabled.
862 *
863 *******************************************************************************/
Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t cascade)864 __STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade)
865 {
866 CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade));
867
868 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1,
869 (uint32_t) cascade);
870 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2,
871 ((uint32_t) cascade >> 1u));
872 }
873
874
875 /*******************************************************************************
876 * Function Name: Cy_MCWDT_GetCascade
877 ****************************************************************************//**
878 *
879 * Reports all the counter cascade option settings.
880 *
881 * \param base
882 * The base pointer to a structure that describes registers.
883 *
884 * \return
885 * The current cascade option values.
886 *
887 *******************************************************************************/
Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const * base)888 __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base)
889 {
890 uint32_t cascade;
891
892 cascade = (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, MCWDT_STRUCT_MCWDT_CONFIG(base)) << 1u) |
893 _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1, MCWDT_STRUCT_MCWDT_CONFIG(base));
894
895 return ((cy_en_mcwdtcascade_t) cascade);
896 }
897
898
899 /*******************************************************************************
900 * Function Name: Cy_MCWDT_SetMatch
901 ****************************************************************************//**
902 *
903 * Sets the match comparison value for the specified counter (0 or 1).
904 *
905 * \param base
906 * The base pointer to a structure that describes registers.
907 *
908 * \param counter
909 * The number of the WDT counter. The valid range is [0-1].
910 *
911 * \param match
912 * The value to match against the counter.
913 * The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0
914 * and [1-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 1.
915 *
916 * \note
917 * The match value is not supported by Counter 2.
918 *
919 * \note
920 * Action on match is taken on the next increment after the counter value
921 * equal to match value.
922 *
923 * \param waitUs
924 * The function waits for some delay in microseconds before returning,
925 * because the match affects after two lf_clk cycles pass. The recommended
926 * value is 93 us.
927 * \note
928 * Setting this parameter to a zero means No wait. This must be taken
929 * into account when changing the match values on the running counters.
930 *
931 *******************************************************************************/
Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,uint32_t match,uint16_t waitUs)932 __STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs)
933 {
934 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
935 CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ? \
936 ((MCWDT_STRUCT_MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) : \
937 ((MCWDT_STRUCT_MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk) > 0U), \
938 match));
939
940 MCWDT_STRUCT_MCWDT_MATCH(base) = (counter == CY_MCWDT_COUNTER0) ?
941 _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_MATCH(base), MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0,
942 (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk)) :
943 _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_MATCH(base), MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1,
944 (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk));
945
946 Cy_SysLib_DelayUs(waitUs);
947 }
948
949
950 /*******************************************************************************
951 * Function Name: Cy_MCWDT_GetMatch
952 ****************************************************************************//**
953 *
954 * Reports the match comparison value for the specified counter (0 or 1).
955 *
956 * \param base
957 * The base pointer to a structure that describes registers.
958 *
959 * \param counter
960 * The number of the WDT counter. The valid range is [0-1].
961 *
962 * \note
963 * The match values are not supported by Counter 2.
964 *
965 * \return
966 * A 16-bit match value.
967 *
968 *******************************************************************************/
Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)969 __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
970 {
971 uint32_t match;
972
973 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
974
975 match = (counter == CY_MCWDT_COUNTER0) ? _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, MCWDT_STRUCT_MCWDT_MATCH(base)) :
976 _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, MCWDT_STRUCT_MCWDT_MATCH(base));
977
978 return (match);
979 }
980
981
982 /*******************************************************************************
983 * Function Name: Cy_MCWDT_SetToggleBit
984 ****************************************************************************//**
985 *
986 * Sets a bit in Counter 2 to monitor for a toggle.
987 *
988 * \param base
989 * The base pointer to a structure that describes registers.
990 *
991 * \param bit
992 * The Counter 2 bit is set to monitor for a toggle. The valid range [0-31].
993 *
994 * \note
995 * This API must not be called when counters are running.
996 * Prior to calling this API, the counter must be disabled.
997 *
998 *******************************************************************************/
Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type * base,uint32_t bit)999 __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit)
1000 {
1001 CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit));
1002
1003 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit);
1004 }
1005
1006
1007 /*******************************************************************************
1008 * Function Name: Cy_MCWDT_GetToggleBit
1009 ****************************************************************************//**
1010 *
1011 * Reports which bit in Counter 2 is monitored for a toggle.
1012 *
1013 * \param base
1014 * The base pointer to a structure that describes registers.
1015 *
1016 * \return
1017 * The bit that is monitored (range 0 to 31).
1018 *
1019 *******************************************************************************/
Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const * base)1020 __STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base)
1021 {
1022 return (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, MCWDT_STRUCT_MCWDT_CONFIG(base)));
1023 }
1024
1025
1026 /*******************************************************************************
1027 * Function Name: Cy_MCWDT_GetCount
1028 ****************************************************************************//**
1029 *
1030 * Reports the current counter value of the specified counter.
1031 *
1032 * \param base
1033 * The base pointer to a structure that describes registers.
1034 *
1035 * \param counter
1036 * The number of the WDT counter. The valid range is [0-2].
1037 *
1038 * \return
1039 * A live counter value. Counters 0 and 1 are 16-bit counters and Counter 2 is
1040 * a 32-bit counter.
1041 *
1042 *******************************************************************************/
Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)1043 __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
1044 {
1045 uint32_t countVal = 0u;
1046
1047 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1048
1049 switch (counter)
1050 {
1051 case CY_MCWDT_COUNTER0:
1052 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0, MCWDT_STRUCT_MCWDT_CNTLOW(base));
1053 break;
1054 case CY_MCWDT_COUNTER1:
1055 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1, MCWDT_STRUCT_MCWDT_CNTLOW(base));
1056 break;
1057 case CY_MCWDT_COUNTER2:
1058 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2, MCWDT_STRUCT_MCWDT_CNTHIGH(base));
1059 break;
1060
1061 default:
1062 CY_ASSERT(0u != 0u);
1063 break;
1064 }
1065
1066 return (countVal);
1067 }
1068
1069
1070 /*******************************************************************************
1071 * Function Name: Cy_MCWDT_ResetCounters
1072 ****************************************************************************//**
1073 *
1074 * Resets all specified counters.
1075 *
1076 * \param base
1077 * The base pointer to a structure that describes registers.
1078 *
1079 * \param counters
1080 * OR of all counters to reset. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1081 * CY_MCWDT_CTR2 macros.
1082 *
1083 * \param waitUs
1084 * The function waits for some delay in microseconds before returning, because
1085 * a reset occurs after one lf_clk cycle passes. The recommended value is 62 us.
1086 * \note This function resets the counters two times to prevent the case when
1087 * the Counter 1 is not reset when the counters are cascaded. The delay waitUs
1088 * must be greater than 100 us when the counters are cascaded.
1089 * The total delay is greater than 2*waitUs because the function has
1090 * the delay after the first reset.
1091 * \note
1092 * Setting this parameter to a zero means No wait. In this case, it is the
1093 * user's responsibility to check whether the selected counters were reset
1094 * immediately after the function call. This can be done by the
1095 * Cy_MCWDT_GetCount() API.
1096 *
1097 *******************************************************************************/
Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)1098 __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
1099 {
1100 uint32_t resetCounters;
1101
1102 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1103
1104 /* Extract particular counters for reset */
1105 resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) |
1106 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) |
1107 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk : 0UL);
1108
1109 MCWDT_STRUCT_MCWDT_CTL(base) |= resetCounters;
1110
1111 Cy_SysLib_DelayUs(waitUs);
1112
1113 MCWDT_STRUCT_MCWDT_CTL(base) |= resetCounters;
1114
1115 Cy_SysLib_DelayUs(waitUs);
1116 }
1117
1118
1119 /*******************************************************************************
1120 * Function Name: Cy_MCWDT_GetInterruptStatus
1121 ****************************************************************************//**
1122 *
1123 * Reports the state of all MCWDT interrupts.
1124 *
1125 * \param base
1126 * The base pointer to a structure that describes registers.
1127 *
1128 * \return
1129 * The OR'd state of the interrupts. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1130 * CY_MCWDT_CTR2 macros.
1131 *
1132 *******************************************************************************/
Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const * base)1133 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base)
1134 {
1135 return (MCWDT_STRUCT_MCWDT_INTR(base));
1136 }
1137
1138
1139 /*******************************************************************************
1140 * Function Name: Cy_MCWDT_ClearInterrupt
1141 ****************************************************************************//**
1142 *
1143 * Clears all specified MCWDT interrupts.
1144 *
1145 * All the WDT interrupts must be cleared by the firmware; otherwise
1146 * interrupts are generated continuously.
1147 *
1148 * \param base
1149 * The base pointer to a structure describes registers.
1150 *
1151 * \param counters
1152 * OR of all interrupt sources to clear. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1153 * CY_MCWDT_CTR2 macros.
1154 *
1155 *******************************************************************************/
Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type * base,uint32_t counters)1156 __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
1157 {
1158 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1159
1160 MCWDT_STRUCT_MCWDT_INTR(base) = counters;
1161 (void) MCWDT_STRUCT_MCWDT_INTR(base);
1162 }
1163
1164
1165 /*******************************************************************************
1166 * Function Name: Cy_MCWDT_SetInterrupt
1167 ****************************************************************************//**
1168 *
1169 * Sets MCWDT interrupt sources in the interrupt request register.
1170 *
1171 * \param base
1172 * The base pointer to a structure that describes registers.
1173 *
1174 * \param counters
1175 * OR of all interrupt sources to set. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1176 * CY_MCWDT_CTR2 macros.
1177 *
1178 *******************************************************************************/
Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type * base,uint32_t counters)1179 __STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
1180 {
1181 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1182
1183 MCWDT_STRUCT_MCWDT_INTR_SET(base) = counters;
1184 }
1185
1186
1187 /*******************************************************************************
1188 * Function Name: Cy_MCWDT_GetInterruptMask
1189 ****************************************************************************//**
1190 *
1191 * Returns the CWDT interrupt mask register. This register specifies which bits
1192 * from the MCWDT interrupt request register will trigger an interrupt event.
1193 *
1194 * \param base
1195 * The base pointer to a structure that describes registers.
1196 *
1197 * \return
1198 * The OR'd state of the interrupt masks. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1199 * CY_MCWDT_CTR2 macros.
1200 *
1201 *******************************************************************************/
Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const * base)1202 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base)
1203 {
1204 return (MCWDT_STRUCT_MCWDT_INTR_MASK(base));
1205 }
1206
1207
1208 /*******************************************************************************
1209 * Function Name: Cy_MCWDT_SetInterruptMask
1210 ****************************************************************************//**
1211 *
1212 * Writes MCWDT interrupt mask register. This register configures which bits
1213 * from MCWDT interrupt request register will trigger an interrupt event.
1214 *
1215 * \param base
1216 * The base pointer to a structure that describes registers.
1217 *
1218 * \param counters
1219 * OR of all interrupt masks to set. See \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1220 * CY_MCWDT_CTR2 macros.
1221 *
1222 *******************************************************************************/
Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type * base,uint32_t counters)1223 __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters)
1224 {
1225 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1226
1227 MCWDT_STRUCT_MCWDT_INTR_MASK(base) = counters;
1228 }
1229
1230
1231 /*******************************************************************************
1232 * Function Name: Cy_MCWDT_GetInterruptStatusMasked
1233 ****************************************************************************//**
1234 *
1235 * Returns the MCWDT interrupt masked request register. This register contains
1236 * the logical AND of corresponding bits from the MCWDT interrupt request and
1237 * mask registers.
1238 * In the interrupt service routine, this function identifies which of the
1239 * enabled MCWDT interrupt sources caused an interrupt event.
1240 *
1241 * \param base
1242 * The base pointer to a structure that describes registers.
1243 *
1244 * \return
1245 * The current status of enabled MCWDT interrupt sources. See
1246 * the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and CY_MCWDT_CTR2 macros.
1247 *
1248 *******************************************************************************/
Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const * base)1249 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base)
1250 {
1251 return (MCWDT_STRUCT_MCWDT_INTR_MASKED(base));
1252 }
1253
1254 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS)
1255 /*******************************************************************************
1256 * Function Name: Cy_MCWDT_GetLowerLimit
1257 ****************************************************************************//**
1258 *
1259 * Reports the Lower Limit value of the specified counter.
1260 *
1261 * \param base
1262 * The base pointer to a structure that describes registers.
1263 *
1264 * \param counter
1265 * The number of the WDT counter. The valid range is [0-1].
1266 *
1267 * \return
1268 * A Lower Limit value. Counters 0 and 1 are 16-bit counters.
1269 *
1270 * \note
1271 * This API is available for CAT1B devices.
1272 *
1273 *******************************************************************************/
Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const * base,cy_en_mcwdtlowerlimit_t counter)1274 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter)
1275 {
1276 uint32_t countVal = 0u;
1277
1278 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1279
1280 switch (counter)
1281 {
1282 case CY_MCWDT_LOWER_LIMIT0:
1283 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0, MCWDT_STRUCT_MCWDT_LOWER_LIMIT(base));
1284 break;
1285 case CY_MCWDT_LOWER_LIMIT1:
1286 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1, MCWDT_STRUCT_MCWDT_LOWER_LIMIT(base));
1287 break;
1288 default:
1289 CY_ASSERT(0u != 0u);
1290 break;
1291 }
1292
1293 return (countVal);
1294 }
1295
1296 /*******************************************************************************
1297 * Function Name: Cy_MCWDT_SetLowerLimit
1298 ****************************************************************************//**
1299 *
1300 * Sets the lower limit value for the specified counter (0 or 1).
1301 *
1302 * \param base
1303 * The base pointer to a structure that describes registers.
1304 *
1305 * \param counter
1306 * The number of the WDT counter. The valid range is [0-1].
1307 *
1308 * \param lowerLimit
1309 * The value to be written in the lower limit register
1310 * The valid range is [0-65535] for c0
1311 * and [1-65535] for c1.
1312 *
1313 * \note
1314 * The lower limit mode is not supported by Counter 2.
1315 *
1316 * \param waitUs
1317 * The function waits for some delay in microseconds before returning,
1318 * because the lower limit register write affects after two lf_clk cycles pass.
1319 * The recommended value is 93 us.
1320 * \note
1321 * Setting this parameter to a zero means No wait. This must be taken
1322 * into account when changing the lower limit register values.
1323 *
1324 * \note
1325 * This API is available for CAT1B devices.
1326 *
1327 *******************************************************************************/
Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type * base,cy_en_mcwdtlowerlimit_t counter,uint32_t lowerLimit,uint16_t waitUs)1328 __STATIC_INLINE void Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, uint32_t lowerLimit, uint16_t waitUs)
1329 {
1330 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1331
1332 MCWDT_STRUCT_MCWDT_LOWER_LIMIT(base) = (counter == CY_MCWDT_LOWER_LIMIT0) ?
1333 _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_LOWER_LIMIT(base), MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0,
1334 (lowerLimit & MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Msk)) :
1335 _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_LOWER_LIMIT(base), MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1,
1336 (lowerLimit & MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Msk));
1337
1338 Cy_SysLib_DelayUs(waitUs);
1339 }
1340
1341 /*******************************************************************************
1342 * Function Name: Cy_MCWDT_SetLowerLimitMode
1343 ****************************************************************************//**
1344 *
1345 * Sets the lower limit mode option for the specified counter.
1346 *
1347 * \param base
1348 * The base pointer to a structure that describes registers.
1349 *
1350 * \param counter
1351 * The number of the WDT counter. The valid range is [0-1].
1352 *
1353 * \note
1354 * The lower limit mode is not supported by Counter 2.
1355 *
1356 * \param mode
1357 * Set 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset
1358 *
1359 * \note
1360 * This API must not be called while the counters are running.
1361 * Prior to calling this API, the counter must be disabled.
1362 * This API is available for CAT1B devices.
1363 *
1364 *******************************************************************************/
Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type * base,cy_en_mcwdtlowerlimit_t counter,cy_en_mcwdtlowerlimitmode_t mode)1365 __STATIC_INLINE void Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, cy_en_mcwdtlowerlimitmode_t mode)
1366 {
1367 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1368 CY_ASSERT_L2(CY_MCWDT_IS_LOWER_LIMIT_MODE_VALID(mode));
1369
1370 if (CY_MCWDT_LOWER_LIMIT0 == counter)
1371 {
1372 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0, mode);
1373 }
1374 else
1375 {
1376 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1, mode);
1377 }
1378 }
1379
1380 /*******************************************************************************
1381 * Function Name: Cy_MCWDT_GetLowerLimitMode
1382 ****************************************************************************//**
1383 *
1384 * Reports the lower limit mode of the specified counter.
1385 *
1386 * \param base
1387 * The base pointer to a structure that describes registers.
1388 *
1389 * \param counter
1390 * The number of the WDT counter. The valid range is [0-1].
1391 *
1392 * \return
1393 * The current lower limit mode of the counter. See enum typedef cy_en_mcwdtlowerlimitmode_t.
1394 *
1395 * \note
1396 * This API is available for CAT1B devices.
1397 *
1398 *******************************************************************************/
Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const * base,cy_en_mcwdtlowerlimit_t counter)1399 __STATIC_INLINE cy_en_mcwdtlowerlimitmode_t Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter)
1400 {
1401 uint32_t getLowerLimitMode;
1402
1403 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1404
1405 if (CY_MCWDT_LOWER_LIMIT0 == counter)
1406 {
1407 getLowerLimitMode = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0, MCWDT_STRUCT_MCWDT_CONFIG(base));
1408 }
1409 else
1410 {
1411 getLowerLimitMode = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1, MCWDT_STRUCT_MCWDT_CONFIG(base));
1412 }
1413
1414 return (cy_en_mcwdtlowerlimitmode_t)getLowerLimitMode;
1415
1416 }
1417
1418 /*******************************************************************************
1419 * Function Name: Cy_MCWDT_GetLowerLimitCascaded
1420 ****************************************************************************//**
1421 *
1422 * Gets lower limit registers cascaded value.
1423 *
1424 * \param base
1425 * The base pointer to a structure that describes registers.
1426 *
1427 * \note
1428 * The lower limit mode is not supported by Counter 2.
1429 *
1430 * \return
1431 * A 32-bit lower limit register value.
1432 *
1433 * \note
1434 * This API is available for CAT1B devices.
1435 *
1436 *******************************************************************************/
Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const * base)1437 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const *base)
1438 {
1439 return (uint32_t)(MCWDT_STRUCT_MCWDT_LOWER_LIMIT(base));
1440 }
1441 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS */
1442
1443 #if defined (CY_IP_MXS40SSRSS)
1444
1445 /*******************************************************************************
1446 * Function Name: Cy_MCWDT_GetCascadeCarryOutMode
1447 ****************************************************************************//**
1448 *
1449 * Reports the Carry out value of the specified cascaded counter.
1450 *
1451 * \param base
1452 * The base pointer to a structure that describes registers.
1453 *
1454 * \param counter
1455 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1456 *
1457 * \return
1458 * Carry out value for the specified cascade type.
1459 *
1460 * \note
1461 * This API is available for CAT1B devices.
1462 *
1463 *******************************************************************************/
Cy_MCWDT_GetCascadeCarryOutMode(MCWDT_STRUCT_Type const * base,cy_en_mcwdtcascade_t counter)1464 __STATIC_INLINE uint32_t Cy_MCWDT_GetCascadeCarryOutMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter)
1465 {
1466 uint32_t countVal = 0u;
1467
1468 switch (counter)
1469 {
1470 case CY_MCWDT_CASCADE_C0C1:
1471 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1, MCWDT_STRUCT_MCWDT_CONFIG(base));
1472 break;
1473 case CY_MCWDT_CASCADE_C1C2:
1474 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2, MCWDT_STRUCT_MCWDT_CONFIG(base));
1475 break;
1476 default:
1477 CY_ASSERT(0u != 0u);
1478 break;
1479 }
1480
1481 return (countVal);
1482 }
1483
1484 /*******************************************************************************
1485 * Function Name: Cy_MCWDT_SetCascadeCarryOutMode
1486 ****************************************************************************//**
1487 *
1488 * Sets the Carry out mode for the specified cascaded counter.
1489 *
1490 * \param base
1491 * The base pointer to a structure that describes registers.
1492 *
1493 * \param counter
1494 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1495 *
1496 * \param carryoutconfig
1497 * CY_MCWDT_CASCADE_CARRYOUT_CONFIG_MATCH:
1498 * For CY_MCWDT_CASCADE_C0C1: carry out on counter 0 match
1499 * For CY_MCWDT_CASCADE_C1C2: carry out on counter 1 match.
1500 * CY_MCWDT_CASCADE_CARRYOUT_CONFIG_ROLLOVER:
1501 * For CY_MCWDT_CASCADE_C0C1: carry out on counter 0 rollover,
1502 * For CY_MCWDT_CASCADE_C1C2: carry out on counter 1 rollover.
1503 *
1504 * \note
1505 * This API is available for CAT1B devices.
1506 *
1507 *******************************************************************************/
Cy_MCWDT_SetCascadeCarryOutMode(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t counter,cy_en_mcwdtcascadecarryoutconfig_t carryoutconfig)1508 __STATIC_INLINE void Cy_MCWDT_SetCascadeCarryOutMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, cy_en_mcwdtcascadecarryoutconfig_t carryoutconfig)
1509 {
1510 CY_ASSERT_L2(CY_MCWDT_IS_CASCADE_CARRYOUT_CONFIG_VALID(carryoutconfig));
1511
1512 if (CY_MCWDT_CASCADE_C0C1 == counter)
1513 {
1514 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1, carryoutconfig);
1515 }
1516 else
1517 {
1518 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2, carryoutconfig);
1519 }
1520 }
1521
1522 /*******************************************************************************
1523 * Function Name: Cy_MCWDT_GetCascadeMatchMode
1524 ****************************************************************************//**
1525 *
1526 * Reports the match value of the specified cascaded counter.
1527 *
1528 * \param base
1529 * The base pointer to a structure that describes registers.
1530 *
1531 * \param counter
1532 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1533 *
1534 * \return
1535 * Match value for the specified cascade type.
1536 *
1537 * \note
1538 * This API is available for CAT1B devices.
1539 *
1540 *******************************************************************************/
Cy_MCWDT_GetCascadeMatchMode(MCWDT_STRUCT_Type const * base,cy_en_mcwdtcascade_t counter)1541 __STATIC_INLINE uint32_t Cy_MCWDT_GetCascadeMatchMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter)
1542 {
1543 uint32_t countVal = 0u;
1544
1545 switch (counter)
1546 {
1547 case CY_MCWDT_CASCADE_C0C1:
1548 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1, MCWDT_STRUCT_MCWDT_CONFIG(base));
1549 break;
1550 case CY_MCWDT_CASCADE_C1C2:
1551 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2, MCWDT_STRUCT_MCWDT_CONFIG(base));
1552 break;
1553 default:
1554 CY_ASSERT(0u != 0u);
1555 break;
1556 }
1557
1558 return (countVal);
1559 }
1560
1561 /*******************************************************************************
1562 * Function Name: Cy_MCWDT_SetCascadeMatchMode
1563 ****************************************************************************//**
1564 *
1565 * Sets the match config for the specified cascaded counter.
1566 *
1567 * \param base
1568 * The base pointer to a structure that describes registers.
1569 *
1570 * \param counter
1571 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1572 *
1573 * \param matchconfig
1574 * CY_MCWDT_CASCADE_MATCH_CONFIG_COUNTER:
1575 * For CY_MCWDT_CASCADE_C0C1: Based on counter 1 alone
1576 * For CY_MCWDT_CASCADE_C1C2: Based on counter 2 alone
1577 * CY_MCWDT_CASCADE_MATCH_CONFIG_CASCADE:
1578 * For CY_MCWDT_CASCADE_C0C1: Based on counter 1 and 0 simulataneously
1579 * For CY_MCWDT_CASCADE_C1C2: Based on counter 2 and 1 simulataneously
1580 *
1581 * \note
1582 * This API is available for CAT1B devices.
1583 *
1584 *******************************************************************************/
Cy_MCWDT_SetCascadeMatchMode(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t counter,cy_en_mcwdtcascadematchconfig_t matchconfig)1585 __STATIC_INLINE void Cy_MCWDT_SetCascadeMatchMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, cy_en_mcwdtcascadematchconfig_t matchconfig)
1586 {
1587 CY_ASSERT_L2(CY_MCWDT_IS_CASCADE_MATCH_CONFIG_VALID(matchconfig));
1588
1589 if (CY_MCWDT_CASCADE_C0C1 == counter)
1590 {
1591 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1, matchconfig);
1592 }
1593 else
1594 {
1595 MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2, matchconfig);
1596 }
1597 }
1598
1599 #endif /* CY_IP_MXS40SSRSS */
1600
1601 /** \} group_mcwdt_functions */
1602
1603 #endif /* CY_IP_MXS40SRSS_MCWDT, CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS */
1604
1605 #if defined(__cplusplus)
1606 }
1607 #endif
1608
1609 #endif /* CY_MCWDT_H */
1610
1611 /** \} group_mcwdt */
1612
1613 /* [] END OF FILE */
1614
