1 /***************************************************************************//**
2 * \file cy_gpio.h
3 * \version 1.50.1
4 *
5 * Provides an API declaration of the GPIO driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 *     http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24 
25 /**
26 * \addtogroup group_gpio
27 * \{
28 * The GPIO driver provides an API to configure and access device Input/Output pins.
29 *
30 * The functions and other declarations used in this driver are in cy_gpio.h.
31 * You can include cy_pdl.h to get access to all functions
32 * and declarations in the PDL.
33 *
34 * IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and
35 * their variants.
36 *
37 * Initialization can be performed either at the port level or by configuring the
38 * individual pins. For efficient use of code space, port
39 * configuration should be used in the field. Refer to the product device header files
40 * for the list of supported ports and pins.
41 *
42 * A port is represented by GPIO_PRT_Type and a pin is represented by a number
43 * 0 to 7.
44 *
45 * For PSoC 64 devices the the un-intended protected pins (due to constrain on PPU configuration)
46 * are modified using PRA driver. But the GPIO diver does not modify the intended protected pins .
47 *
48 * - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit
49 *   (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled
50 *   cy_stc_gpio_pin_config_t structure).
51 * - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled
52 *   cy_stc_gpio_prt_config_t structure. The values in the structure are
53 *   bitfields representing the desired value for each pin in the port.
54 * - Pin configuration and management is based on the port address and pin number.
55 *   \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port
56 *   address from the port number at run-time.
57 * - Each I/O is individually configurable to one of eight drive modes represented
58 *   by drivemode of cy_stc_gpio_pin_config_t structure.
59 *
60 * Once the pin/port initialization is complete, each pin can be accessed by
61 * specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API
62 * functions.
63 *
64 * \section group_gpio_configuration Configuration Considerations
65 *
66 * 1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection.
67 *    This allows the pin to connect to signal sources/sinks throughout the device,
68 *    as defined by the pin HSIOM selection options (en_hsiom_sel_t).
69 * 2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW
70 *    control digital pin only) at Power-On-Reset(POR).
71 * 3. Some API functions perform read-modify-write operations on shared port
72 *    registers. These functions are not thread safe and care must be taken when
73 *    called by the application.
74 * 4. Digital input buffer provides a high-impedance buffer for the external
75 *    digital input. The input buffer is connected to the HSIOM for routing to
76 *    the CPU port registers and selected peripheral. Enabling the input
77 *    buffer provides possibility to read the pin state via the CPU.
78 *    If pin is connected to an analog signal, the input buffer should be
79 *    disabled to avoid crowbar currents. For more information refer to device
80 *    TRM and the device datasheet.
81 *
82 * Multiple pins on a port can be updated using direct port register writes with an
83 * appropriate port mask. An example is shown below, highlighting the different ways of
84 * configuring Port 1 pins using:
85 *
86 * - Initialize a Pin using cy_stc_gpio_pin_config_t structure
87 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_Init
88 *
89 * - Initialize entire port using cy_stc_gpio_prt_config_t structure
90 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Init
91 *
92 * - Port output data register
93 * - Port output data set register
94 * - Port output data clear register
95 *
96 * \snippet gpio/snippet/main.c Cy_GPIO_Snippet
97 *
98 * \section group_gpio_more_information More Information
99 *
100 * Refer to the technical reference manual (TRM) and the device datasheet.
101 *
102 * \section group_gpio_changelog Changelog
103 * <table class="doxtable">
104 *   <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
105 *   <tr>
106 *     <td>1.50.1</td>
107 *     <td>Updated doxygen for External clock source to HF0.</td>
108 *     <td>Documentation enhancement.</td>
109 *   </tr>
110 *   <tr>
111 *     <td>1.50</td>
112 *     <td>Modified \ref Cy_GPIO_Pin_Init, \ref Cy_GPIO_Pin_FastInit, and
113 *         \ref Cy_GPIO_SetDrivemode APIs to catch wrong drive modes.</td>
114 *     <td>Defect fix.</td>
115 *   </tr>
116 *   <tr>
117 *     <td rowspan="2">1.40</td>
118 *     <td>Changes in Support of the new family of devices</td>
119 *     <td>Added new family of devices</td>
120 *   </tr>
121 *   <tr>
122 *     <td>Changes in support of Secure pins used for External clocks on Secure devices</td>
123 *     <td>Added support for accessing External clocks protected pins</td>
124 *   </tr>
125 *   <tr>
126 *     <td>1.30</td>
127 *     <td>Fixed/documented MISRA 2012 violations.</td>
128 *     <td>MISRA 2012 compliance.</td>
129 *   </tr>
130 *   <tr>
131 *     <td>1.20.1</td>
132 *     <td>Minor documentation updates.</td>
133 *     <td>Documentation enhancement.</td>
134 *   </tr>
135 *   <tr>
136 *     <td rowspan="3">1.20</td>
137 *     <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
138 *     <td>Driver library directory-structure simplification.</td>
139 *   </tr>
140 *   <tr>
141 *     <td>Added the functions for configuring the AMux bus splitter switch cells:
142 *     - \ref Cy_GPIO_SetAmuxSplit
143 *     - \ref Cy_GPIO_GetAmuxSplit
144 *     </td>
145 *     <td>Added a new functionality related to AMux bus.</td>
146 *   </tr>
147 *   <tr>
148 *     <td>Added register access layer. Use register access macros instead
149 *         of direct register access using dereferenced pointers.</td>
150 *     <td>Makes register access device-independent, so that the PDL does
151 *         not need to be recompiled for each supported part number.</td>
152 *   </tr>
153 *   <tr>
154 *     <td>1.10.1</td>
155 *     <td>Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus,
156 *         \ref Cy_GPIO_GetInterruptMask, \ref Cy_GPIO_GetInterruptStatusMasked.
157 *
158 *         Minor documentation edits.
159 *     </td>
160 *     <td>Documentation update and clarification</td>
161 *   </tr>
162 *   <tr>
163 *     <td>1.10</td>
164 *     <td>Added input parameter validation to the API functions</td>
165 *     <td></td>
166 *   </tr>
167 *   <tr>
168 *     <td>1.0</td>
169 *     <td>Initial version</td>
170 *     <td></td>
171 *   </tr>
172 * </table>
173 *
174 * \defgroup group_gpio_macros Macros
175 * \defgroup group_gpio_functions Functions
176 * \{
177 *   \defgroup group_gpio_functions_init       Initialization Functions
178 *   \defgroup group_gpio_functions_gpio       GPIO Functions
179 *   \defgroup group_gpio_functions_sio        SIO Functions
180 *   \defgroup group_gpio_functions_interrupt  Port Interrupt Functions
181 * \}
182 * \defgroup group_gpio_data_structures Data Structures
183 * \defgroup group_gpio_enums Enumerated Types
184 */
185 
186 #if !defined(CY_GPIO_H)
187 #define CY_GPIO_H
188 
189 #include "cy_device.h"
190 
191 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS40IOSS)
192 
193 #include <stddef.h>
194 #include "cy_syslib.h"
195 
196 #if defined(__cplusplus)
197 extern "C" {
198 #endif
199 
200 /** \addtogroup group_gpio_macros
201 * \{
202 */
203 
204 /** Driver major version */
205 #define CY_GPIO_DRV_VERSION_MAJOR       1
206 
207 /** Driver minor version */
208 #define CY_GPIO_DRV_VERSION_MINOR       50
209 
210 /** GPIO driver ID */
211 #define CY_GPIO_ID CY_PDL_DRV_ID(0x16U)
212 
213 /** \} group_gpio_macros */
214 
215 
216 /***************************************
217 *       Enumerations
218 ***************************************/
219 /**
220 * \addtogroup group_gpio_enums
221 * \{
222 */
223 
224 /** GPIO Driver error codes */
225 typedef enum
226 {
227     CY_GPIO_SUCCESS   = 0x00U,                                    /**< Returned successful */
228     CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */
229 } cy_en_gpio_status_t;
230 
231 /** AMux switch open/close config */
232 typedef enum
233 {
234     CY_GPIO_AMUX_OPENALL,   /**< Open ground switch. Open right switch. Open left switch */
235     CY_GPIO_AMUX_L,         /**< Open ground switch. Open right switch. Close left switch */
236     CY_GPIO_AMUX_R,         /**< Open ground switch. Close right switch. Open left switch */
237     CY_GPIO_AMUX_LR,        /**< Open ground switch. Close right switch. Close left switch */
238     CY_GPIO_AMUX_G,         /**< Close ground switch. Open right switch. Open left switch */
239     CY_GPIO_AMUX_GL,        /**< Close ground switch. Open right switch. Close left switch */
240     CY_GPIO_AMUX_GR,        /**< Close ground switch. Close right switch. Open left switch */
241     CY_GPIO_AMUX_GLR,       /**< Close ground switch. Close right switch. Close left switch */
242 }cy_en_gpio_amuxconnect_t;
243 
244 /**
245 * AMux Bus selection
246 */
247 typedef enum
248 {
249     CY_GPIO_AMUXBUSA,       /**< AMuxBus A */
250     CY_GPIO_AMUXBUSB        /**< AMuxBus B */
251 }cy_en_gpio_amuxselect_t;
252 
253 /** \} group_gpio_enums */
254 
255 
256 /***************************************
257 *       Configuration Structures
258 ***************************************/
259 
260 /**
261 * \addtogroup group_gpio_data_structures
262 * \{
263 */
264 
265 /** This structure is used to initialize a port of GPIO pins */
266 typedef struct
267 {
268     uint32_t out;           /**< Initial output data for the IO pins in the port */
269     uint32_t intrMask;      /**< Interrupt enable mask for the port interrupt */
270     uint32_t intrCfg;       /**< Port pin interrupt edge detection configuration */
271     uint32_t cfg;           /**< Port pin drive modes and input buffer enable configuration */
272     uint32_t cfgIn;         /**< Port pin input buffer configuration */
273     uint32_t cfgOut;        /**< Port pin output buffer configuration */
274     uint32_t cfgSIO;        /**< Port SIO pins configuration */
275     uint32_t sel0Active;    /**< HSIOM selection for port pins 0,1,2,3 */
276     uint32_t sel1Active;    /**< HSIOM selection for port pins 4,5,6,7 */
277 #if defined (CY_IP_MXS40SIOSS)
278     /**
279     * \note
280     * This parameter is available for the CAT1B devices.
281     **/
282     uint32_t cfgSlew;       /**< Port slew rate configuration */
283     /**
284     * \note
285     * This parameter is available for the CAT1B devices.
286     **/
287     uint32_t cfgDriveSel0;  /**< Drive strength configuration for pins 0,1,2,3 */
288     /**
289     * \note
290     * This parameter is available for the CAT1B devices.
291     **/
292     uint32_t cfgDriveSel1;  /**< Drive strength configuration for pins 4,5,6,7 */
293     /**
294     * \note
295     * This parameter is available for the CAT1B devices.
296     **/
297     uint32_t nonSecMask;    /**< HSIOM non secure mask for port pins 0-7 */
298 #endif /* CY_IP_MXS40SIOSS */
299 } cy_stc_gpio_prt_config_t;
300 
301 /** This structure is used to initialize a single GPIO pin */
302 typedef struct
303 {
304     uint32_t outVal;         /**< Pin output state */
305     uint32_t driveMode;      /**< Drive mode */
306     en_hsiom_sel_t hsiom;    /**< HSIOM selection */
307     uint32_t intEdge;        /**< Interrupt Edge type */
308     uint32_t intMask;        /**< Interrupt enable mask */
309     uint32_t vtrip;          /**< Input buffer voltage trip type */
310     uint32_t slewRate;       /**< Output buffer slew rate */
311     uint32_t driveSel;       /**< Drive strength */
312     uint32_t vregEn;         /**< SIO pair output buffer mode */
313     uint32_t ibufMode;       /**< SIO pair input buffer mode */
314     uint32_t vtripSel;       /**< SIO pair input buffer trip point */
315     uint32_t vrefSel;        /**< SIO pair reference voltage for input buffer trip point */
316     uint32_t vohSel;         /**< SIO pair regulated voltage output level */
317 #if defined (CY_IP_MXS40SIOSS)
318     /**
319     * \note
320     * This parameter is available for the CAT1B devices.
321     **/
322     uint32_t nonSec;         /**< Secure attribute for each Pin of a port */
323 #endif /* CY_IP_MXS40SIOSS */
324 } cy_stc_gpio_pin_config_t;
325 
326 /** \} group_gpio_data_structures */
327 
328 /***************************************
329 *        Constants
330 ***************************************/
331 
332 /** \cond INTERNAL */
333 
334 /* General Constants */
335 #define CY_GPIO_PRT_HALF                       (4UL)      /**< Half-way point of a GPIO port */
336 #define CY_GPIO_PRT_DEINIT                     (0UL)      /**< De-init value for port registers */
337 #if defined (CY_IP_MXS40SIOSS)
338 #define CY_HSIOM_NONSEC_DEINIT                 (0xFFUL)   /**< De-init value for port non sec register */
339 #endif /* CY_IP_MXS40SIOSS */
340 
341 /* GPIO Masks */
342 #define CY_GPIO_HSIOM_MASK                     (0x1FUL)   /**< HSIOM selection mask */
343 #define CY_GPIO_OUT_MASK                       (0x01UL)   /**< Single pin mask for OUT register */
344 #define CY_GPIO_IN_MASK                        (0x01UL)   /**< Single pin mask for IN register */
345 #define CY_GPIO_CFG_DM_MASK                    (0x0FUL)   /**< Single pin mask for drive mode in CFG register */
346 #define CY_GPIO_CFG_IN_VTRIP_SEL_MASK          (0x01UL)   /**< Single pin mask for VTRIP selection in CFG IN register */
347 #define CY_GPIO_INTR_STATUS_MASK               (0x01UL)   /**< Single pin mask for interrupt status in INTR register */
348 #define CY_GPIO_INTR_EN_MASK                   (0x01UL)   /**< Single pin mask for interrupt status in INTR register */
349 #define CY_GPIO_INTR_MASKED_MASK               (0x01UL)   /**< Single pin mask for masked interrupt status in INTR_MASKED register */
350 #define CY_GPIO_INTR_SET_MASK                  (0x01UL)   /**< Single pin mask for setting the interrupt in INTR_MASK register */
351 #define CY_GPIO_INTR_EDGE_MASK                 (0x03UL)   /**< Single pin mask for interrupt edge type in INTR_EDGE register */
352 #define CY_GPIO_INTR_FLT_EDGE_MASK             (0x07UL)   /**< Single pin mask for setting filtered interrupt */
353 #if defined (CY_IP_MXS40IOSS)
354 #define CY_GPIO_CFG_OUT_SLOW_MASK              (0x01UL)   /**< Single pin mask for slew rate in CFG OUT register */
355 #define CY_GPIO_CFG_OUT_DRIVE_SEL_MASK         (0x03UL)   /**< Single pin mask for drive strength in CFG OUT register */
356 #else
357 #define CY_GPIO_HSIOM_SEC_MASK                 (0x01UL)   /**< Single pin mask for NONSECURE_MASK register */
358 #define CY_GPIO_CFG_SLEW_EXT_MASK              (0x07UL)   /**< Single pin mask for slew rate in CFG SLEW EXT register */
359 #define CY_GPIO_CFG_DRIVE_SEL_EXT_MASK         (0x1FUL)   /**< Single pin mask for drive strength in CFG DRIVE EXT register */
360 #endif /* CY_IP_MXS40IOSS */
361 
362 /* SIO Masks */
363 #define CY_GPIO_VREG_EN_MASK                   (0x01UL)   /**< Single SIO pin mask for voltage regulation enable */
364 #define CY_GPIO_IBUF_MASK                      (0x01UL)   /**< Single SIO pin mask for input buffer */
365 #define CY_GPIO_IBUF_SHIFT                     (0x01UL)   /**< Single SIO pin shift for input buffer */
366 #define CY_GPIO_VTRIP_SEL_MASK                 (0x01UL)   /**< Single SIO pin mask for the input buffer trip point */
367 #define CY_GPIO_VTRIP_SEL_SHIFT                (0x02UL)   /**< Single SIO pin shift for the input buffer trip point */
368 #define CY_GPIO_VREF_SEL_MASK                  (0x03UL)   /**< Single SIO pin mask for voltage reference */
369 #define CY_GPIO_VREF_SEL_SHIFT                 (0x03UL)   /**< Single SIO pin shift for voltage reference */
370 #define CY_GPIO_VOH_SEL_MASK                   (0x07UL)   /**< Single SIO pin mask for VOH */
371 #define CY_GPIO_VOH_SEL_SHIFT                  (0x05UL)   /**< Single SIO pin shift for VOH */
372 
373 /* Special mask for SIO pin pair setting */
374 #define CY_GPIO_SIO_ODD_PIN_MASK               (0x00FEUL) /**< SIO pin pair selection mask */
375 #define CY_GPIO_SIO_PIN_MASK                   (0x00FFUL) /**< SIO pin pair mask */
376 
377 /* Offsets */
378 #define CY_GPIO_HSIOM_OFFSET                   (3UL)      /**< Offset for HSIOM */
379 #define CY_GPIO_DRIVE_MODE_OFFSET              (2UL)      /**< Offset for Drive mode */
380 #define CY_GPIO_INBUF_OFFSET                   (3UL)      /**< Offset for input buffer */
381 #define CY_GPIO_CFG_OUT_DRIVE_OFFSET           (16UL)     /**< Offset for drive strength */
382 #define CY_GPIO_INTR_CFG_OFFSET                (1UL)      /**< Offset for interrupt config */
383 #define CY_GPIO_INTR_FILT_OFFSET               (18UL)     /**< Offset for filtered interrupt config */
384 #define CY_GPIO_CFG_SIO_OFFSET                 (2UL)      /**< Offset for SIO config */
385 #if defined (CY_IP_MXS40SIOSS)
386 #define CY_GPIO_CFG_SLEW_EXT_OFFSET            (2UL)      /**< Offset for CFG SLEW EXT */
387 #define CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET       (3UL)      /**< Offset for CFG SLEW EXT */
388 #endif /* CY_IP_MXS40SIOSS */
389 
390 /* Parameter validation constants */
391 #define CY_GPIO_PINS_MAX                       (8UL)      /**< Number of pins in the port */
392 #define CY_GPIO_PRT_PINS_MASK                  (0x0000000FFUL)
393 #define CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK     (GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk | \
394                                                 GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk | \
395                                                 GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk | \
396                                                 GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk | \
397                                                 GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk | \
398                                                 GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk | \
399                                                 GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk | \
400                                                 GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk)
401 #define CY_GPIO_PRT_INTR_CFG_RANGE_MASK        (CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK | \
402                                                 GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk | \
403                                                 GPIO_PRT_INTR_CFG_FLT_SEL_Msk)
404 #define CY_GPIO_PRT_INT_MASK_MASK              (0x0000001FFUL)
405 #define CY_GPIO_PRT_SEL_ACTIVE_MASK            (0x1FFFFFFFUL)
406 
407 #define GPIO_MAX_SPLIT_CELL_SEGMENTS           (9U)
408 
409 /* Parameter validation macros */
410 #define CY_GPIO_IS_PIN_VALID(pinNum)           (CY_GPIO_PINS_MAX > (pinNum))
411 #define CY_GPIO_IS_FILTER_PIN_VALID(pinNum)    (CY_GPIO_PINS_MAX >= (pinNum))
412 #define CY_GPIO_IS_VALUE_VALID(outVal)         (1UL >= (outVal))
413 #define CY_GPIO_IS_DM_VALID(driveMode)         ((0U == ((driveMode) & (uint32_t)~CY_GPIO_CFG_DM_MASK)) && \
414                                                ((driveMode) != CY_GPIO_DM_INVALID_IN_OFF) && \
415                                                ((driveMode) != CY_GPIO_DM_INVALID))
416 
417 #define CY_GPIO_IS_HSIOM_VALID(hsiom)          (0U == ((hsiom) & (uint32_t)~CY_GPIO_HSIOM_MASK))
418 
419 #define CY_GPIO_IS_INT_EDGE_VALID(intEdge)     ((CY_GPIO_INTR_DISABLE  == (intEdge)) || \
420                                                 (CY_GPIO_INTR_RISING   == (intEdge)) || \
421                                                 (CY_GPIO_INTR_FALLING  == (intEdge)) || \
422                                                 (CY_GPIO_INTR_BOTH     == (intEdge)))
423 
424 #define CY_GPIO_IS_VREF_SEL_VALID(vrefSel)     ((CY_SIO_VREF_PINREF    == (vrefSel)) || \
425                                                 (CY_SIO_VREF_1_2V      == (vrefSel)) || \
426                                                 (CY_SIO_VREF_AMUX_A    == (vrefSel)) || \
427                                                 (CY_SIO_VREF_AMUX_B    == (vrefSel)))
428 
429 #define CY_GPIO_IS_VOH_SEL_VALID(vrefSel)      ((CY_SIO_VOH_1_00       == (vrefSel)) || \
430                                                 (CY_SIO_VOH_1_25       == (vrefSel)) || \
431                                                 (CY_SIO_VOH_1_49       == (vrefSel)) || \
432                                                 (CY_SIO_VOH_1_67       == (vrefSel)) || \
433                                                 (CY_SIO_VOH_2_08       == (vrefSel)) || \
434                                                 (CY_SIO_VOH_2_50       == (vrefSel)) || \
435                                                 (CY_SIO_VOH_2_78       == (vrefSel)) || \
436                                                 (CY_SIO_VOH_4_16       == (vrefSel)))
437 
438 #define CY_GPIO_IS_PIN_BIT_VALID(pinBit)       (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK))
439 #define CY_GPIO_IS_INTR_CFG_VALID(intrCfg)     (0U == ((intrCfg) & (uint32_t)~CY_GPIO_PRT_INTR_CFG_RANGE_MASK))
440 #define CY_GPIO_IS_INTR_MASK_VALID(intrMask)   (0U == ((intrMask) & (uint32_t)~CY_GPIO_PRT_INT_MASK_MASK))
441 #define CY_GPIO_IS_SEL_ACT_VALID(selActive)    (0U == ((selActive) & (uint32_t)~CY_GPIO_PRT_SEL_ACTIVE_MASK))
442 
443 #define CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl)       (((uint32_t) (switchCtrl)) < GPIO_MAX_SPLIT_CELL_SEGMENTS)
444 
445 #define CY_GPIO_IS_AMUX_CONNECT_VALID(amuxConnect)    ((CY_GPIO_AMUX_OPENALL == (amuxConnect)) || \
446                                                        (CY_GPIO_AMUX_L       == (amuxConnect)) || \
447                                                        (CY_GPIO_AMUX_R       == (amuxConnect)) || \
448                                                        (CY_GPIO_AMUX_LR      == (amuxConnect)) || \
449                                                        (CY_GPIO_AMUX_G       == (amuxConnect)) || \
450                                                        (CY_GPIO_AMUX_GL      == (amuxConnect)) || \
451                                                        (CY_GPIO_AMUX_GR      == (amuxConnect)) || \
452                                                        (CY_GPIO_AMUX_GLR     == (amuxConnect)))
453 
454 #define CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus)       ((CY_GPIO_AMUXBUSA       == (amuxBus)) || \
455                                                      (CY_GPIO_AMUXBUSB       == (amuxBus)))
456 
457 #if defined (CY_IP_MXS40IOSS)
458 #define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel)   ((CY_GPIO_DRIVE_FULL    == (driveSel)) || \
459                                                 (CY_GPIO_DRIVE_1_2     == (driveSel)) || \
460                                                 (CY_GPIO_DRIVE_1_4     == (driveSel)) || \
461                                                 (CY_GPIO_DRIVE_1_8     == (driveSel)))
462 #else
463 #define CY_GPIO_IS_HSIOM_SEC_VALID(secValue)   (0U == ((secValue) & (uint32_t)~CY_GPIO_HSIOM_SEC_MASK))
464 #define CY_GPIO_IS_SLEW_RATE_VALID(slewRate)   (0U == ((slewRate) & (uint32_t)~CY_GPIO_CFG_SLEW_EXT_MASK))
465 #define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel)   (0U == ((driveSel) & (uint32_t)~CY_GPIO_CFG_DRIVE_SEL_EXT_MASK))
466 #endif /* CY_IP_MXS40IOSS */
467 
468 /** \endcond */
469 
470 
471 /***************************************
472 *        Function Constants
473 ***************************************/
474 
475 /**
476 * \addtogroup group_gpio_macros
477 * \{
478 */
479 
480 /**
481 * \defgroup group_gpio_driveModes Pin drive mode
482 * \{
483 * Constants to be used for setting the drive mode of the pin. There are eight
484 * primary drive modes.
485 * Below diagrams are simplified output driver diagrams of the pin view for the
486 * CPU register and UDB/DSI based digital peripherals on each of the eight drive
487 * modes.
488 * \image html gpio_cpu_dm_block_diagram.png
489 *
490 * Below is a simplified output driver diagram that shows the pin view for
491 * fixed-function-based peripherals for each of the eight drive modes.
492 * \image html gpio_periio_dm_block_diagram.png
493 *
494 * - High-Impedance:
495 *   This is the standard high-impedance (HI-Z) state recommended for analog and
496 *   digital inputs. For digital signals, the input buffer is enabled; for analog
497 *   signals, the input buffer is typically disabled to reduce crowbar current
498 *   and leakage in low-power designs. To achieve the lowest device current, unused
499 *   GPIOs must be configured to the high-impedance drive mode with input buffer
500 *   disabled. Highimpedance drive mode with input buffer disabled is also the
501 *   default pin reset state.
502 *
503 * - Resistive Pull-Up or Resistive Pull-Down:
504 *   Resistive modes provide a series resistance in one of the data states and
505 *   strong drive in the other. Pins can be used for either digital input or
506 *   digital output in these modes. If resistive pull-up is required, a '1' must be
507 *   written to that pin's Data Register bit. If resistive pull-down is required,
508 *   a '0' must be written to that pin's Data Register. Interfacing mechanical
509 *   switches is a common application of these drive modes. The resistive modes are
510 *   also used to interface PSoC with open drain drive lines. Resistive pull-up is
511 *   used when the input is open drain low and resistive pull-down is used when the
512 *   input is open drain high.
513 *
514 * - Open Drain Drives High and Open Drain Drives Low:
515 *   Open drain modes provide high impedance in one of the data states and strong
516 *   drive in the other. Pins are useful as digital inputs or outputs in these
517 *   modes. Therefore, these modes are widely used in bidirectional digital
518 *   communication. Open drain drive high mode is used when the signal is
519 *   externally pulled down and open drain drive low is used when the signal is
520 *   externally pulled high. A common application for the open drain drives low
521 *   mode is driving I2C bus signal lines.
522 *
523 * - Strong Drive:
524 *   The strong drive mode is the standard digital output mode for pins; it
525 *   provides a strong CMOS output drive in both high and low states. Strong drive
526 *   mode pins should not be used as inputs under normal circumstances. This mode
527 *   is often used for digital output signals or to drive external devices.
528 *
529 * - Resistive Pull-Up and Resistive Pull-Down:
530 *   In the resistive pull-up and pull-down mode, the GPIO will have a series
531 *   resistance in both logic 1 and logic 0 output states. The high data state is
532 *   pulled up while the low data state is pulled down. This mode is useful when
533 *   the pin is driven by other signals that may cause shorts.
534 */
535 #define CY_GPIO_DM_ANALOG                      (0x00UL) /**< Analog High-Z. Input buffer off */
536 #define CY_GPIO_DM_INVALID_IN_OFF              (0x01UL) /**< Invalid mode. It should not be used */
537 #define CY_GPIO_DM_PULLUP_IN_OFF               (0x02UL) /**< Resistive Pull-Up. Input buffer off */
538 #define CY_GPIO_DM_PULLDOWN_IN_OFF             (0x03UL) /**< Resistive Pull-Down. Input buffer off */
539 #define CY_GPIO_DM_OD_DRIVESLOW_IN_OFF         (0x04UL) /**< Open Drain, Drives Low. Input buffer off */
540 #define CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF        (0x05UL) /**< Open Drain, Drives High. Input buffer off */
541 #define CY_GPIO_DM_STRONG_IN_OFF               (0x06UL) /**< Strong Drive. Input buffer off */
542 #define CY_GPIO_DM_PULLUP_DOWN_IN_OFF          (0x07UL) /**< Resistive Pull-Up/Down. Input buffer off */
543 #define CY_GPIO_DM_HIGHZ                       (0x08UL) /**< Digital High-Z. Input buffer on */
544 #define CY_GPIO_DM_INVALID                     (0x09UL) /**< Invalid mode. It should not be used */
545 #define CY_GPIO_DM_PULLUP                      (0x0AUL) /**< Resistive Pull-Up. Input buffer on */
546 #define CY_GPIO_DM_PULLDOWN                    (0x0BUL) /**< Resistive Pull-Down. Input buffer on */
547 #define CY_GPIO_DM_OD_DRIVESLOW                (0x0CUL) /**< Open Drain, Drives Low. Input buffer on */
548 #define CY_GPIO_DM_OD_DRIVESHIGH               (0x0DUL) /**< Open Drain, Drives High. Input buffer on */
549 #define CY_GPIO_DM_STRONG                      (0x0EUL) /**< Strong Drive. Input buffer on */
550 #define CY_GPIO_DM_PULLUP_DOWN                 (0x0FUL) /**< Resistive Pull-Up/Down. Input buffer on */
551 /** \} */
552 
553 /**
554 * \defgroup group_gpio_vtrip Voltage trip mode
555 * \{
556 * Constants to be used for setting the voltage trip type on the pin.
557 */
558 #define CY_GPIO_VTRIP_CMOS                     (0x00UL) /**< Input buffer compatible with CMOS and I2C interfaces */
559 #define CY_GPIO_VTRIP_TTL                      (0x01UL) /**< Input buffer compatible with TTL and MediaLB interfaces */
560 /** \} */
561 
562 /**
563 * \defgroup group_gpio_slewRate Slew Rate Mode
564 * \{
565 * Constants to be used for setting the slew rate of the pin.
566 */
567 #define CY_GPIO_SLEW_FAST                      (0x00UL) /**< Fast slew rate */
568 #define CY_GPIO_SLEW_SLOW                      (0x01UL) /**< Slow slew rate */
569 /** \} */
570 
571 /**
572 * \defgroup group_gpio_driveStrength Pin drive strength
573 * \{
574 * Constants to be used for setting the drive strength of the pin.
575 */
576 #define CY_GPIO_DRIVE_FULL                     (0x00UL) /**< Full drive strength: Max drive current */
577 #define CY_GPIO_DRIVE_1_2                      (0x01UL) /**< 1/2 drive strength: 1/2 drive current */
578 #define CY_GPIO_DRIVE_1_4                      (0x02UL) /**< 1/4 drive strength: 1/4 drive current */
579 #define CY_GPIO_DRIVE_1_8                      (0x03UL) /**< 1/8 drive strength: 1/8 drive current */
580 /** \} */
581 
582 /**
583 * \defgroup group_gpio_interruptTrigger Interrupt trigger type
584 * \{
585 * Constants to be used for setting the interrupt trigger type on the pin.
586 */
587 #define CY_GPIO_INTR_DISABLE                   (0x00UL) /**< Disable the pin interrupt generation */
588 #define CY_GPIO_INTR_RISING                    (0x01UL) /**< Rising-Edge interrupt */
589 #define CY_GPIO_INTR_FALLING                   (0x02UL) /**< Falling-Edge interrupt */
590 #define CY_GPIO_INTR_BOTH                      (0x03UL) /**< Both-Edge interrupt */
591 /** \} */
592 
593 /**
594 * \defgroup group_gpio_sioVreg SIO output buffer mode
595 * \{
596 * Constants to be used for setting the SIO output buffer mode on the pin.
597 */
598 #define CY_SIO_VREG_UNREGULATED                (0x00UL) /**< Unregulated output buffer */
599 #define CY_SIO_VREG_REGULATED                  (0x01UL) /**< Regulated output buffer */
600 /** \} */
601 
602 /**
603 * \defgroup group_gpio_sioIbuf SIO input buffer mode
604 * \{
605 * Constants to be used for setting the SIO input buffer mode on the pin.
606 */
607 #define CY_SIO_IBUF_SINGLEENDED                (0x00UL) /**< Single ended input buffer */
608 #define CY_SIO_IBUF_DIFFERENTIAL               (0x01UL) /**< Differential input buffer */
609 /** \} */
610 
611 /**
612 * \defgroup group_gpio_sioVtrip SIO input buffer trip-point
613 * \{
614 * Constants to be used for setting the SIO input buffer trip-point of the pin.
615 */
616 #define CY_SIO_VTRIP_CMOS                      (0x00UL) /**< CMOS input buffer (single-ended) */
617 #define CY_SIO_VTRIP_TTL                       (0x01UL) /**< TTL input buffer (single-ended) */
618 #define CY_SIO_VTRIP_0_5VDDIO_0_5VOH           (0x00UL) /**< 0.5xVddio or 0.5xVoh (differential) */
619 #define CY_SIO_VTRIP_0_4VDDIO_1_0VREF          (0x01UL) /**< 0.4xVddio or 0.4xVoh (differential) */
620 /** \} */
621 
622 /**
623 * \defgroup group_gpio_sioVref SIO reference voltage for input buffer trip-point
624 * \{
625 * Constants to be used for setting the reference voltage of SIO input buffer trip-point.
626 */
627 #define CY_SIO_VREF_PINREF                     (0x00UL) /**< Vref from analog pin */
628 #define CY_SIO_VREF_1_2V                       (0x01UL) /**< Vref from internal 1.2V reference */
629 #define CY_SIO_VREF_AMUX_A                     (0x02UL) /**< Vref from AMUXBUS_A */
630 #define CY_SIO_VREF_AMUX_B                     (0x03UL) /**< Vref from AMUXBUS_B */
631 /** \} */
632 
633 /**
634 * \defgroup group_gpio_sioVoh Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair
635 * \{
636 * Constants to be used for setting the Voh and input buffer trip-point of an SIO pair
637 */
638 #define CY_SIO_VOH_1_00                        (0x00UL) /**< Voh = 1 x Reference */
639 #define CY_SIO_VOH_1_25                        (0x01UL) /**< Voh = 1.25 x Reference */
640 #define CY_SIO_VOH_1_49                        (0x02UL) /**< Voh = 1.49 x Reference */
641 #define CY_SIO_VOH_1_67                        (0x03UL) /**< Voh = 1.67 x Reference */
642 #define CY_SIO_VOH_2_08                        (0x04UL) /**< Voh = 2.08 x Reference */
643 #define CY_SIO_VOH_2_50                        (0x05UL) /**< Voh = 2.50 x Reference */
644 #define CY_SIO_VOH_2_78                        (0x06UL) /**< Voh = 2.78 x Reference */
645 #define CY_SIO_VOH_4_16                        (0x07UL) /**< Voh = 4.16 x Reference */
646 /** \} */
647 
648 /** \} group_gpio_macros */
649 
650 /***************************************
651 *        Function Prototypes
652 ***************************************/
653 
654 /**
655 * \addtogroup group_gpio_functions
656 * \{
657 */
658 
659 /**
660 * \addtogroup group_gpio_functions_init
661 * \{
662 */
663 
664 cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type* base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config);
665 cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config);
666 void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom);
667 void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base);
668 void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value);
669 en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum);
670 __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum);
671 #if defined (CY_IP_MXS40SIOSS)
672 void Cy_GPIO_Pin_SecFastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom);
673 __STATIC_INLINE void Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
674 __STATIC_INLINE uint32_t Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum);
675 #endif /* CY_IP_MXS40SIOSS */
676 
677 /** \} group_gpio_functions_init */
678 
679 /**
680 * \addtogroup group_gpio_functions_gpio
681 * \{
682 */
683 
684 void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, cy_en_gpio_amuxselect_t amuxBus);
685 cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus);
686 
687 uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum);
688 void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
689 uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum);
690 void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum);
691 void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum);
692 void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum);
693 void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
694 uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum);
695 void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
696 uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum);
697 void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
698 uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum);
699 void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
700 uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum);
701 
702 /** \} group_gpio_functions_gpio */
703 
704 /**
705 * \addtogroup group_gpio_functions_sio
706 * \{
707 */
708 
709 void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
710 uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum);
711 void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
712 uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum);
713 void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
714 uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum);
715 void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
716 uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum);
717 void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
718 uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum);
719 
720 /** \} group_gpio_functions_sio */
721 
722 /**
723 * \addtogroup group_gpio_functions_interrupt
724 * \{
725 */
726 
727 uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum);
728 void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
729 void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
730 uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum);
731 uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum);
732 void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
733 void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
734 uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum);
735 void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value);
736 uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base);
737 
738 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void);
739 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void);
740 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void);
741 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void);
742 #if defined (CY_IP_MXS40SIOSS)
743 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause0(void);
744 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause1(void);
745 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause2(void);
746 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause3(void);
747 #endif /* CY_IP_MXS40SIOSS */
748 
749 /** \} group_gpio_functions_interrupt */
750 
751 /** \cond INTERNAL */
752 #if defined (CY_IP_MXS40SIOSS)
753 #define HSIOM_PRT_V1_Type HSIOM_PRT_Type
754 #endif /* CY_IP_MXS40SIOSS */
755 /** \endcond */
756 
757 /**
758 * \addtogroup group_gpio_functions_init
759 * \{
760 */
761 
762 #if defined (CY_IP_MXS40SIOSS)
763 /*******************************************************************************
764 * Function Name: Cy_GPIO_SetHSIOM_SecPin
765 ****************************************************************************//**
766 *
767 * Configures the pin as secure or non-secure.
768 *
769 *
770 * \param base
771 * Pointer to the pin's port register base address
772 *
773 * \param pinNum
774 * Position of the pin bit-field within the port register
775 *
776 * \param value
777 * Secure HSIOM non-secure mask
778 *
779 * \note
780 * This function modifies a port register in a read-modify-write operation. It is
781 * not thread safe as the resource is shared among multiple pins on a port.
782 * This function should be called from the right protection context to access
783 * HSIOM secure port (HSIOM_SECURE_PRT_Type).
784 *
785 * \note
786 * This API is available for the CAT1B devices.
787 *
788 * \funcusage
789 *
790 *******************************************************************************/
Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)791 __STATIC_INLINE void Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
792 {
793     uint32_t tempReg;
794     uint32_t portNum;
795     HSIOM_SECURE_PRT_Type* portAddrSecHSIOM;
796 
797     CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
798     CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value));
799 
800     portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
801     portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
802 
803     tempReg= HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) & ~(CY_GPIO_HSIOM_SEC_MASK << pinNum);
804     HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) = tempReg | ((value & CY_GPIO_HSIOM_SEC_MASK) << pinNum);
805 }
806 
807 /*******************************************************************************
808 * Function Name: Cy_GPIO_GetHSIOM_SecPin
809 ****************************************************************************//**
810 *
811 * Returns the current status of secure Pin.
812 *
813 * \param base
814 * Pointer to the pin's port register base address
815 *
816 * \param pinNum
817 * Position of the pin bit-field within the port register
818 *
819 * \return
820 * HSIOM input selection
821 *
822 * \note
823 * This API is available for the CAT1B devices.
824 *
825 * \funcusage
826 *
827 *******************************************************************************/
Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type * base,uint32_t pinNum)828 __STATIC_INLINE uint32_t Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum)
829 {
830     uint32_t portNum;
831     HSIOM_SECURE_PRT_Type* portAddrSecHSIOM;
832 
833     CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
834 
835     portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
836     portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
837 
838     return (uint32_t)((HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) >> pinNum) & CY_GPIO_HSIOM_SEC_MASK);
839 }
840 
841 #endif /* CY_IP_MXS40SIOSS */
842 
843 /*******************************************************************************
844 * Function Name: Cy_GPIO_PortToAddr
845 ****************************************************************************//**
846 *
847 * Retrieves the port address based on the given port number.
848 *
849 * This is a helper function to calculate the port base address when given a port
850 * number. It is to be used when pin access needs to be calculated at runtime.
851 *
852 * \param portNum
853 * Port number
854 *
855 * \return
856 * Base address of the port register structure
857 *
858 * \funcusage
859 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_PortToAddr
860 *
861 *******************************************************************************/
Cy_GPIO_PortToAddr(uint32_t portNum)862 __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum)
863 {
864     GPIO_PRT_Type* portBase;
865 
866     if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR)
867     {
868         portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum));
869     }
870     else
871     {
872         /* Error: Return default base address */
873         portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE);
874     }
875 
876     return (portBase);
877 }
878 
879 /** \} group_gpio_functions_init */
880 
881 
882 
883 /**
884 * \addtogroup group_gpio_functions_interrupt
885 * \{
886 */
887 
888 /*******************************************************************************
889 * Function Name: Cy_GPIO_GetInterruptCause0
890 ****************************************************************************//**
891 *
892 * Returns the interrupt status for ports 0 to 31.
893 *
894 * \return
895 * 0 = Interrupt not detected on port
896 * 1 = Interrupt detected on port
897 *
898 * \funcusage
899 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptCause0
900 *
901 *******************************************************************************/
Cy_GPIO_GetInterruptCause0(void)902 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void)
903 {
904     return (GPIO_INTR_CAUSE0);
905 }
906 
907 
908 /*******************************************************************************
909 * Function Name: Cy_GPIO_GetInterruptCause1
910 ****************************************************************************//**
911 *
912 * Returns the interrupt status for ports 32 to 63.
913 *
914 * \return
915 * 0 = Interrupt not detected on port
916 * 1 = Interrupt detected on port
917 *
918 * \funcusage
919 * Refer to the Cy_GPIO_GetInterruptCause0() example.
920 *
921 *******************************************************************************/
Cy_GPIO_GetInterruptCause1(void)922 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void)
923 {
924     return (GPIO_INTR_CAUSE1);
925 }
926 
927 
928 /*******************************************************************************
929 * Function Name: Cy_GPIO_GetInterruptCause2
930 ****************************************************************************//**
931 *
932 * Returns the interrupt status for ports 64 to 95.
933 *
934 * \return
935 * 0 = Interrupt not detected on port
936 * 1 = Interrupt detected on port
937 * \funcusage
938 * Refer to the Cy_GPIO_GetInterruptCause0() example.
939 *
940 *******************************************************************************/
Cy_GPIO_GetInterruptCause2(void)941 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void)
942 {
943     return (GPIO_INTR_CAUSE2);
944 }
945 
946 
947 /*******************************************************************************
948 * Function Name: Cy_GPIO_GetInterruptCause3
949 ****************************************************************************//**
950 *
951 * Returns the interrupt status for ports 96 to 127.
952 *
953 * \return
954 * 0 = Interrupt not detected on port
955 * 1 = Interrupt detected on port
956 *
957 * \funcusage
958 * Refer to the Cy_GPIO_GetInterruptCause0() example.
959 *
960 *******************************************************************************/
Cy_GPIO_GetInterruptCause3(void)961 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void)
962 {
963     return (GPIO_INTR_CAUSE3);
964 }
965 
966 #if defined (CY_IP_MXS40SIOSS)
967 /*******************************************************************************
968 * Function Name: Cy_GPIO_GetSecureInterruptCause0
969 ****************************************************************************//**
970 *
971 * Returns the interrupt status for ports 0 to 31.
972 *
973 * \return
974 * 0 = Interrupt not detected on port
975 * 1 = Interrupt detected on port
976 *
977 * \note
978 * This API is available for the CAT1B devices.
979 *
980 * \funcusage
981 *
982 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause0(void)983 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause0(void)
984 {
985     return (GPIO_SEC_INTR_CAUSE0);
986 }
987 
988 
989 /*******************************************************************************
990 * Function Name: Cy_GPIO_GetSecureInterruptCause1
991 ****************************************************************************//**
992 *
993 * Returns the interrupt status for ports 32 to 63.
994 *
995 * \return
996 * 0 = Interrupt not detected on port
997 * 1 = Interrupt detected on port
998 *
999 * \note
1000 * This API is available for the CAT1B devices.
1001 *
1002 * \funcusage
1003 *
1004 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause1(void)1005 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause1(void)
1006 {
1007     return (GPIO_SEC_INTR_CAUSE1);
1008 }
1009 
1010 
1011 /*******************************************************************************
1012 * Function Name: Cy_GPIO_GetSecureInterruptCause2
1013 ****************************************************************************//**
1014 *
1015 * Returns the interrupt status for ports 64 to 95.
1016 *
1017 * \return
1018 * 0 = Interrupt not detected on port
1019 * 1 = Interrupt detected on port
1020 *
1021 * \note
1022 * This API is available for the CAT1B devices.
1023 *
1024 * \funcusage
1025 *
1026 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause2(void)1027 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause2(void)
1028 {
1029     return (GPIO_SEC_INTR_CAUSE2);
1030 }
1031 
1032 
1033 /*******************************************************************************
1034 * Function Name: Cy_GPIO_GetSecureInterruptCause3
1035 ****************************************************************************//**
1036 *
1037 * Returns the interrupt status for ports 96 to 127.
1038 *
1039 * \return
1040 * 0 = Interrupt not detected on port
1041 * 1 = Interrupt detected on port
1042 *
1043 * \note
1044 * This API is available for the CAT1B devices.
1045 *
1046 * \funcusage
1047 *
1048 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause3(void)1049 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause3(void)
1050 {
1051     return (GPIO_SEC_INTR_CAUSE3);
1052 }
1053 #endif /* CY_IP_MXS40SIOSS */
1054 
1055 /** \} group_gpio_functions_interrupt */
1056 
1057 /** \} group_gpio_functions */
1058 
1059 #if defined(__cplusplus)
1060 }
1061 #endif
1062 
1063 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS40IOSS */
1064 
1065 #endif /* CY_GPIO_H */
1066 
1067 /** \} group_gpio */
1068 
1069 /* [] END OF FILE */
1070