1 /***************************************************************************//** 2 * \file gpio_psoc6_03_68_qfn.h 3 * 4 * \brief 5 * PSoC6_03 device GPIO header for 68-QFN package 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _GPIO_PSOC6_03_68_QFN_H_ 29 #define _GPIO_PSOC6_03_68_QFN_H_ 30 31 /* Package type */ 32 enum 33 { 34 CY_GPIO_PACKAGE_QFN, 35 CY_GPIO_PACKAGE_BGA, 36 CY_GPIO_PACKAGE_CSP, 37 CY_GPIO_PACKAGE_WLCSP, 38 CY_GPIO_PACKAGE_LQFP, 39 CY_GPIO_PACKAGE_TQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN 44 #define CY_GPIO_PIN_COUNT 68u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ANALOG_VDDD, 50 AMUXBUS_CSD0, 51 AMUXBUS_CSD1, 52 AMUXBUS_SAR, 53 AMUXBUS_VDDIO_1, 54 AMUXBUS_VSSA, 55 AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, 56 AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, 57 }; 58 59 /* AMUX Splitter Controls */ 60 typedef enum 61 { 62 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 63 AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 64 } cy_en_amux_split_t; 65 66 /* Port List */ 67 /* PORT 0 (AUTOLVL) */ 68 #define P0_0_PORT GPIO_PRT0 69 #define P0_0_PIN 0u 70 #define P0_0_NUM 0u 71 #define P0_1_PORT GPIO_PRT0 72 #define P0_1_PIN 1u 73 #define P0_1_NUM 1u 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_3_PORT GPIO_PRT0 78 #define P0_3_PIN 3u 79 #define P0_3_NUM 3u 80 #define P0_4_PORT GPIO_PRT0 81 #define P0_4_PIN 4u 82 #define P0_4_NUM 4u 83 #define P0_5_PORT GPIO_PRT0 84 #define P0_5_PIN 5u 85 #define P0_5_NUM 5u 86 87 /* PORT 2 (AUTOLVL) */ 88 #define P2_0_PORT GPIO_PRT2 89 #define P2_0_PIN 0u 90 #define P2_0_NUM 0u 91 #define P2_1_PORT GPIO_PRT2 92 #define P2_1_PIN 1u 93 #define P2_1_NUM 1u 94 #define P2_2_PORT GPIO_PRT2 95 #define P2_2_PIN 2u 96 #define P2_2_NUM 2u 97 #define P2_3_PORT GPIO_PRT2 98 #define P2_3_PIN 3u 99 #define P2_3_NUM 3u 100 #define P2_4_PORT GPIO_PRT2 101 #define P2_4_PIN 4u 102 #define P2_4_NUM 4u 103 #define P2_5_PORT GPIO_PRT2 104 #define P2_5_PIN 5u 105 #define P2_5_NUM 5u 106 #define P2_6_PORT GPIO_PRT2 107 #define P2_6_PIN 6u 108 #define P2_6_NUM 6u 109 #define P2_7_PORT GPIO_PRT2 110 #define P2_7_PIN 7u 111 #define P2_7_NUM 7u 112 113 /* PORT 3 (GPIO_OVT, AUTOLVL) */ 114 #define P3_0_PORT GPIO_PRT3 115 #define P3_0_PIN 0u 116 #define P3_0_NUM 0u 117 #define P3_0_AMUXSEGMENT AMUXBUS_VSSA 118 #define P3_1_PORT GPIO_PRT3 119 #define P3_1_PIN 1u 120 #define P3_1_NUM 1u 121 #define P3_1_AMUXSEGMENT AMUXBUS_VSSA 122 123 /* PORT 5 (AUTOLVL) */ 124 #define P5_0_PORT GPIO_PRT5 125 #define P5_0_PIN 0u 126 #define P5_0_NUM 0u 127 #define P5_1_PORT GPIO_PRT5 128 #define P5_1_PIN 1u 129 #define P5_1_NUM 1u 130 #define P5_6_PORT GPIO_PRT5 131 #define P5_6_PIN 6u 132 #define P5_6_NUM 6u 133 #define P5_7_PORT GPIO_PRT5 134 #define P5_7_PIN 7u 135 #define P5_7_NUM 7u 136 137 /* PORT 6 (AUTOLVL) */ 138 #define P6_2_PORT GPIO_PRT6 139 #define P6_2_PIN 2u 140 #define P6_2_NUM 2u 141 #define P6_3_PORT GPIO_PRT6 142 #define P6_3_PIN 3u 143 #define P6_3_NUM 3u 144 #define P6_4_PORT GPIO_PRT6 145 #define P6_4_PIN 4u 146 #define P6_4_NUM 4u 147 #define P6_5_PORT GPIO_PRT6 148 #define P6_5_PIN 5u 149 #define P6_5_NUM 5u 150 #define P6_6_PORT GPIO_PRT6 151 #define P6_6_PIN 6u 152 #define P6_6_NUM 6u 153 #define P6_7_PORT GPIO_PRT6 154 #define P6_7_PIN 7u 155 #define P6_7_NUM 7u 156 157 /* PORT 7 (AUTOLVL) */ 158 #define P7_0_PORT GPIO_PRT7 159 #define P7_0_PIN 0u 160 #define P7_0_NUM 0u 161 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 162 #define P7_1_PORT GPIO_PRT7 163 #define P7_1_PIN 1u 164 #define P7_1_NUM 1u 165 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 166 #define P7_2_PORT GPIO_PRT7 167 #define P7_2_PIN 2u 168 #define P7_2_NUM 2u 169 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 170 #define P7_3_PORT GPIO_PRT7 171 #define P7_3_PIN 3u 172 #define P7_3_NUM 3u 173 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 174 #define P7_7_PORT GPIO_PRT7 175 #define P7_7_PIN 7u 176 #define P7_7_NUM 7u 177 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 178 179 /* PORT 8 (AUTOLVL) */ 180 #define P8_0_PORT GPIO_PRT8 181 #define P8_0_PIN 0u 182 #define P8_0_NUM 0u 183 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 184 #define P8_1_PORT GPIO_PRT8 185 #define P8_1_PIN 1u 186 #define P8_1_NUM 1u 187 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 188 189 /* PORT 9 (AUTOLVL) */ 190 #define P9_0_PORT GPIO_PRT9 191 #define P9_0_PIN 0u 192 #define P9_0_NUM 0u 193 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 194 #define P9_1_PORT GPIO_PRT9 195 #define P9_1_PIN 1u 196 #define P9_1_NUM 1u 197 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 198 #define P9_2_PORT GPIO_PRT9 199 #define P9_2_PIN 2u 200 #define P9_2_NUM 2u 201 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 202 #define P9_3_PORT GPIO_PRT9 203 #define P9_3_PIN 3u 204 #define P9_3_NUM 3u 205 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 206 207 /* PORT 10 (AUTOLVL) */ 208 #define P10_0_PORT GPIO_PRT10 209 #define P10_0_PIN 0u 210 #define P10_0_NUM 0u 211 #define P10_1_PORT GPIO_PRT10 212 #define P10_1_PIN 1u 213 #define P10_1_NUM 1u 214 #define P10_2_PORT GPIO_PRT10 215 #define P10_2_PIN 2u 216 #define P10_2_NUM 2u 217 #define P10_3_PORT GPIO_PRT10 218 #define P10_3_PIN 3u 219 #define P10_3_NUM 3u 220 #define P10_4_PORT GPIO_PRT10 221 #define P10_4_PIN 4u 222 #define P10_4_NUM 4u 223 #define P10_5_PORT GPIO_PRT10 224 #define P10_5_PIN 5u 225 #define P10_5_NUM 5u 226 227 /* PORT 11 (AUTOLVL) */ 228 #define P11_0_PORT GPIO_PRT11 229 #define P11_0_PIN 0u 230 #define P11_0_NUM 0u 231 #define P11_1_PORT GPIO_PRT11 232 #define P11_1_PIN 1u 233 #define P11_1_NUM 1u 234 #define P11_2_PORT GPIO_PRT11 235 #define P11_2_PIN 2u 236 #define P11_2_NUM 2u 237 #define P11_3_PORT GPIO_PRT11 238 #define P11_3_PIN 3u 239 #define P11_3_NUM 3u 240 #define P11_4_PORT GPIO_PRT11 241 #define P11_4_PIN 4u 242 #define P11_4_NUM 4u 243 #define P11_5_PORT GPIO_PRT11 244 #define P11_5_PIN 5u 245 #define P11_5_NUM 5u 246 #define P11_6_PORT GPIO_PRT11 247 #define P11_6_PIN 6u 248 #define P11_6_NUM 6u 249 #define P11_7_PORT GPIO_PRT11 250 #define P11_7_PIN 7u 251 #define P11_7_NUM 7u 252 253 /* PORT 12 (AUTOLVL) */ 254 #define P12_6_PORT GPIO_PRT12 255 #define P12_6_PIN 6u 256 #define P12_6_NUM 6u 257 #define P12_7_PORT GPIO_PRT12 258 #define P12_7_PIN 7u 259 #define P12_7_NUM 7u 260 261 /* PORT 14 (AUX) */ 262 #define USBDP_PORT GPIO_PRT14 263 #define USBDP_PIN 0u 264 #define USBDP_NUM 0u 265 #define USBDM_PORT GPIO_PRT14 266 #define USBDM_PIN 1u 267 #define USBDM_NUM 1u 268 269 /* Analog Connections */ 270 #define CSD_CMODPADD_PORT 7u 271 #define CSD_CMODPADD_PIN 1u 272 #define CSD_CMODPADS_PORT 7u 273 #define CSD_CMODPADS_PIN 1u 274 #define CSD_CSH_TANKPADD_PORT 7u 275 #define CSD_CSH_TANKPADD_PIN 2u 276 #define CSD_CSH_TANKPADS_PORT 7u 277 #define CSD_CSH_TANKPADS_PIN 2u 278 #define CSD_CSHIELDPADS_PORT 7u 279 #define CSD_CSHIELDPADS_PIN 7u 280 #define CSD_VREF_EXT_PORT 7u 281 #define CSD_VREF_EXT_PIN 3u 282 #define IOSS_ADFT0_NET_PORT 10u 283 #define IOSS_ADFT0_NET_PIN 0u 284 #define IOSS_ADFT1_NET_PORT 10u 285 #define IOSS_ADFT1_NET_PIN 1u 286 #define LPCOMP_INN_COMP0_PORT 5u 287 #define LPCOMP_INN_COMP0_PIN 7u 288 #define LPCOMP_INN_COMP1_PORT 6u 289 #define LPCOMP_INN_COMP1_PIN 3u 290 #define LPCOMP_INP_COMP0_PORT 5u 291 #define LPCOMP_INP_COMP0_PIN 6u 292 #define LPCOMP_INP_COMP1_PORT 6u 293 #define LPCOMP_INP_COMP1_PIN 2u 294 #define PASS_AREF_EXT_VREF_PORT 9u 295 #define PASS_AREF_EXT_VREF_PIN 3u 296 #define PASS_SARMUX_PADS0_PORT 10u 297 #define PASS_SARMUX_PADS0_PIN 0u 298 #define PASS_SARMUX_PADS1_PORT 10u 299 #define PASS_SARMUX_PADS1_PIN 1u 300 #define PASS_SARMUX_PADS2_PORT 10u 301 #define PASS_SARMUX_PADS2_PIN 2u 302 #define PASS_SARMUX_PADS3_PORT 10u 303 #define PASS_SARMUX_PADS3_PIN 3u 304 #define PASS_SARMUX_PADS4_PORT 10u 305 #define PASS_SARMUX_PADS4_PIN 4u 306 #define PASS_SARMUX_PADS5_PORT 10u 307 #define PASS_SARMUX_PADS5_PIN 5u 308 #define SRSS_ADFT_PIN0_PORT 10u 309 #define SRSS_ADFT_PIN0_PIN 0u 310 #define SRSS_ADFT_PIN1_PORT 10u 311 #define SRSS_ADFT_PIN1_PIN 1u 312 #define SRSS_ECO_IN_PORT 12u 313 #define SRSS_ECO_IN_PIN 6u 314 #define SRSS_ECO_OUT_PORT 12u 315 #define SRSS_ECO_OUT_PIN 7u 316 #define SRSS_WCO_IN_PORT 0u 317 #define SRSS_WCO_IN_PIN 0u 318 #define SRSS_WCO_OUT_PORT 0u 319 #define SRSS_WCO_OUT_PIN 1u 320 321 /* HSIOM Connections */ 322 typedef enum 323 { 324 /* Generic HSIOM connections */ 325 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 326 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 327 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 328 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 329 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 330 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 331 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 332 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 333 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 334 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 335 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 336 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 337 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 338 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 339 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 340 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 341 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 342 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 343 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 344 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 345 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 346 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 347 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 348 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 349 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 350 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 351 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 352 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 353 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 354 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 355 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 356 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 357 358 /* P0.0 */ 359 P0_0_GPIO = 0, /* GPIO controls 'out' */ 360 P0_0_AMUXA = 4, /* Analog mux bus A */ 361 P0_0_AMUXB = 5, /* Analog mux bus B */ 362 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 363 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 364 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 365 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 366 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 367 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 368 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 369 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 370 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 371 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 372 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 373 374 /* P0.1 */ 375 P0_1_GPIO = 0, /* GPIO controls 'out' */ 376 P0_1_AMUXA = 4, /* Analog mux bus A */ 377 P0_1_AMUXB = 5, /* Analog mux bus B */ 378 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 379 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 380 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 381 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 382 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 383 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 384 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 385 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 386 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 387 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 388 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 389 390 /* P0.2 */ 391 P0_2_GPIO = 0, /* GPIO controls 'out' */ 392 P0_2_AMUXA = 4, /* Analog mux bus A */ 393 P0_2_AMUXB = 5, /* Analog mux bus B */ 394 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 395 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 396 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 397 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 398 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 399 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 400 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 401 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 402 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 403 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 404 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 405 406 /* P0.3 */ 407 P0_3_GPIO = 0, /* GPIO controls 'out' */ 408 P0_3_AMUXA = 4, /* Analog mux bus A */ 409 P0_3_AMUXB = 5, /* Analog mux bus B */ 410 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 411 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 412 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 413 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 414 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 415 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 416 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 417 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 418 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 419 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 420 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 421 422 /* P0.4 */ 423 P0_4_GPIO = 0, /* GPIO controls 'out' */ 424 P0_4_AMUXA = 4, /* Analog mux bus A */ 425 P0_4_AMUXB = 5, /* Analog mux bus B */ 426 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 427 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 428 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 429 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 430 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 431 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 432 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 433 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 434 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 435 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 436 P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 437 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 438 439 /* P0.5 */ 440 P0_5_GPIO = 0, /* GPIO controls 'out' */ 441 P0_5_AMUXA = 4, /* Analog mux bus A */ 442 P0_5_AMUXB = 5, /* Analog mux bus B */ 443 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 444 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 445 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 446 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 447 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 448 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 449 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 450 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 451 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 452 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 453 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 454 P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 455 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 456 457 /* P2.0 */ 458 P2_0_GPIO = 0, /* GPIO controls 'out' */ 459 P2_0_AMUXA = 4, /* Analog mux bus A */ 460 P2_0_AMUXB = 5, /* Analog mux bus B */ 461 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 462 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 463 P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 464 P2_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 465 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 466 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 467 P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 468 P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 469 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 470 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 471 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 472 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 473 P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ 474 475 /* P2.1 */ 476 P2_1_GPIO = 0, /* GPIO controls 'out' */ 477 P2_1_AMUXA = 4, /* Analog mux bus A */ 478 P2_1_AMUXB = 5, /* Analog mux bus B */ 479 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 480 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 481 P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 482 P2_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 483 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 484 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 485 P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 486 P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 487 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 488 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 489 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 490 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 491 P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ 492 493 /* P2.2 */ 494 P2_2_GPIO = 0, /* GPIO controls 'out' */ 495 P2_2_AMUXA = 4, /* Analog mux bus A */ 496 P2_2_AMUXB = 5, /* Analog mux bus B */ 497 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 498 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 499 P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 500 P2_2_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 501 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 502 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 503 P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 504 P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 505 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 506 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 507 P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ 508 509 /* P2.3 */ 510 P2_3_GPIO = 0, /* GPIO controls 'out' */ 511 P2_3_AMUXA = 4, /* Analog mux bus A */ 512 P2_3_AMUXB = 5, /* Analog mux bus B */ 513 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 514 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 515 P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 516 P2_3_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 517 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 518 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 519 P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 520 P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 521 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 522 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 523 P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ 524 525 /* P2.4 */ 526 P2_4_GPIO = 0, /* GPIO controls 'out' */ 527 P2_4_AMUXA = 4, /* Analog mux bus A */ 528 P2_4_AMUXB = 5, /* Analog mux bus B */ 529 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 530 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 531 P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 532 P2_4_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 533 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 534 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 535 P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 536 P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 537 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 538 P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ 539 540 /* P2.5 */ 541 P2_5_GPIO = 0, /* GPIO controls 'out' */ 542 P2_5_AMUXA = 4, /* Analog mux bus A */ 543 P2_5_AMUXB = 5, /* Analog mux bus B */ 544 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 545 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 546 P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 547 P2_5_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 548 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 549 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 550 P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 551 P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 552 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 553 P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ 554 555 /* P2.6 */ 556 P2_6_GPIO = 0, /* GPIO controls 'out' */ 557 P2_6_AMUXA = 4, /* Analog mux bus A */ 558 P2_6_AMUXB = 5, /* Analog mux bus B */ 559 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 560 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 561 P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 562 P2_6_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 563 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 564 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 565 P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 566 P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 567 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 568 P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 569 P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ 570 571 /* P2.7 */ 572 P2_7_GPIO = 0, /* GPIO controls 'out' */ 573 P2_7_AMUXA = 4, /* Analog mux bus A */ 574 P2_7_AMUXB = 5, /* Analog mux bus B */ 575 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 576 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 577 P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 578 P2_7_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 579 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 580 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 581 P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 582 P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 583 P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 584 P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ 585 586 /* P3.0 */ 587 P3_0_GPIO = 0, /* GPIO controls 'out' */ 588 P3_0_AMUXA = 4, /* Analog mux bus A */ 589 P3_0_AMUXB = 5, /* Analog mux bus B */ 590 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 591 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 592 P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 593 P3_0_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 594 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 595 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 596 P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 597 P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 598 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 599 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 600 P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ 601 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 602 P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ 603 604 /* P3.1 */ 605 P3_1_GPIO = 0, /* GPIO controls 'out' */ 606 P3_1_AMUXA = 4, /* Analog mux bus A */ 607 P3_1_AMUXB = 5, /* Analog mux bus B */ 608 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 609 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 610 P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 611 P3_1_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 612 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 613 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 614 P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 615 P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 616 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 617 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 618 P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ 619 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 620 P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ 621 622 /* P5.0 */ 623 P5_0_GPIO = 0, /* GPIO controls 'out' */ 624 P5_0_AMUXA = 4, /* Analog mux bus A */ 625 P5_0_AMUXB = 5, /* Analog mux bus B */ 626 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 627 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 628 P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 629 P5_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 630 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 631 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 632 P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 633 P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 634 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 635 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 636 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 637 P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ 638 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 639 640 /* P5.1 */ 641 P5_1_GPIO = 0, /* GPIO controls 'out' */ 642 P5_1_AMUXA = 4, /* Analog mux bus A */ 643 P5_1_AMUXB = 5, /* Analog mux bus B */ 644 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 645 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 646 P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 647 P5_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 648 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 649 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 650 P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 651 P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 652 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 653 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 654 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 655 P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ 656 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 657 658 /* P5.6 */ 659 P5_6_GPIO = 0, /* GPIO controls 'out' */ 660 P5_6_AMUXA = 4, /* Analog mux bus A */ 661 P5_6_AMUXB = 5, /* Analog mux bus B */ 662 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 663 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 664 P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 665 P5_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 666 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 667 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 668 P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 669 P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 670 671 /* P5.7 */ 672 P5_7_GPIO = 0, /* GPIO controls 'out' */ 673 P5_7_AMUXA = 4, /* Analog mux bus A */ 674 P5_7_AMUXB = 5, /* Analog mux bus B */ 675 P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 676 P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 677 P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 678 P5_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 679 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 680 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 681 P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 682 P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 683 684 /* P6.2 */ 685 P6_2_GPIO = 0, /* GPIO controls 'out' */ 686 P6_2_AMUXA = 4, /* Analog mux bus A */ 687 P6_2_AMUXB = 5, /* Analog mux bus B */ 688 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 689 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 690 P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 691 P6_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 692 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 693 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 694 P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 695 P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 696 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 697 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 698 699 /* P6.3 */ 700 P6_3_GPIO = 0, /* GPIO controls 'out' */ 701 P6_3_AMUXA = 4, /* Analog mux bus A */ 702 P6_3_AMUXB = 5, /* Analog mux bus B */ 703 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 704 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 705 P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 706 P6_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 707 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 708 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 709 P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 710 P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 711 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 712 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 713 714 /* P6.4 */ 715 P6_4_GPIO = 0, /* GPIO controls 'out' */ 716 P6_4_AMUXA = 4, /* Analog mux bus A */ 717 P6_4_AMUXB = 5, /* Analog mux bus B */ 718 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 719 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 720 P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 721 P6_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 722 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 723 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 724 P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 725 P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 726 P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ 727 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 728 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 729 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 730 P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ 731 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 732 733 /* P6.5 */ 734 P6_5_GPIO = 0, /* GPIO controls 'out' */ 735 P6_5_AMUXA = 4, /* Analog mux bus A */ 736 P6_5_AMUXB = 5, /* Analog mux bus B */ 737 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 738 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 739 P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 740 P6_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 741 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 742 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 743 P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 744 P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 745 P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ 746 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 747 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 748 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 749 P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ 750 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 751 752 /* P6.6 */ 753 P6_6_GPIO = 0, /* GPIO controls 'out' */ 754 P6_6_AMUXA = 4, /* Analog mux bus A */ 755 P6_6_AMUXB = 5, /* Analog mux bus B */ 756 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 757 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 758 P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 759 P6_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 760 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 761 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 762 P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 763 P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 764 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 765 P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ 766 767 /* P6.7 */ 768 P6_7_GPIO = 0, /* GPIO controls 'out' */ 769 P6_7_AMUXA = 4, /* Analog mux bus A */ 770 P6_7_AMUXB = 5, /* Analog mux bus B */ 771 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 772 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 773 P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 774 P6_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 775 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 776 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 777 P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 778 P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 779 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 780 P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ 781 782 /* P7.0 */ 783 P7_0_GPIO = 0, /* GPIO controls 'out' */ 784 P7_0_AMUXA = 4, /* Analog mux bus A */ 785 P7_0_AMUXB = 5, /* Analog mux bus B */ 786 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 787 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 788 P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 789 P7_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 790 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ 791 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ 792 P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ 793 P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ 794 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 795 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 796 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 797 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 798 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 799 800 /* P7.1 */ 801 P7_1_GPIO = 0, /* GPIO controls 'out' */ 802 P7_1_AMUXA = 4, /* Analog mux bus A */ 803 P7_1_AMUXB = 5, /* Analog mux bus B */ 804 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 805 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 806 P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 807 P7_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 808 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ 809 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ 810 P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ 811 P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ 812 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 813 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 814 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 815 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 816 817 /* P7.2 */ 818 P7_2_GPIO = 0, /* GPIO controls 'out' */ 819 P7_2_AMUXA = 4, /* Analog mux bus A */ 820 P7_2_AMUXB = 5, /* Analog mux bus B */ 821 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 822 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 823 P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 824 P7_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 825 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 826 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 827 P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 828 P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 829 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 830 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 831 832 /* P7.3 */ 833 P7_3_GPIO = 0, /* GPIO controls 'out' */ 834 P7_3_AMUXA = 4, /* Analog mux bus A */ 835 P7_3_AMUXB = 5, /* Analog mux bus B */ 836 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 837 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 838 P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 839 P7_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 840 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 841 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 842 P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 843 P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 844 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 845 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 846 847 /* P7.7 */ 848 P7_7_GPIO = 0, /* GPIO controls 'out' */ 849 P7_7_AMUXA = 4, /* Analog mux bus A */ 850 P7_7_AMUXB = 5, /* Analog mux bus B */ 851 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 852 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 853 P7_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 854 P7_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 855 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 856 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 857 P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 858 P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 859 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 860 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 861 862 /* P8.0 */ 863 P8_0_GPIO = 0, /* GPIO controls 'out' */ 864 P8_0_AMUXA = 4, /* Analog mux bus A */ 865 P8_0_AMUXB = 5, /* Analog mux bus B */ 866 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 867 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 868 P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 869 P8_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 870 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 871 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 872 P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 873 P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 874 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 875 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 876 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 877 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 878 879 /* P8.1 */ 880 P8_1_GPIO = 0, /* GPIO controls 'out' */ 881 P8_1_AMUXA = 4, /* Analog mux bus A */ 882 P8_1_AMUXB = 5, /* Analog mux bus B */ 883 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 884 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 885 P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 886 P8_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ 887 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 888 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 889 P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 890 P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 891 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 892 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 893 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 894 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 895 896 /* P9.0 */ 897 P9_0_GPIO = 0, /* GPIO controls 'out' */ 898 P9_0_AMUXA = 4, /* Analog mux bus A */ 899 P9_0_AMUXB = 5, /* Analog mux bus B */ 900 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 901 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 902 P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 903 P9_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:2 */ 904 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 905 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 906 P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 907 P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 908 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 909 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 910 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 911 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 912 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 913 914 /* P9.1 */ 915 P9_1_GPIO = 0, /* GPIO controls 'out' */ 916 P9_1_AMUXA = 4, /* Analog mux bus A */ 917 P9_1_AMUXB = 5, /* Analog mux bus B */ 918 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 919 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 920 P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 921 P9_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:2 */ 922 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 923 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 924 P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 925 P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 926 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 927 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 928 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 929 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 930 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 931 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 932 933 /* P9.2 */ 934 P9_2_GPIO = 0, /* GPIO controls 'out' */ 935 P9_2_AMUXA = 4, /* Analog mux bus A */ 936 P9_2_AMUXB = 5, /* Analog mux bus B */ 937 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 938 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 939 P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 940 P9_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:2 */ 941 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 942 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 943 P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 944 P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 945 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 946 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 947 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 948 949 /* P9.3 */ 950 P9_3_GPIO = 0, /* GPIO controls 'out' */ 951 P9_3_AMUXA = 4, /* Analog mux bus A */ 952 P9_3_AMUXB = 5, /* Analog mux bus B */ 953 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 954 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 955 P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 956 P9_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:2 */ 957 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 958 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 959 P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 960 P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 961 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 962 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 963 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 964 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 965 966 /* P10.0 */ 967 P10_0_GPIO = 0, /* GPIO controls 'out' */ 968 P10_0_AMUXA = 4, /* Analog mux bus A */ 969 P10_0_AMUXB = 5, /* Analog mux bus B */ 970 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 971 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 972 P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ 973 P10_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:2 */ 974 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 975 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 976 P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 977 P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 978 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 979 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 980 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 981 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 982 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 983 984 /* P10.1 */ 985 P10_1_GPIO = 0, /* GPIO controls 'out' */ 986 P10_1_AMUXA = 4, /* Analog mux bus A */ 987 P10_1_AMUXB = 5, /* Analog mux bus B */ 988 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 989 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 990 P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ 991 P10_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:2 */ 992 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 993 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 994 P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 995 P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 996 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 997 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 998 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 999 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1000 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1001 1002 /* P10.2 */ 1003 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1004 P10_2_AMUXA = 4, /* Analog mux bus A */ 1005 P10_2_AMUXB = 5, /* Analog mux bus B */ 1006 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1007 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1008 P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 1009 P10_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:2 */ 1010 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1011 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1012 P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1013 P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1014 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 1015 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 1016 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1017 1018 /* P10.3 */ 1019 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1020 P10_3_AMUXA = 4, /* Analog mux bus A */ 1021 P10_3_AMUXB = 5, /* Analog mux bus B */ 1022 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1023 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1024 P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 1025 P10_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:2 */ 1026 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1027 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1028 P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1029 P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1030 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 1031 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 1032 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1033 1034 /* P10.4 */ 1035 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1036 P10_4_AMUXA = 4, /* Analog mux bus A */ 1037 P10_4_AMUXB = 5, /* Analog mux bus B */ 1038 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1039 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1040 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 1041 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:3 */ 1042 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1043 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1044 P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1045 P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1046 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1047 1048 /* P10.5 */ 1049 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1050 P10_5_AMUXA = 4, /* Analog mux bus A */ 1051 P10_5_AMUXB = 5, /* Analog mux bus B */ 1052 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1053 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1054 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1055 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:3 */ 1056 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1057 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1058 P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1059 P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1060 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1061 1062 /* P11.0 */ 1063 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1064 P11_0_AMUXA = 4, /* Analog mux bus A */ 1065 P11_0_AMUXB = 5, /* Analog mux bus B */ 1066 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1067 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1068 P11_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:6 */ 1069 P11_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:3 */ 1070 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1071 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1072 P11_0_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 1073 P11_0_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 1074 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1075 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 1076 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 1077 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 1078 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1079 1080 /* P11.1 */ 1081 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1082 P11_1_AMUXA = 4, /* Analog mux bus A */ 1083 P11_1_AMUXB = 5, /* Analog mux bus B */ 1084 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1085 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1086 P11_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:6 */ 1087 P11_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:3 */ 1088 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1089 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1090 P11_1_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1091 P11_1_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1092 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1093 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 1094 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 1095 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 1096 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1097 1098 /* P11.2 */ 1099 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1100 P11_2_AMUXA = 4, /* Analog mux bus A */ 1101 P11_2_AMUXB = 5, /* Analog mux bus B */ 1102 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1103 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1104 P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ 1105 P11_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:3 */ 1106 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1107 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1108 P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1109 P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1110 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1111 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 1112 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 1113 1114 /* P11.3 */ 1115 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1116 P11_3_AMUXA = 4, /* Analog mux bus A */ 1117 P11_3_AMUXB = 5, /* Analog mux bus B */ 1118 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1119 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1120 P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ 1121 P11_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:3 */ 1122 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1123 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1124 P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1125 P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1126 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1127 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 1128 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 1129 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1130 1131 /* P11.4 */ 1132 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1133 P11_4_AMUXA = 4, /* Analog mux bus A */ 1134 P11_4_AMUXB = 5, /* Analog mux bus B */ 1135 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1136 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1137 P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:7 */ 1138 P11_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:3 */ 1139 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1140 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1141 P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1142 P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1143 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1144 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 1145 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1146 1147 /* P11.5 */ 1148 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1149 P11_5_AMUXA = 4, /* Analog mux bus A */ 1150 P11_5_AMUXB = 5, /* Analog mux bus B */ 1151 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1152 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1153 P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:7 */ 1154 P11_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:3 */ 1155 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1156 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1157 P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1158 P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1159 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1160 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 1161 1162 /* P11.6 */ 1163 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1164 P11_6_AMUXA = 4, /* Analog mux bus A */ 1165 P11_6_AMUXB = 5, /* Analog mux bus B */ 1166 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1167 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1168 P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:7 */ 1169 P11_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:3 */ 1170 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1171 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1172 P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1173 P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1174 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1175 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 1176 1177 /* P11.7 */ 1178 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1179 P11_7_AMUXA = 4, /* Analog mux bus A */ 1180 P11_7_AMUXB = 5, /* Analog mux bus B */ 1181 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1182 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1183 P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:7 */ 1184 P11_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:3 */ 1185 P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1186 P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1187 P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1188 P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1189 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1190 1191 /* P12.6 */ 1192 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1193 P12_6_AMUXA = 4, /* Analog mux bus A */ 1194 P12_6_AMUXB = 5, /* Analog mux bus B */ 1195 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1196 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1197 P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:7 */ 1198 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:3 */ 1199 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1200 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1201 P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1202 P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1203 1204 /* P12.7 */ 1205 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1206 P12_7_AMUXA = 4, /* Analog mux bus A */ 1207 P12_7_AMUXB = 5, /* Analog mux bus B */ 1208 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1209 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1210 P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:7 */ 1211 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:3 */ 1212 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1213 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1214 P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1215 P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1216 1217 /* USBDP */ 1218 USBDP_GPIO = 0, /* GPIO controls 'out' */ 1219 1220 /* USBDM */ 1221 USBDM_GPIO = 0 /* GPIO controls 'out' */ 1222 } en_hsiom_sel_t; 1223 1224 #endif /* _GPIO_PSOC6_03_68_QFN_H_ */ 1225 1226 1227 /* [] END OF FILE */ 1228
