1 /***************************************************************************//** 2 * \file cy8c6347bzi_bld34.h 3 * 4 * \brief 5 * CY8C6347BZI-BLD34 device header 6 * 7 * \note 8 * Generator version: 1.6.0.414 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CY8C6347BZI_BLD34_H_ 29 #define _CY8C6347BZI_BLD34_H_ 30 31 /** 32 * \addtogroup group_device CY8C6347BZI-BLD34 33 * \{ 34 */ 35 36 /** 37 * \addtogroup Configuration_of_CMSIS 38 * \{ 39 */ 40 41 /******************************************************************************* 42 * Interrupt Number Definition 43 *******************************************************************************/ 44 45 typedef enum { 46 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 47 (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 48 (defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \ 49 (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) 50 /* ARM Cortex-M0+ Core Interrupt Numbers */ 51 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 52 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 53 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 54 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 55 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 56 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 57 /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */ 58 NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */ 59 NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */ 60 NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */ 61 NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */ 62 NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */ 63 NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */ 64 NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */ 65 NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */ 66 NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */ 67 NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */ 68 NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */ 69 NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */ 70 NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */ 71 NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */ 72 NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */ 73 NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */ 74 NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */ 75 NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */ 76 NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */ 77 NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */ 78 NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */ 79 NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */ 80 NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */ 81 NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */ 82 NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */ 83 NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */ 84 NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */ 85 NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */ 86 NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */ 87 NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */ 88 NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */ 89 NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */ 90 unconnected_IRQn = 240 /*!< 240 Unconnected */ 91 #else 92 /* ARM Cortex-M4 Core Interrupt Numbers */ 93 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 94 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 95 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 96 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ 97 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 98 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 99 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 100 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 101 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 102 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 103 /* CY8C6347BZI-BLD34 Peripheral Interrupt Numbers */ 104 ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ 105 ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ 106 ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ 107 ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ 108 ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ 109 ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ 110 ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ 111 ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ 112 ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ 113 ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ 114 ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ 115 ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ 116 ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ 117 ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ 118 ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ 119 ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ 120 ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ 121 lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ 122 scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ 123 srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ 124 srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ 125 srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ 126 srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 127 pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ 128 bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ 129 cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ 130 cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ 131 cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ 132 cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ 133 cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ 134 cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ 135 cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ 136 cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ 137 cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ 138 cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ 139 cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ 140 cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ 141 cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ 142 cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ 143 cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ 144 cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ 145 scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ 146 scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ 147 scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ 148 scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ 149 scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ 150 scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ 151 scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ 152 scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ 153 csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ 154 cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ 155 cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ 156 cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ 157 cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ 158 cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ 159 cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ 160 cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ 161 cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ 162 cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ 163 cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ 164 cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ 165 cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ 166 cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ 167 cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ 168 cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ 169 cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ 170 cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ 171 cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ 172 cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ 173 cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ 174 cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ 175 cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ 176 cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ 177 cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ 178 cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ 179 cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ 180 cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ 181 cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ 182 cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ 183 cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ 184 cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ 185 cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ 186 cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ 187 cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ 188 cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ 189 cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ 190 cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ 191 cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ 192 cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ 193 cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ 194 tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ 195 tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ 196 tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ 197 tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ 198 tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ 199 tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ 200 tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ 201 tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ 202 tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ 203 tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ 204 tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ 205 tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ 206 tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ 207 tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ 208 tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ 209 tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ 210 tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ 211 tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ 212 tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ 213 tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ 214 tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ 215 tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ 216 tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ 217 tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ 218 tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ 219 tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ 220 tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ 221 tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ 222 tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ 223 tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ 224 tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ 225 tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ 226 udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ 227 udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ 228 udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ 229 udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ 230 udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ 231 udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ 232 udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ 233 udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ 234 udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ 235 udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ 236 udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ 237 udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ 238 udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ 239 udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ 240 udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ 241 udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ 242 pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ 243 audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ 244 audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ 245 profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ 246 smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ 247 usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ 248 usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ 249 usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ 250 pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ 251 unconnected_IRQn = 240 /*!< 240 Unconnected */ 252 #endif 253 } IRQn_Type; 254 255 256 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 257 (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 258 (defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \ 259 (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) 260 261 /* CY8C6347BZI-BLD34 interrupts that can be routed to the CM0+ NVIC */ 262 typedef enum { 263 ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ 264 ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ 265 ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ 266 ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ 267 ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ 268 ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ 269 ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ 270 ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ 271 ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ 272 ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ 273 ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ 274 ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ 275 ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ 276 ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ 277 ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ 278 ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ 279 ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ 280 lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ 281 scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ 282 srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ 283 srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ 284 srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ 285 srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 286 pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ 287 bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ 288 cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ 289 cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ 290 cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ 291 cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ 292 cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ 293 cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ 294 cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ 295 cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ 296 cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ 297 cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ 298 cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ 299 cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ 300 cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ 301 cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ 302 cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ 303 cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ 304 scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ 305 scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ 306 scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ 307 scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ 308 scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ 309 scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ 310 scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ 311 scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ 312 csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ 313 cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ 314 cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ 315 cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ 316 cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ 317 cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ 318 cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ 319 cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ 320 cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ 321 cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ 322 cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ 323 cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ 324 cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ 325 cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ 326 cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ 327 cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ 328 cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ 329 cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ 330 cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ 331 cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ 332 cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ 333 cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ 334 cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ 335 cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ 336 cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ 337 cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ 338 cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ 339 cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ 340 cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ 341 cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ 342 cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ 343 cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ 344 cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ 345 cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ 346 cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ 347 cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ 348 cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ 349 cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ 350 cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ 351 cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ 352 cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ 353 tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ 354 tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ 355 tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ 356 tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ 357 tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ 358 tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ 359 tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ 360 tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ 361 tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ 362 tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ 363 tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ 364 tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ 365 tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ 366 tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ 367 tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ 368 tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ 369 tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ 370 tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ 371 tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ 372 tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ 373 tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ 374 tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ 375 tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ 376 tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ 377 tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ 378 tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ 379 tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ 380 tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ 381 tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ 382 tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ 383 tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ 384 tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ 385 udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ 386 udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ 387 udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ 388 udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ 389 udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ 390 udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ 391 udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ 392 udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ 393 udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ 394 udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ 395 udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ 396 udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ 397 udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ 398 udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ 399 udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ 400 udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ 401 pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ 402 audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ 403 audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ 404 profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ 405 smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ 406 usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ 407 usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ 408 usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ 409 pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ 410 disconnected_IRQn = 240 /*!< 240 Disconnected */ 411 } cy_en_intr_t; 412 413 #endif 414 415 /******************************************************************************* 416 * Processor and Core Peripheral Section 417 *******************************************************************************/ 418 419 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 420 (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 421 (defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \ 422 (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) 423 424 /* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ 425 #define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ 426 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 427 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 428 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 429 #define __MPU_PRESENT 1 /*!< MPU present or not */ 430 431 /** \} Configuration_of_CMSIS */ 432 433 #include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ 434 435 #else 436 437 /* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ 438 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 439 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 440 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 441 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 442 #define __MPU_PRESENT 1 /*!< MPU present or not */ 443 #define __FPU_PRESENT 1 /*!< FPU present or not */ 444 #define __CM0P_PRESENT 1 /*!< CM0P present or not */ 445 #define __DTCM_PRESENT 0 /*!< DTCM present or not */ 446 #define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ 447 #define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ 448 449 /** \} Configuration_of_CMSIS */ 450 451 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 452 453 #endif 454 455 /* Memory Blocks */ 456 #define CY_ROM_BASE 0x00000000UL 457 #define CY_ROM_SIZE 0x00020000UL 458 #define CY_SRAM_BASE 0x08000000UL 459 #define CY_SRAM_SIZE 0x00048000UL 460 #define CY_FLASH_BASE 0x10000000UL 461 #define CY_FLASH_SIZE 0x00100000UL 462 #define CY_EM_EEPROM_BASE 0x14000000UL 463 #define CY_EM_EEPROM_SIZE 0x00008000UL 464 #define CY_SFLASH_BASE 0x16000000UL 465 #define CY_SFLASH_SIZE 0x00008000UL 466 #define CY_XIP_BASE 0x18000000UL 467 #define CY_XIP_SIZE 0x08000000UL 468 #define CY_EFUSE_BASE 0x402C0800UL 469 #define CY_EFUSE_SIZE 0x00000200UL 470 471 #include "system_psoc6.h" /*!< PSoC 6 System */ 472 473 /* IP List */ 474 #define CY_IP_MXAUDIOSS 1u 475 #define CY_IP_MXAUDIOSS_INSTANCES 1u 476 #define CY_IP_MXAUDIOSS_VERSION 1u 477 #define CY_IP_MXBLESS 1u 478 #define CY_IP_MXBLESS_INSTANCES 1u 479 #define CY_IP_MXBLESS_VERSION 1u 480 #define CY_IP_M4CPUSS 1u 481 #define CY_IP_M4CPUSS_INSTANCES 1u 482 #define CY_IP_M4CPUSS_VERSION 1u 483 #define CY_IP_M4CPUSS_DMA 1u 484 #define CY_IP_M4CPUSS_DMA_INSTANCES 2u 485 #define CY_IP_M4CPUSS_DMA_VERSION 1u 486 #define CY_IP_MXCSDV2 1u 487 #define CY_IP_MXCSDV2_INSTANCES 1u 488 #define CY_IP_MXCSDV2_VERSION 1u 489 #define CY_IP_MXEFUSE 1u 490 #define CY_IP_MXEFUSE_INSTANCES 1u 491 #define CY_IP_MXEFUSE_VERSION 1u 492 #define CY_IP_MXS40IOSS 1u 493 #define CY_IP_MXS40IOSS_INSTANCES 1u 494 #define CY_IP_MXS40IOSS_VERSION 1u 495 #define CY_IP_MXLCD 1u 496 #define CY_IP_MXLCD_INSTANCES 1u 497 #define CY_IP_MXLCD_VERSION 1u 498 #define CY_IP_MXLPCOMP 1u 499 #define CY_IP_MXLPCOMP_INSTANCES 1u 500 #define CY_IP_MXLPCOMP_VERSION 1u 501 #define CY_IP_MXS40PASS 1u 502 #define CY_IP_MXS40PASS_INSTANCES 1u 503 #define CY_IP_MXS40PASS_VERSION 1u 504 #define CY_IP_MXS40PASS_SAR 1u 505 #define CY_IP_MXS40PASS_SAR_INSTANCES 1u 506 #define CY_IP_MXS40PASS_SAR_VERSION 1u 507 #define CY_IP_MXS40PASS_CTDAC 1u 508 #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u 509 #define CY_IP_MXS40PASS_CTDAC_VERSION 1u 510 #define CY_IP_MXS40PASS_CTB 1u 511 #define CY_IP_MXS40PASS_CTB_INSTANCES 1u 512 #define CY_IP_MXS40PASS_CTB_VERSION 1u 513 #define CY_IP_MXPERI 1u 514 #define CY_IP_MXPERI_INSTANCES 1u 515 #define CY_IP_MXPERI_VERSION 1u 516 #define CY_IP_MXPERI_TR 1u 517 #define CY_IP_MXPERI_TR_INSTANCES 1u 518 #define CY_IP_MXPERI_TR_VERSION 1u 519 #define CY_IP_MXPROFILE 1u 520 #define CY_IP_MXPROFILE_INSTANCES 1u 521 #define CY_IP_MXPROFILE_VERSION 1u 522 #define CY_IP_MXSCB 1u 523 #define CY_IP_MXSCB_INSTANCES 9u 524 #define CY_IP_MXSCB_VERSION 1u 525 #define CY_IP_MXSMIF 1u 526 #define CY_IP_MXSMIF_INSTANCES 1u 527 #define CY_IP_MXSMIF_VERSION 1u 528 #define CY_IP_MXS40SRSS 1u 529 #define CY_IP_MXS40SRSS_INSTANCES 1u 530 #define CY_IP_MXS40SRSS_VERSION 1u 531 #define CY_IP_MXS40SRSS_RTC 1u 532 #define CY_IP_MXS40SRSS_RTC_INSTANCES 1u 533 #define CY_IP_MXS40SRSS_RTC_VERSION 1u 534 #define CY_IP_MXS40SRSS_MCWDT 1u 535 #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u 536 #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u 537 #define CY_IP_MXTCPWM 1u 538 #define CY_IP_MXTCPWM_INSTANCES 2u 539 #define CY_IP_MXTCPWM_VERSION 1u 540 #define CY_IP_MXUDB 1u 541 #define CY_IP_MXUDB_INSTANCES 1u 542 #define CY_IP_MXUDB_VERSION 1u 543 #define CY_IP_MXUSBFS 1u 544 #define CY_IP_MXUSBFS_INSTANCES 1u 545 #define CY_IP_MXUSBFS_VERSION 1u 546 547 #include "psoc6_01_config.h" 548 #include "gpio_psoc6_01_124_bga_sip.h" 549 550 #define CY_DEVICE_PSOC6ABLE2 551 #define CY_SILICON_ID 0xE22F2100UL 552 #define CY_HF_CLK_MAX_FREQ 150000000UL 553 554 #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL 555 556 /******************************************************************************* 557 * SFLASH 558 *******************************************************************************/ 559 560 #define SFLASH_BASE 0x16000000UL 561 #define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ 562 563 /******************************************************************************* 564 * PERI 565 *******************************************************************************/ 566 567 #define PERI_BASE 0x40010000UL 568 #define PERI_PPU_GR_MMIO0_BASE 0x40015000UL 569 #define PERI_PPU_GR_MMIO1_BASE 0x40015040UL 570 #define PERI_PPU_GR_MMIO2_BASE 0x40015080UL 571 #define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL 572 #define PERI_PPU_GR_MMIO4_BASE 0x40015100UL 573 #define PERI_PPU_GR_MMIO6_BASE 0x40015180UL 574 #define PERI_PPU_GR_MMIO9_BASE 0x40015240UL 575 #define PERI_PPU_GR_MMIO10_BASE 0x40015280UL 576 #define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL 577 #define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL 578 #define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL 579 #define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL 580 #define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL 581 #define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL 582 #define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL 583 #define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL 584 #define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL 585 #define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL 586 #define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL 587 #define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL 588 #define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL 589 #define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL 590 #define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL 591 #define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL 592 #define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL 593 #define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL 594 #define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL 595 #define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL 596 #define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL 597 #define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL 598 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL 599 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL 600 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL 601 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL 602 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL 603 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL 604 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL 605 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL 606 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL 607 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL 608 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL 609 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL 610 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL 611 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL 612 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL 613 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL 614 #define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL 615 #define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL 616 #define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL 617 #define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL 618 #define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL 619 #define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL 620 #define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL 621 #define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL 622 #define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL 623 #define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL 624 #define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL 625 #define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL 626 #define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL 627 #define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL 628 #define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL 629 #define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL 630 #define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL 631 #define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL 632 #define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL 633 #define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL 634 #define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL 635 #define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL 636 #define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL 637 #define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL 638 #define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL 639 #define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL 640 #define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL 641 #define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL 642 #define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL 643 #define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL 644 #define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL 645 #define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL 646 #define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL 647 #define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL 648 #define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ 649 #define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ 650 #define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ 651 #define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ 652 #define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ 653 #define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ 654 #define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ 655 #define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ 656 #define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ 657 #define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ 658 #define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ 659 #define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ 660 #define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ 661 #define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ 662 #define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ 663 #define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ 664 #define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ 665 #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ 666 #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ 667 #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ 668 #define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ 669 #define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ 670 #define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ 671 #define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ 672 #define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ 673 #define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ 674 #define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ 675 #define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ 676 #define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ 677 #define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ 678 #define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ 679 #define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ 680 #define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ 681 #define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ 682 #define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ 683 #define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ 684 #define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ 685 #define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ 686 #define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ 687 #define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ 688 #define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ 689 #define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ 690 #define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ 691 #define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ 692 #define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ 693 #define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ 694 #define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ 695 #define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ 696 #define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ 697 #define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ 698 #define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ 699 #define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ 700 #define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ 701 #define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ 702 #define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ 703 #define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ 704 #define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ 705 #define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ 706 #define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ 707 #define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ 708 #define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ 709 #define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ 710 #define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ 711 #define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ 712 #define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ 713 #define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ 714 #define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ 715 #define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ 716 #define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ 717 #define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ 718 #define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ 719 #define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ 720 #define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ 721 #define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ 722 #define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ 723 #define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ 724 #define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ 725 #define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ 726 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ 727 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ 728 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ 729 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ 730 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ 731 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ 732 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ 733 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ 734 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ 735 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ 736 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ 737 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ 738 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ 739 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ 740 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ 741 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ 742 #define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ 743 #define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ 744 #define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ 745 #define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ 746 #define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ 747 #define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ 748 #define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ 749 #define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ 750 #define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ 751 #define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ 752 #define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ 753 #define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ 754 #define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ 755 #define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ 756 #define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ 757 #define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ 758 #define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ 759 #define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ 760 #define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ 761 #define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ 762 #define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ 763 #define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ 764 #define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ 765 #define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ 766 #define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ 767 #define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ 768 #define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ 769 #define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ 770 #define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ 771 #define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ 772 #define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ 773 #define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ 774 #define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ 775 #define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ 776 777 /******************************************************************************* 778 * CPUSS 779 *******************************************************************************/ 780 781 #define CPUSS_BASE 0x40210000UL 782 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ 783 784 /******************************************************************************* 785 * FAULT 786 *******************************************************************************/ 787 788 #define FAULT_BASE 0x40220000UL 789 #define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ 790 #define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ 791 #define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ 792 793 /******************************************************************************* 794 * IPC 795 *******************************************************************************/ 796 797 #define IPC_BASE 0x40230000UL 798 #define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ 799 #define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ 800 #define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ 801 #define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ 802 #define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ 803 #define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ 804 #define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ 805 #define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ 806 #define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ 807 #define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ 808 #define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ 809 #define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ 810 #define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ 811 #define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ 812 #define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ 813 #define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ 814 #define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ 815 #define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ 816 #define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ 817 #define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ 818 #define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ 819 #define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ 820 #define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ 821 #define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ 822 #define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ 823 #define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ 824 #define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ 825 #define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ 826 #define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ 827 #define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ 828 #define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ 829 #define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ 830 #define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ 831 832 /******************************************************************************* 833 * PROT 834 *******************************************************************************/ 835 836 #define PROT_BASE 0x40240000UL 837 #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ 838 #define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ 839 #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ 840 #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ 841 #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ 842 #define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ 843 #define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ 844 #define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ 845 #define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ 846 #define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ 847 #define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ 848 #define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ 849 #define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ 850 #define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ 851 #define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ 852 #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ 853 #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ 854 #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ 855 #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ 856 #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ 857 #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ 858 #define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ 859 #define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ 860 #define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ 861 #define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ 862 #define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ 863 #define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ 864 #define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ 865 #define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ 866 #define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ 867 #define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ 868 #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ 869 #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ 870 #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ 871 #define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ 872 #define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ 873 #define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ 874 #define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ 875 #define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ 876 #define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ 877 #define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ 878 #define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ 879 #define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ 880 #define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ 881 #define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ 882 #define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ 883 #define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ 884 #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ 885 #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ 886 #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ 887 888 /******************************************************************************* 889 * FLASHC 890 *******************************************************************************/ 891 892 #define FLASHC_BASE 0x40250000UL 893 #define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ 894 #define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ 895 896 /******************************************************************************* 897 * SRSS 898 *******************************************************************************/ 899 900 #define SRSS_BASE 0x40260000UL 901 #define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ 902 #define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ 903 #define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ 904 905 /******************************************************************************* 906 * BACKUP 907 *******************************************************************************/ 908 909 #define BACKUP_BASE 0x40270000UL 910 #define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ 911 912 /******************************************************************************* 913 * DW 914 *******************************************************************************/ 915 916 #define DW0_BASE 0x40280000UL 917 #define DW1_BASE 0x40281000UL 918 #define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ 919 #define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ 920 #define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ 921 #define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ 922 #define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ 923 #define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ 924 #define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ 925 #define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ 926 #define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ 927 #define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ 928 #define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ 929 #define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ 930 #define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ 931 #define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ 932 #define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ 933 #define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ 934 #define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ 935 #define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ 936 #define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ 937 #define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ 938 #define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ 939 #define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ 940 #define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ 941 #define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ 942 #define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ 943 #define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ 944 #define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ 945 #define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ 946 #define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ 947 #define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ 948 #define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ 949 #define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ 950 #define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ 951 #define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ 952 953 /******************************************************************************* 954 * EFUSE 955 *******************************************************************************/ 956 957 #define EFUSE_BASE 0x402C0000UL 958 #define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ 959 960 /******************************************************************************* 961 * PROFILE 962 *******************************************************************************/ 963 964 #define PROFILE_BASE 0x402D0000UL 965 #define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ 966 #define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ 967 #define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ 968 #define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ 969 #define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ 970 #define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ 971 #define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ 972 #define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ 973 #define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ 974 975 /******************************************************************************* 976 * HSIOM 977 *******************************************************************************/ 978 979 #define HSIOM_BASE 0x40310000UL 980 #define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ 981 #define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ 982 #define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ 983 #define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ 984 #define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ 985 #define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ 986 #define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ 987 #define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ 988 #define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ 989 #define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ 990 #define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ 991 #define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ 992 #define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ 993 #define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ 994 #define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ 995 #define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ 996 997 /******************************************************************************* 998 * GPIO 999 *******************************************************************************/ 1000 1001 #define GPIO_BASE 0x40320000UL 1002 #define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ 1003 #define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ 1004 #define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ 1005 #define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ 1006 #define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ 1007 #define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ 1008 #define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ 1009 #define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ 1010 #define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ 1011 #define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ 1012 #define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ 1013 #define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ 1014 #define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ 1015 #define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ 1016 #define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ 1017 #define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ 1018 1019 /******************************************************************************* 1020 * SMARTIO 1021 *******************************************************************************/ 1022 1023 #define SMARTIO_BASE 0x40330000UL 1024 #define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ 1025 #define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ 1026 #define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ 1027 1028 /******************************************************************************* 1029 * UDB 1030 *******************************************************************************/ 1031 1032 #define UDB_BASE 0x40340000UL 1033 #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ 1034 #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ 1035 #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ 1036 #define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ 1037 #define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ 1038 #define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ 1039 #define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ 1040 #define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ 1041 #define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ 1042 #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ 1043 #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ 1044 #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ 1045 #define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */ 1046 #define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */ 1047 #define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */ 1048 #define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */ 1049 #define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */ 1050 #define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */ 1051 #define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */ 1052 #define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */ 1053 #define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */ 1054 #define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */ 1055 #define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */ 1056 #define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */ 1057 #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ 1058 #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ 1059 #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ 1060 #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ 1061 #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ 1062 #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ 1063 #define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */ 1064 #define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */ 1065 #define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */ 1066 #define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */ 1067 #define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */ 1068 #define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */ 1069 #define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */ 1070 #define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */ 1071 #define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */ 1072 #define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */ 1073 #define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */ 1074 #define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */ 1075 #define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */ 1076 #define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */ 1077 #define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */ 1078 #define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */ 1079 #define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */ 1080 #define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */ 1081 #define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */ 1082 #define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */ 1083 #define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */ 1084 #define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */ 1085 #define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */ 1086 1087 /******************************************************************************* 1088 * LPCOMP 1089 *******************************************************************************/ 1090 1091 #define LPCOMP_BASE 0x40350000UL 1092 #define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ 1093 1094 /******************************************************************************* 1095 * CSD 1096 *******************************************************************************/ 1097 1098 #define CSD0_BASE 0x40360000UL 1099 #define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ 1100 1101 /******************************************************************************* 1102 * TCPWM 1103 *******************************************************************************/ 1104 1105 #define TCPWM0_BASE 0x40380000UL 1106 #define TCPWM1_BASE 0x40390000UL 1107 #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ 1108 #define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ 1109 #define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ 1110 #define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ 1111 #define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ 1112 #define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ 1113 #define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ 1114 #define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ 1115 #define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ 1116 #define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ 1117 #define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ 1118 #define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ 1119 #define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ 1120 #define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ 1121 #define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ 1122 #define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ 1123 #define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ 1124 #define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ 1125 #define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ 1126 #define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ 1127 #define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ 1128 #define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ 1129 #define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ 1130 #define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ 1131 #define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ 1132 #define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ 1133 #define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ 1134 #define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ 1135 #define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ 1136 #define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ 1137 #define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ 1138 #define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ 1139 #define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ 1140 #define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ 1141 1142 /******************************************************************************* 1143 * LCD 1144 *******************************************************************************/ 1145 1146 #define LCD0_BASE 0x403B0000UL 1147 #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ 1148 1149 /******************************************************************************* 1150 * BLE 1151 *******************************************************************************/ 1152 1153 #define BLE_BASE 0x403C0000UL 1154 #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ 1155 #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ 1156 #define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ 1157 #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ 1158 #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ 1159 1160 /******************************************************************************* 1161 * USBFS 1162 *******************************************************************************/ 1163 1164 #define USBFS0_BASE 0x403F0000UL 1165 #define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ 1166 #define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ 1167 #define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ 1168 #define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ 1169 1170 /******************************************************************************* 1171 * SMIF 1172 *******************************************************************************/ 1173 1174 #define SMIF0_BASE 0x40420000UL 1175 #define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ 1176 #define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ 1177 #define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ 1178 #define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ 1179 #define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ 1180 1181 /******************************************************************************* 1182 * SCB 1183 *******************************************************************************/ 1184 1185 #define SCB0_BASE 0x40610000UL 1186 #define SCB1_BASE 0x40620000UL 1187 #define SCB2_BASE 0x40630000UL 1188 #define SCB3_BASE 0x40640000UL 1189 #define SCB4_BASE 0x40650000UL 1190 #define SCB5_BASE 0x40660000UL 1191 #define SCB6_BASE 0x40670000UL 1192 #define SCB7_BASE 0x40680000UL 1193 #define SCB8_BASE 0x40690000UL 1194 #define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ 1195 #define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ 1196 #define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ 1197 #define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ 1198 #define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ 1199 #define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ 1200 #define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ 1201 #define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ 1202 #define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ 1203 1204 /******************************************************************************* 1205 * CTBM 1206 *******************************************************************************/ 1207 1208 #define CTBM0_BASE 0x41100000UL 1209 #define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ 1210 1211 /******************************************************************************* 1212 * CTDAC 1213 *******************************************************************************/ 1214 1215 #define CTDAC0_BASE 0x41140000UL 1216 #define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ 1217 1218 /******************************************************************************* 1219 * SAR 1220 *******************************************************************************/ 1221 1222 #define SAR_BASE 0x411D0000UL 1223 #define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ 1224 1225 /******************************************************************************* 1226 * PASS 1227 *******************************************************************************/ 1228 1229 #define PASS_BASE 0x411F0000UL 1230 #define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ 1231 #define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ 1232 1233 /******************************************************************************* 1234 * I2S 1235 *******************************************************************************/ 1236 1237 #define I2S0_BASE 0x42A10000UL 1238 #define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ 1239 1240 /******************************************************************************* 1241 * PDM 1242 *******************************************************************************/ 1243 1244 #define PDM0_BASE 0x42A20000UL 1245 #define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ 1246 1247 1248 /* Backward compatibility definitions */ 1249 #define CY_SRAM0_BASE CY_SRAM_BASE 1250 #define CY_SRAM0_SIZE CY_SRAM_SIZE 1251 #define I2S I2S0 1252 #define PDM PDM0 1253 1254 /** \} CY8C6347BZI-BLD34 */ 1255 1256 #endif /* _CY8C6347BZI_BLD34_H_ */ 1257 1258 1259 /* [] END OF FILE */ 1260
