1# CAT1 (PSoC™ 6) Hardware Abstraction Layer (HAL) Release Notes 2The CAT1 Hardware Abstraction Layer (HAL) provides an implementation of the Hardware Abstraction Layer for the PSoC™ 6 family of chips. This API provides convenience methods for initializing and manipulating different hardware peripherals. Depending on the specific chip being used, not all features may be supported. 3 4This library is only supported on the Cortex-M4. It is not compatible with the Cortex-M0+. Any peripherals used by the Cortex-M0+ must be configured using the PDL and reserved on the Cortex-M4 by calling cyhal_hwmgr_reserve(). This ensures the HAL is aware the resource is in use and does not overuse it. 5 6### What's Included? 7This release of the CAT1 HAL includes support for the following drivers: 8* ADC 9* Clock 10* Comparator 11* CRC 12* DAC 13* DMA 14* EZ-I2C 15* Flash 16* GPIO 17* Hardware Manager 18* I2C 19* I2S 20* LowPower Timer (LPTimer) 21* OpAmp 22* PDM/PCM 23* Power Management (SysPM) 24* PWM 25* QSPI 26* Quadrature Decoder (QuadDec) 27* RTC 28* SDHC 29* SDIO 30* SPI 31* System 32* TDM 33* Timer 34* True Random Number Generator (TRNG) 35* UART 36* USB Device 37* WDT 38 39### What Changed? 40#### v2.0.0 41This major version update includes changes that break API compatibility with prior releases. Each major or breaking change is described below: 42* Clock: 43 1. Renamed cyhal_resource_inst_t CYHAL_CLOCK_<name> constants with CYHAL_CLOCK_RSC_<name>. Created new CYHAL_CLOCK_<name> constants of type cyhal_clock_t. 44 2. Replaced cyhal_clock_init with cyhal_clock_reserve. 45 3. Removed div_type & div_num from cyhal_clock_t. 46* DMA: 47 1. cyhal_dma_enable must be called after configuring the DMA, but before a trigger will initiate a transfer 48* Flash: 49 1. The data buffer passed to functions must be from SRAM, the driver no longer contains a scratch buffer to copy into. 50* GPIO: 51 1. cyhal_gpio_enable_output updated to require a new argument to specify whether the signal is level or edge based. 52 2. cyhal_gpio_connect_digital no longer takes the signal type parameter. 53 3. cyhal_gpio_register_callback now takes a structure containing details about the callback. 54 4. Removed deprecated functions cyhal_gpio_register_irq & cyhal_gpio_irq_enable 55* I2C: 56 1. Removed deprecated functions cyhal_i2c_register_irq & cyhal_i2c_irq_enable 57* I2S/TDM: 58 1. The mclk GPIO selection is moved into the RX/TX specific pins struct. This allows RX and TX to use separate mclk pins on devices that support this; 59 see the device datasheet for details. For devices which only support a single MCLK pin shared between RX and TX, there is no change in functionality; when 60 calling `cyhal_i2s_init` or `cyhal_tdm_init` the same `cyhal_gpio_t` value should be provided for both RX and TX. 61* PWM: 62 1. cyhal_pwm_connect_digital no longer takes the signal type parameter. 63 2. cyhal_pwm_init will always produce a non-inverted waveform on the specified pin, even if that pin natively produces an inverted 64 output (for example, the `line_compl` pins on PSoC™ devices). This improves consistency with the behavior of cyhal_pwm_init_adv. 65* QSPI: 66 1. cyhal_qspi_init() function got one additional parameter - shared clock (clk), which will allow users to use multiple HAL drivers which depends on same clock source. 67 2. cyhal_qspi_init() now takes io[x] and ssel pins as pointer to cyhal_qspi_slave_pin_config_t structure, that contain mentioned pins. 68 3. cyhal_qspi_slave_select_config function was replaced by cyhal_qspi_slave_configure, which provides possibility to add memory slaves with own data lines (instead of shared data lines and own slave select like it was when cyhal_qspi_slave_select_config has been used). cyhal_qspi_slave_config, as cyhal_qspi_init, takes cyhal_qspi_slave_pin_config_t as parameter. 69 4. cyhal_qspi_command_t structure was updated: address.value field removed, data_rate field was added into all command subsections. 70 5. Added address parameter to all transfer functions (cyhal_qspi_read, cyhal_qspi_read_async, cyhal_qspi_write, cyhal_qspi_write_async anb cyhal_qspi_transfer). 71 6. cyhal_qspi_datarate_t enum was added. Corresponding configuration fields are added into each sub-structure of cyhal_qspi_command_t. 72* SDHC: 73 1. cyhal_sdhc_init() and cyhal_sdhc_init_hw() functions got one additional parameter - shared clock (block_clk), which will allow users to use multiple HAL drivers which depends on same clock source. 74* SDIO: 75 1. Updated the names of enum cyhal_tranfer_t and its types CYHAL_READ and CYHAL_WRITE to cyhal_sdio_transfer_type_t, CYHAL_SDIO_XFER_TYPE_READ, and CYHAL_SDIO_XFER_TYPE_WRITE, respectively. 76 2. Removed deprecated functions cyhal_sdio_register_irq & cyhal_sdio_irq_enable 77* Timer: 78 1. cyhal_timer_connect_digital no longer takes the signal type parameter. 79* UART: 80 1. cyhal_uart_set_flow_control function was replaced by cyhal_uart_enable_flow_control, which only controls the enablement status of flow control. CTS / RTS pins are now provided via cyhal_uart_init() function. 81* I2C: 82 1. The following deprecated functions have been removed: cyhal_i2c_slave_config_write_buff, cyhal_i2c_slave_config_read_buff. 83* Other: 84 1. Removed cyhal_deprecated.h, and all associated code. 85NOTE: This version requires core-lib 1.3.0 or later 86#### v1.6.0 87* Added new TDM driver 88* Added support for 1.8v devices to SDHC/SDIO drivers 89* Extended System driver to support registering for other interrupts 90* Fixed issues with level trigger signals to the DMA driver 91* Fixed a few bugs in various drivers 92#### v1.5.0 93* Added new Quadrature Decoder (QuadDec) driver 94* Added digital hardware connection APIs to drivers 95* Fixed a few bugs in various drivers 96* Updated SDHC and MXSDHC-based SDIO communication functions to use semaphores in RTOS aware environments for improved performance 97* Added optional implementations for SDHC control pin APIs and RTOS aware delay API provided as weak functions in the PDL (Disabled by: DEFINES+=CYHAL_DISABLE_WEAK_FUNC_IMPL) 98#### v1.4.0 99* Renamed library from psoc6hal to mtb-hal-cat1 100* Added support for new PSoC™ 6 S4 devices 101* Extended clock support for QSPI and SDHC drivers 102* Fixed a few bugs in various drivers 103* Minor documentation updates 104#### v1.3.0 105* Added new Analog Comparator driver 106* Added new OpAmp driver 107* Extended ADC driver 108* Extended DAC driver 109* Extended SPI/QSPI drivers to support multiple slave select signals 110* Fixed SDHC based SDIO cyhal_sdio_is_busy() function to return status immediately instead of waiting until the transfer completes 111* Fixed a few bugs in various drivers 112* Minor update for documentation & branding 113#### v1.2.1 114* Added new option for SysPM driver to support tickless sleep in addition to deepsleep 115* Fixed an issue with deep-sleep wake-up in the SDIO and SDHC drivers that could cause intermittent communication failures 116* Minor bug fixes and documentation improvements 117#### v1.2.0 118* Added new Clock driver 119* Added new SysPM Power Management driver 120* Added new I2S driver 121* Added new PDM/PCM driver 122* Reduced flash memory usage for a number of drivers 123* Improved documentation for a number of drivers 124* Fixed a few bugs in various drivers 125NOTE: The new SysPM driver needs to be initialized by calling cyhal_syspm_init(). This is done automatically by Board Support Packages version 1.2.0 and later. 126#### v1.1.1 127* Improved documentation for a number of drivers 128* Fixed duplicate symbol definition with PDL 1.4.1 release 129* Minor bug fixes 130#### v1.1.0 131* Added new DMA driver 132* Added new EZ-I2C driver 133* Extended System driver to allow getting information about reset 134* Extended System driver to provide delay functions 135* Updated PWM driver to provide additional configuration options 136* Updated Timer driver to allow reading the current count 137* Updated RTC driver to support Day Light Savings time 138* Updated LP Timer driver to improve performance 139* Minor updates up avoid potential warnings on some toolchains 140* Multiple bug fixes across drivers 141#### v1.0.0 142* Initial release (ADC, CRC, DAC, Flash, GPIO, Hardware Manager, I2C, LP Timer, PWM, QSPI, RTC, SDHC, SDIO, SPI, System, Timer, TRNG, UART, USB Device, WDT) 143 144### Supported Software and Tools 145This version of the CAT1 Hardware Abstraction Layer was validated for compatibility with the following Software and Tools: 146 147| Software and Tools | Version | 148| :--- | :----: | 149| ModusToolbox™ Software Environment | 2.4.0 | 150| GCC Compiler | 10.3.1 | 151| IAR Compiler | 8.4 | 152| ARM Compiler | 6.11 | 153 154Minimum required ModusToolbox™ Software Environment: v2.0 155 156### More information 157Use the following links for more information, as needed: 158* [API Reference Guide](https://infineon.github.io/mtb-hal-cat1/html/modules.html) 159* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) 160* [Infineon GitHub](https://github.com/infineon) 161* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment) 162 163--- 164© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021. 165
