1 /** 2 * @file xmc4_eru_map.h 3 * @date 2016-10-27 4 * 5 * @cond 6 ********************************************************************************************************************* 7 * XMClib v2.1.24 - XMC Peripheral Driver Library 8 * 9 * Copyright (c) 2015-2019, Infineon Technologies AG 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 13 * following conditions are met: 14 * 15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials provided with the distribution. 20 * 21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 22 * products derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 33 * Infineon Technologies AG dave@infineon.com). 34 ********************************************************************************************************************* 35 * 36 * Change History 37 * -------------- 38 * 39 * 2015-02-20: 40 * - Initial version 41 * 42 * 2015-12-07: 43 * - Add XMC4300 support 44 * 45 * 2016-10-27: 46 * - Fixed: Remove incorrect ERU0_ETL1_INPUTB_P0_1 and replace it by ERU0_ETL1_INPUTB_SCU_HIB_SR1 47 * 48 * @endcond 49 */ 50 51 #ifndef XMC4_ERU_MAP_H 52 #define XMC4_ERU_MAP_H 53 54 /********************************************************************************************************************* 55 * MACROS 56 *********************************************************************************************************************/ 57 #define ERU0_ETL0 XMC_ERU0, 0 58 #define ERU0_ETL1 XMC_ERU0, 1 59 #define ERU0_ETL2 XMC_ERU0, 2 60 #define ERU0_ETL3 XMC_ERU0, 3 61 62 #define ERU0_OGU0 XMC_ERU0, 0 63 #define ERU0_OGU1 XMC_ERU0, 1 64 #define ERU0_OGU2 XMC_ERU0, 2 65 #define ERU0_OGU3 XMC_ERU0, 3 66 67 #define ERU1_ETL0 XMC_ERU1, 0 68 #define ERU1_ETL1 XMC_ERU1, 1 69 #define ERU1_ETL2 XMC_ERU1, 2 70 #define ERU1_ETL3 XMC_ERU1, 3 71 72 #define ERU1_OGU0 XMC_ERU1, 0 73 #define ERU1_OGU1 XMC_ERU1, 1 74 #define ERU1_OGU2 XMC_ERU1, 2 75 #define ERU1_OGU3 XMC_ERU1, 3 76 77 #if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) 78 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 79 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 80 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 81 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 82 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 83 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 84 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 85 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 86 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 87 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 88 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 89 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 90 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 91 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 92 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 93 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 94 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 95 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 96 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 97 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 98 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 99 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 100 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 101 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 102 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 103 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 104 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 105 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 106 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 107 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 108 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 109 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 110 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 111 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 112 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 113 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 114 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 115 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 116 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 117 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 118 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 119 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 120 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 121 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 122 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 123 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 124 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 125 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 126 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 127 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 128 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 129 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 130 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 131 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 132 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 133 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 134 135 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 136 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 137 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 138 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 139 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 140 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 141 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 142 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 143 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 144 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 145 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 146 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 147 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 148 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 149 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 150 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 151 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 152 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 153 #endif 154 155 156 #if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) 157 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 158 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 159 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 160 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 161 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 162 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 163 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 164 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 165 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 166 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 167 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 168 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 169 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 170 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 171 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 172 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 173 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 174 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 175 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 176 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 177 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 178 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 179 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 180 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 181 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 182 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 183 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 184 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 185 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 186 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 187 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 188 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 189 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 190 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 191 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 192 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 193 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 194 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 195 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 196 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 197 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 198 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 199 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 200 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 201 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 202 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 203 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 204 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 205 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 206 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 207 208 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 209 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 210 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 211 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 212 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 213 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 214 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 215 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 216 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 217 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 218 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 219 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 220 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 221 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 222 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 223 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 224 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 225 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 226 #endif 227 228 229 #if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) 230 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 231 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 232 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 233 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 234 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 235 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 236 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 237 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 238 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 239 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 240 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 241 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 242 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 243 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 244 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 245 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 246 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 247 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 248 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 249 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 250 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 251 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 252 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 253 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 254 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 255 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 256 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 257 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 258 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 259 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 260 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 261 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 262 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 263 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 264 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 265 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 266 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 267 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 268 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 269 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 270 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 271 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 272 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 273 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 274 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 275 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 276 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 277 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 278 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 279 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 280 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 281 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 282 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 283 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 284 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 285 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 286 287 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 288 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 289 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 290 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 291 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 292 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 293 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 294 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 295 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 296 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 297 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 298 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 299 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 300 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 301 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 302 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 303 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 304 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 305 #endif 306 307 308 #if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) 309 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 310 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 311 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 312 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 313 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 314 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 315 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 316 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 317 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 318 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 319 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 320 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 321 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 322 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 323 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 324 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 325 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 326 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 327 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 328 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 329 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 330 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 331 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 332 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 333 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 334 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 335 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 336 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 337 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 338 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 339 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 340 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 341 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 342 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 343 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 344 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 345 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 346 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 347 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 348 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 349 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 350 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 351 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 352 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 353 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 354 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 355 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 356 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 357 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 358 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 359 360 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 361 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 362 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 363 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 364 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 365 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 366 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 367 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 368 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 369 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 370 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 371 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 372 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 373 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 374 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 375 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 376 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 377 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 378 #endif 379 380 381 #if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) 382 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 383 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 384 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 385 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 386 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 387 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 388 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 389 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 390 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 391 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 392 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 393 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 394 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 395 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 396 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 397 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 398 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 399 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 400 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 401 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 402 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 403 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 404 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 405 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 406 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 407 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 408 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 409 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 410 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 411 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 412 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 413 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 414 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 415 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 416 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 417 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 418 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 419 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 420 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 421 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 422 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 423 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 424 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 425 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 426 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 427 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 428 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 429 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 430 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 431 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 432 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 433 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 434 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 435 436 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 437 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 438 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 439 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 440 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 441 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 442 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 443 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 444 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 445 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 446 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 447 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 448 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 449 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 450 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 451 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 452 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 453 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 454 #endif 455 456 457 #if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) 458 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 459 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 460 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 461 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 462 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 463 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 464 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 465 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 466 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 467 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 468 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 469 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 470 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 471 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 472 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 473 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 474 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 475 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 476 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 477 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 478 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 479 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 480 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 481 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 482 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 483 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 484 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 485 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 486 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 487 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 488 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 489 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 490 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 491 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 492 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 493 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 494 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 495 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 496 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 497 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 498 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 499 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 500 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 501 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 502 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 503 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 504 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 505 506 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 507 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 508 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 509 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 510 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 511 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 512 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 513 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 514 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 515 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 516 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 517 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 518 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 519 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 520 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 521 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 522 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 523 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 524 #endif 525 526 527 #if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) 528 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 529 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 530 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 531 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 532 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 533 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 534 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 535 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 536 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 537 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 538 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 539 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 540 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 541 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 542 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 543 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 544 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 545 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 546 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 547 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 548 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 549 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 550 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 551 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 552 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 553 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 554 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 555 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 556 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 557 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 558 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 559 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 560 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 561 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 562 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 563 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 564 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 565 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 566 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 567 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 568 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 569 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 570 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 571 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 572 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 573 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 574 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 575 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 576 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 577 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 578 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 579 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 580 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 581 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 582 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 583 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 584 585 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 586 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 587 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 588 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 589 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 590 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 591 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 592 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 593 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 594 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 595 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 596 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 597 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 598 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 599 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 600 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 601 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 602 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 603 #endif 604 605 606 #if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) 607 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 608 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 609 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 610 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 611 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 612 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 613 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 614 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 615 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 616 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 617 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 618 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 619 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 620 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 621 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 622 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 623 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 624 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 625 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 626 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 627 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 628 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 629 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 630 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 631 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 632 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 633 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 634 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 635 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 636 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 637 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 638 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 639 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 640 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 641 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 642 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 643 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 644 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 645 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 646 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 647 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 648 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 649 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 650 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 651 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 652 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 653 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 654 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 655 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 656 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 657 658 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 659 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 660 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 661 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 662 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 663 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 664 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 665 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 666 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 667 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 668 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 669 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 670 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 671 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 672 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 673 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 674 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 675 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 676 #endif 677 678 679 #if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) 680 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 681 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 682 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 683 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 684 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 685 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 686 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 687 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 688 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 689 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 690 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 691 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 692 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 693 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 694 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 695 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 696 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 697 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 698 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 699 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 700 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 701 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 702 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 703 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 704 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 705 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 706 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 707 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 708 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 709 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 710 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 711 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 712 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 713 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 714 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 715 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 716 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 717 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 718 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 719 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 720 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 721 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 722 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 723 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 724 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 725 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 726 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 727 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 728 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 729 #define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 730 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 731 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 732 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 733 #define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 734 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 735 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 736 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 737 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 738 739 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 740 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 741 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 742 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 743 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 744 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 745 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 746 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 747 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 748 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 749 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 750 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 751 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 752 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 753 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 754 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 755 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 756 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 757 #endif 758 759 760 #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) 761 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 762 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 763 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 764 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 765 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 766 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 767 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 768 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 769 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 770 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 771 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 772 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 773 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 774 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 775 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 776 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 777 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 778 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 779 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 780 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 781 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 782 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 783 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 784 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 785 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 786 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 787 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 788 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 789 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 790 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 791 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 792 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 793 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 794 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 795 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 796 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 797 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 798 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 799 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 800 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 801 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 802 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 803 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 804 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 805 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 806 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 807 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 808 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 809 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 810 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 811 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 812 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 813 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 814 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 815 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 816 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 817 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 818 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 819 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 820 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 821 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 822 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 823 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 824 825 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 826 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 827 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 828 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 829 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 830 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 831 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 832 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 833 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 834 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 835 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 836 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 837 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 838 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 839 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 840 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 841 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 842 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 843 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 844 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 845 #endif 846 847 848 #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) 849 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 850 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 851 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 852 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 853 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 854 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 855 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 856 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 857 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 858 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 859 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 860 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 861 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 862 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 863 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 864 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 865 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 866 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 867 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 868 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 869 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 870 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 871 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 872 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 873 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 874 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 875 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 876 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 877 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 878 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 879 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 880 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 881 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 882 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 883 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 884 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 885 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 886 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 887 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 888 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 889 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 890 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 891 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 892 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 893 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 894 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 895 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 896 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 897 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 898 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 899 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 900 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 901 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 902 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 903 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 904 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 905 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 906 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 907 908 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 909 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 910 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 911 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 912 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 913 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 914 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 915 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 916 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 917 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 918 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 919 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 920 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 921 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 922 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 923 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 924 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 925 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 926 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 927 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 928 #endif 929 930 931 #if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) 932 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 933 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 934 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 935 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 936 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 937 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 938 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 939 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 940 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 941 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 942 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 943 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 944 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 945 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 946 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 947 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 948 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 949 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 950 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 951 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 952 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 953 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 954 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 955 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 956 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 957 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 958 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 959 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 960 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 961 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 962 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 963 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 964 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 965 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 966 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 967 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 968 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 969 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 970 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 971 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 972 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 973 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 974 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 975 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 976 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 977 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 978 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 979 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 980 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 981 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 982 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 983 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 984 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 985 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 986 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 987 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 988 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 989 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 990 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 991 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 992 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 993 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 994 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 995 996 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 997 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 998 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 999 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1000 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1001 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1002 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1003 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1004 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1005 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1006 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1007 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1008 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1009 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1010 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1011 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1012 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1013 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1014 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1015 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1016 #endif 1017 1018 1019 #if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) 1020 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1021 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1022 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1023 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1024 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1025 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1026 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1027 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1028 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1029 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1030 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1031 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1032 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1033 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1034 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1035 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1036 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1037 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1038 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1039 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1040 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1041 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1042 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1043 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1044 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1045 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1046 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1047 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1048 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1049 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1050 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1051 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1052 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1053 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1054 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1055 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1056 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1057 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1058 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1059 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1060 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1061 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1062 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1063 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1064 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1065 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1066 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1067 #define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 1068 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1069 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1070 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1071 #define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 1072 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1073 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1074 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1075 #define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 1076 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1077 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1078 1079 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1080 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1081 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1082 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1083 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1084 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1085 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1086 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1087 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1088 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1089 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1090 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1091 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1092 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1093 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1094 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1095 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1096 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1097 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1098 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1099 #endif 1100 1101 1102 #if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) 1103 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1104 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1105 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1106 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1107 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1108 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1109 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1110 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1111 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1112 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1113 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1114 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1115 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1116 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1117 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1118 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1119 #define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 1120 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1121 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1122 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1123 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1124 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1125 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1126 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1127 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1128 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1129 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1130 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1131 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1132 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1133 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1134 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1135 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1136 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1137 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1138 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1139 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1140 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1141 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1142 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1143 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1144 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1145 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1146 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1147 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1148 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1149 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1150 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1151 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1152 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1153 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1154 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1155 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1156 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1157 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1158 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1159 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1160 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1161 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1162 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1163 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1164 1165 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1166 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1167 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1168 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1169 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1170 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1171 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1172 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1173 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1174 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1175 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1176 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1177 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1178 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1179 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1180 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1181 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1182 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1183 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1184 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1185 #endif 1186 1187 1188 #if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) 1189 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1190 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1191 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1192 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1193 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1194 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1195 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1196 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1197 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1198 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1199 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1200 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1201 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1202 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1203 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1204 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1205 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1206 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1207 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1208 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1209 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1210 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1211 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1212 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1213 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1214 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1215 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1216 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1217 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1218 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1219 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1220 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1221 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1222 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1223 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1224 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1225 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1226 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1227 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1228 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1229 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1230 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1231 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1232 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1233 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1234 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1235 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1236 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1237 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1238 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1239 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1240 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1241 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1242 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1243 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1244 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1245 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1246 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1247 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1248 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1249 1250 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1251 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1252 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1253 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1254 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1255 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1256 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1257 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1258 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1259 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1260 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1261 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1262 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1263 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1264 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1265 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1266 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1267 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1268 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1269 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1270 #endif 1271 1272 1273 #if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) 1274 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1275 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1276 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1277 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1278 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1279 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1280 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1281 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1282 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1283 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1284 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1285 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1286 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1287 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1288 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1289 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1290 #define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 1291 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1292 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1293 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1294 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1295 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1296 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1297 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1298 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1299 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1300 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1301 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1302 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1303 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1304 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1305 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1306 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1307 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1308 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1309 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1310 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1311 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1312 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1313 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1314 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1315 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1316 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1317 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1318 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1319 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1320 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1321 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1322 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1323 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1324 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1325 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1326 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1327 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1328 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1329 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1330 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1331 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1332 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1333 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1334 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1335 1336 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1337 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1338 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1339 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1340 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1341 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1342 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1343 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1344 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1345 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1346 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1347 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1348 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1349 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1350 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1351 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1352 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1353 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1354 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1355 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1356 #endif 1357 1358 1359 #if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) 1360 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1361 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1362 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1363 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1364 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1365 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1366 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1367 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1368 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1369 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1370 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1371 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1372 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1373 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1374 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1375 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1376 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1377 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1378 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1379 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1380 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1381 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1382 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1383 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1384 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1385 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1386 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1387 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1388 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1389 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1390 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1391 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1392 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1393 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1394 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1395 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1396 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1397 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1398 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1399 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1400 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1401 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1402 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1403 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1404 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1405 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1406 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1407 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1408 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1409 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1410 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1411 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1412 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1413 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1414 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1415 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1416 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1417 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1418 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1419 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1420 1421 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1422 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1423 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1424 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1425 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1426 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1427 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1428 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1429 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1430 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1431 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1432 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1433 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1434 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1435 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1436 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1437 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1438 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1439 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1440 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1441 #endif 1442 1443 1444 #if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) 1445 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1446 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1447 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1448 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1449 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1450 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1451 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1452 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1453 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1454 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1455 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1456 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1457 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1458 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1459 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1460 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1461 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1462 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1463 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1464 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1465 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1466 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1467 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1468 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1469 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1470 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1471 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1472 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1473 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1474 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1475 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1476 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1477 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1478 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1479 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1480 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1481 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1482 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1483 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1484 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1485 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1486 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1487 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1488 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1489 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1490 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1491 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1492 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1493 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1494 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1495 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1496 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1497 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1498 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1499 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1500 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1501 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1502 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1503 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1504 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1505 1506 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1507 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1508 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1509 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1510 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1511 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1512 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1513 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1514 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1515 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1516 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1517 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1518 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1519 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1520 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1521 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1522 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1523 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1524 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1525 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1526 #endif 1527 1528 1529 #if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) 1530 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1531 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1532 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1533 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1534 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1535 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1536 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1537 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1538 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1539 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1540 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1541 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1542 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1543 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1544 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1545 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1546 #define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 1547 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1548 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1549 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1550 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1551 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1552 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1553 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1554 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1555 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1556 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1557 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1558 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1559 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1560 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1561 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1562 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1563 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1564 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1565 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1566 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1567 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1568 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1569 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1570 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1571 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1572 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1573 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1574 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1575 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1576 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1577 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1578 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1579 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1580 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1581 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1582 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1583 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1584 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1585 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1586 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1587 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1588 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1589 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1590 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1591 1592 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1593 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1594 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1595 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1596 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1597 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1598 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1599 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1600 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1601 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1602 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1603 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1604 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1605 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1606 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1607 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1608 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1609 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1610 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1611 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1612 #endif 1613 1614 1615 #if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) 1616 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1617 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1618 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1619 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1620 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1621 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1622 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1623 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1624 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1625 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1626 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1627 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1628 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1629 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1630 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1631 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1632 #define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 1633 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1634 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1635 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1636 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1637 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1638 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1639 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1640 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1641 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1642 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1643 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1644 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1645 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1646 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1647 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1648 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1649 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1650 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1651 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1652 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1653 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1654 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1655 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1656 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1657 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1658 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1659 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1660 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1661 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1662 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1663 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1664 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1665 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1666 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1667 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1668 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1669 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1670 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1671 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1672 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1673 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1674 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1675 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1676 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1677 1678 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1679 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1680 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1681 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1682 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1683 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1684 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1685 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1686 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1687 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1688 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1689 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1690 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1691 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1692 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1693 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1694 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1695 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1696 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1697 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1698 #endif 1699 1700 1701 #if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) 1702 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1703 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1704 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1705 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1706 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1707 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1708 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1709 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1710 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1711 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1712 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1713 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1714 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1715 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1716 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1717 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1718 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1719 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1720 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1721 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1722 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1723 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1724 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1725 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1726 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1727 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1728 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1729 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1730 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1731 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1732 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1733 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1734 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1735 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1736 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1737 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1738 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1739 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1740 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1741 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1742 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1743 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1744 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1745 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1746 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1747 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1748 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1749 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1750 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1751 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1752 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1753 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1754 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1755 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1756 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1757 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1758 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1759 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1760 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1761 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1762 1763 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1764 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1765 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1766 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1767 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1768 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1769 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1770 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1771 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1772 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1773 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1774 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1775 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1776 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1777 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1778 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1779 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1780 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1781 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1782 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1783 #endif 1784 1785 1786 #if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) 1787 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1788 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1789 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1790 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1791 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1792 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1793 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1794 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1795 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1796 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1797 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1798 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1799 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1800 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1801 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1802 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1803 #define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 1804 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1805 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1806 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1807 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1808 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1809 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1810 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1811 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1812 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1813 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1814 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1815 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1816 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1817 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1818 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1819 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1820 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1821 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1822 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1823 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1824 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1825 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1826 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1827 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1828 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1829 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1830 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1831 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1832 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1833 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1834 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1835 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1836 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1837 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1838 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1839 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1840 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1841 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1842 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1843 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1844 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1845 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1846 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1847 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1848 1849 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1850 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1851 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1852 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1853 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1854 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1855 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1856 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1857 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1858 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1859 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1860 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1861 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1862 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1863 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1864 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1865 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1866 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1867 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1868 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1869 #endif 1870 1871 1872 #if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) 1873 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1874 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1875 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1876 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1877 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1878 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1879 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1880 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1881 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1882 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1883 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1884 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1885 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1886 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1887 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1888 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1889 #define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 1890 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1891 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1892 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1893 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1894 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1895 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1896 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1897 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1898 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1899 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1900 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1901 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1902 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1903 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1904 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1905 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1906 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1907 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1908 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1909 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1910 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1911 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1912 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1913 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 1914 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 1915 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 1916 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1917 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 1918 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 1919 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 1920 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1921 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 1922 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 1923 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 1924 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1925 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 1926 #define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 1927 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 1928 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 1929 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 1930 #define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 1931 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 1932 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1933 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 1934 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 1935 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 1936 1937 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1938 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1939 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1940 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1941 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1942 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1943 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1944 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1945 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1946 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1947 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1948 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1949 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1950 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1951 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1952 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1953 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1954 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1955 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1956 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1957 #endif 1958 1959 1960 #if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) 1961 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 1962 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 1963 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1964 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 1965 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 1966 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 1967 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 1968 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 1969 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 1970 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 1971 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 1972 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 1973 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 1974 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 1975 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 1976 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 1977 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 1978 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1979 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 1980 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 1981 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 1982 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 1983 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 1984 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 1985 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 1986 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 1987 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 1988 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 1989 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 1990 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 1991 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 1992 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 1993 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 1994 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 1995 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 1996 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 1997 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 1998 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1999 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 2000 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 2001 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 2002 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 2003 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 2004 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 2005 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 2006 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 2007 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 2008 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 2009 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 2010 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 2011 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 2012 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 2013 #define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 2014 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 2015 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 2016 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 2017 #define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 2018 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 2019 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 2020 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 2021 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 2022 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 2023 2024 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2025 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2026 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2027 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2028 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2029 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2030 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2031 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2032 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 2033 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2034 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2035 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 2036 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2037 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2038 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 2039 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2040 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2041 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 2042 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2043 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2044 #endif 2045 2046 2047 #if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) 2048 #define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 2049 #define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 2050 #define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 2051 #define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 2052 #define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 2053 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 2054 #define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 2055 #define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 2056 #define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 2057 #define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 2058 #define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 2059 #define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 2060 #define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 2061 #define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 2062 #define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 2063 #define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 2064 #define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 2065 #define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 2066 #define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 2067 #define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 2068 #define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 2069 #define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 2070 #define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 2071 #define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 2072 #define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 2073 #define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 2074 #define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 2075 #define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 2076 #define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 2077 #define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 2078 #define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 2079 #define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 2080 #define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 2081 #define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 2082 #define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 2083 #define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 2084 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 2085 #define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 2086 #define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 2087 #define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 2088 #define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 2089 #define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 2090 #define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 2091 #define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 2092 #define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 2093 #define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 2094 #define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 2095 #define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 2096 #define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 2097 #define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 2098 #define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 2099 #define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 2100 #define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 2101 #define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 2102 #define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 2103 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 2104 #define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 2105 #define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 2106 #define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 2107 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 2108 #define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 2109 #define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 2110 #define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 2111 2112 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2113 #define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2114 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2115 #define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2116 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2117 #define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2118 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2119 #define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2120 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 2121 #define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2122 #define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2123 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 2124 #define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2125 #define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2126 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 2127 #define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2128 #define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2129 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 2130 #define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 2131 #define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 2132 #endif 2133 2134 #endif /* XMC4_ERU_MAP_H */ 2135
