1 /**
2 * @file xmc_uart.h
3 * @date 2019-05-07
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial
41 *
42 * 2015-05-20:
43 * - Description updated <br>
44 * - Added XMC_UART_CH_TriggerServiceRequest() and XMC_UART_CH_SelectInterruptNodePointer <br>
45 *
46 * 2015-06-20:
47 * - Removed version macros and declaration of GetDriverVersion API <br>
48 *
49 * 2015-09-01:
50 * - Modified XMC_UART_CH_SetInputSource() for avoiding complete DXCR register overwriting. <br>
51 * - Modified XMC_UART_CH_EVENT_t enum for supporting XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent()
52 * for supporting multiple events configuration <br>
53 *
54 * 2016-05-20:
55 * - Added XMC_UART_CH_EnableDataTransmission() and XMC_UART_CH_DisableDataTransmission()
56 *
57 * 2017-10-25:
58 * - Added XMC_UART_CH_EnableMasterClock() and XMC_UART_CH_DisableMasterClock()
59 *
60 * 2019-05-07:
61 * - Added normal_divider_mode to XMC_UART_CH_CONFIG_t configuration structure.
62 * It selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection
63 * - Added XMC_UART_CH_SetBaudrateEx()
64 *
65 * @endcond
66 *
67 */
68
69 #ifndef XMC_UART_H
70 #define XMC_UART_H
71
72 /*********************************************************************************************************************
73 * HEADER FILES
74 *********************************************************************************************************************/
75
76 #include "xmc_usic.h"
77
78 /**
79 * @addtogroup XMClib XMC Peripheral Library
80 * @{
81 */
82
83 /**
84 * @addtogroup UART
85 * @brief Universal Asynchronous Receiver/Transmitter (UART) driver for XMC microcontroller family.
86 *
87 * The UART driver uses Universal Serial Interface Channel(USIC) module to implement UART protocol.
88 * It provides APIs to configure USIC channel for UART communication. The driver enables the user
89 * in getting the status of UART protocol events, configuring interrupt service requests, protocol
90 * related parameter configuration etc.
91 *
92 * UART driver features:
93 * -# Configuration structure XMC_UART_CH_CONFIG_t and initialization function XMC_UART_CH_Init()
94 * -# Enumeration of events with their bit masks @ref XMC_UART_CH_EVENT_t, @ref XMC_UART_CH_STATUS_FLAG_t
95 * -# Allows the selection of input source for the DX0 input stage using the API XMC_UART_CH_SetInputSource()
96 * -# Allows configuration of baudrate using XMC_UART_CH_SetBaudrate() and configuration of data length using
97 XMC_UART_CH_SetWordLength() and XMC_UART_CH_SetFrameLength()
98 * -# Provides the status of UART protocol events, XMC_UART_CH_GetStatusFlag()
99 * -# Allows transmission of data using XMC_UART_CH_Transmit() and gets received data using XMC_UART_CH_GetReceivedData()
100 *
101 * @{
102 */
103
104 /*********************************************************************************************************************
105 * MACROS
106 *********************************************************************************************************************/
107
108 #if defined(USIC0)
109 #define XMC_UART0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
110 #define XMC_UART0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
111 #endif
112
113 #if defined(USIC1)
114 #define XMC_UART1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
115 #define XMC_UART1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
116 #endif
117
118 #if defined(USIC2)
119 #define XMC_UART2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
120 #define XMC_UART2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
121 #endif
122
123 /*********************************************************************************************************************
124 * ENUMS
125 *********************************************************************************************************************/
126
127 /**
128 * UART driver status
129 */
130 typedef enum XMC_UART_CH_STATUS
131 {
132 XMC_UART_CH_STATUS_OK, /**< UART driver status : OK*/
133 XMC_UART_CH_STATUS_ERROR, /**< UART driver status : ERROR */
134 XMC_UART_CH_STATUS_BUSY /**< UART driver status : BUSY */
135 } XMC_UART_CH_STATUS_t;
136
137 /**
138 * UART portocol status. The enum values can be used for getting the status of UART channel.
139 *
140 */
141 typedef enum XMC_UART_CH_STATUS_FLAG
142 {
143 XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE = USIC_CH_PSR_ASCMode_TXIDLE_Msk, /**< UART Protocol Status transmit IDLE*/
144 XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE = USIC_CH_PSR_ASCMode_RXIDLE_Msk, /**< UART Protocol Status receive IDLE*/
145 XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED = USIC_CH_PSR_ASCMode_SBD_Msk, /**< UART Protocol Status synchronization break detected*/
146 XMC_UART_CH_STATUS_FLAG_COLLISION_DETECTED = USIC_CH_PSR_ASCMode_COL_Msk, /**< UART Protocol Status collision detected*/
147 XMC_UART_CH_STATUS_FLAG_RECEIVER_NOISE_DETECTED = USIC_CH_PSR_ASCMode_RNS_Msk, /**< UART Protocol Status receiver noise detected */
148 XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_0 = USIC_CH_PSR_ASCMode_FER0_Msk, /**< UART Protocol Status format error in stop bit 0 */
149 XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_1 = USIC_CH_PSR_ASCMode_FER1_Msk, /**< UART Protocol Status format error in stop bit 1 */
150 XMC_UART_CH_STATUS_FLAG_RECEIVE_FRAME_FINISHED = USIC_CH_PSR_ASCMode_RFF_Msk, /**< UART Protocol Status receive frame finished */
151 XMC_UART_CH_STATUS_FLAG_TRANSMITTER_FRAME_FINISHED = USIC_CH_PSR_ASCMode_TFF_Msk, /**< UART Protocol Status transmit frame finished */
152 XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY = USIC_CH_PSR_ASCMode_BUSY_Msk, /**< UART Protocol Status transfer status busy */
153 XMC_UART_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_ASCMode_RSIF_Msk, /**< UART Protocol Status receive start indication flag*/
154 XMC_UART_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_ASCMode_DLIF_Msk, /**< UART Protocol Status data lost indication flag*/
155 XMC_UART_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_ASCMode_TSIF_Msk, /**< UART Protocol Status transmit shift indication flag*/
156 XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_ASCMode_TBIF_Msk, /**< UART Protocol Status transmit buffer indication flag*/
157 XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_RIF_Msk, /**< UART Protocol Status receive indication flag*/
158 XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_AIF_Msk, /**< UART Protocol Status alternative receive indication flag*/
159 XMC_UART_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_ASCMode_BRGIF_Msk /**< UART Protocol Status baudrate generator indication flag*/
160 } XMC_UART_CH_STATUS_FLAG_t;
161
162 /**
163 * UART configuration events. The enums can be used for configuring events using the CCR register.
164 */
165 typedef enum XMC_CH_UART_EVENT
166 {
167 XMC_UART_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
168 XMC_UART_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
169 XMC_UART_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
170 XMC_UART_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
171 XMC_UART_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
172 XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
173 XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
174
175 XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK = USIC_CH_PCR_ASCMode_SBIEN_Msk, /**< Event synchronization break */
176 XMC_UART_CH_EVENT_COLLISION = USIC_CH_PCR_ASCMode_CDEN_Msk, /**< Event collision */
177 XMC_UART_CH_EVENT_RECEIVER_NOISE = USIC_CH_PCR_ASCMode_RNIEN_Msk, /**< Event receiver noise */
178 XMC_UART_CH_EVENT_FORMAT_ERROR = USIC_CH_PCR_ASCMode_FEIEN_Msk, /**< Event format error */
179 XMC_UART_CH_EVENT_FRAME_FINISHED = USIC_CH_PCR_ASCMode_FFIEN_Msk /**< Event frame finished */
180 } XMC_UART_CH_EVENT_t;
181
182 /**
183 * UART Input sampling frequency options
184 */
185 typedef enum XMC_UART_CH_INPUT_SAMPLING_FREQ
186 {
187 XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH, /**< Sampling frequency input fperiph*/
188 XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER /**< Sampling frequency input fractional divider*/
189 } XMC_UART_CH_INPUT_SAMPLING_FREQ_t;
190
191 /**
192 * UART input stages
193 */
194 typedef enum XMC_UART_CH_INPUT
195 {
196 XMC_UART_CH_INPUT_RXD = 0UL /**< UART input stage DX0*/
197 #if UC_FAMILY == XMC1
198 ,
199 XMC_UART_CH_INPUT_RXD1 = 3UL, /**< UART input stage DX3*/
200 XMC_UART_CH_INPUT_RXD2 = 5UL /**< UART input stage DX5*/
201 #endif
202 } XMC_UART_CH_INPUT_t;
203
204
205 /**
206 * UART channel interrupt node pointers
207 */
208 typedef enum XMC_UART_CH_INTERRUPT_NODE_POINTER
209 {
210 XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
211 XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
212 XMC_UART_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
213 XMC_UART_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
214 XMC_UART_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
215 } XMC_UART_CH_INTERRUPT_NODE_POINTER_t;
216
217 /*********************************************************************************************************************
218 * DATA STRUCTURES
219 *********************************************************************************************************************/
220
221 /**
222 * UART initialization structure
223 */
224 typedef struct XMC_UART_CH_CONFIG
225 {
226 uint32_t baudrate; /**< Desired baudrate. \b Range: minimum= 100, maximum= (fPERIPH * 1023)/(1024 * oversampling) */
227 bool normal_divider_mode; /**< Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection */
228 uint8_t data_bits; /**< Number of bits for the data field. Value configured as USIC channel word length. \n
229 \b Range: minimum= 1, maximum= 16*/
230 uint8_t frame_length; /**< Indicates nmber of bits in a frame. Configured as USIC channel frame length. \n
231 \b Range: minimum= 1, maximum= 63*/
232 uint8_t stop_bits; /**< Number of stop bits. \b Range: minimum= 1, maximum= 2 */
233 uint8_t oversampling; /**< Number of samples for a symbol(DCTQ).\b Range: minimum= 1, maximum= 32*/
234 XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Parity mode. \b Range: @ref XMC_USIC_CH_PARITY_MODE_NONE, @ref XMC_USIC_CH_PARITY_MODE_EVEN, \n
235 @ref XMC_USIC_CH_PARITY_MODE_ODD*/
236 } XMC_UART_CH_CONFIG_t;
237
238 /*********************************************************************************************************************
239 * API PROTOTYPES
240 *********************************************************************************************************************/
241
242 #ifdef __cplusplus
243 extern "C" {
244 #endif
245
246 /**
247 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
248 * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1,XMC_UART1_CH0, XMC_UART1_CH1,XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
249 * @param config Constant pointer to UART configuration structure of type @ref XMC_UART_CH_CONFIG_t.
250 * @return XMC_UART_CH_STATUS_t Status of initializing the USIC channel for UART protocol.\n
251 * \b Range: @ref XMC_UART_CH_STATUS_OK if initialization is successful.\n
252 * @ref XMC_UART_CH_STATUS_ERROR if configuration of baudrate failed.
253 *
254 * \par<b>Description</b><br>
255 * Initializes the USIC channel for UART protocol.\n\n
256 * During the initialization, USIC channel is enabled, baudrate is configured with the defined oversampling value
257 * in the intialization structure. If the oversampling value is set to 0 in the structure, the default oversampling of 16
258 * is considered. Sampling point for each symbol is configured at the half of sampling period. Symbol value is decided by the
259 * majority decision among 3 samples.
260 * Word length is configured with the number of data bits. If the value of \a frame_length is 0, then USIC channel frame length
261 * is set to the same value as word length. If \a frame_length is greater than 0, it is set as the USIC channel frame length.
262 * Parity mode is set to the value configured for \a parity_mode.
263 * The USIC channel should be set to UART mode by calling the XMC_UART_CH_Start() API after the initialization.
264 *
265 * \par<b>Related APIs:</b><BR>
266 * XMC_UART_CH_Start(), XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n
267 */
268 void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const config);
269
270 /**
271 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
272 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
273 * @return None
274 *
275 * \par<b>Description</b><br>
276 * Sets the USIC channel operation mode to UART mode.\n\n
277 * CCR register bitfield \a Mode is set to 2(UART mode). This API should be called after configuring
278 * the USIC channel. Transmission and reception can happen only when the UART mode is set.
279 * This is an inline function.
280 *
281 * \par<b>Related APIs:</b><BR>
282 * XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n
283 */
XMC_UART_CH_Start(XMC_USIC_CH_t * const channel)284 __STATIC_INLINE void XMC_UART_CH_Start(XMC_USIC_CH_t *const channel)
285 {
286 channel->CCR = (uint32_t)(((channel->CCR) & (~USIC_CH_CCR_MODE_Msk)) | (uint32_t)XMC_USIC_CH_OPERATING_MODE_UART);
287 }
288
289 /**
290 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
291 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
292 * @return XMC_UART_CH_STATUS_t Status to indicate if the communication channel is stopped successfully.\n
293 * @ref XMC_UART_CH_STATUS_OK if the communication channel is stopped.
294 * @ref XMC_UART_CH_STATUS_BUSY if the communication channel is busy.
295 *
296 * \par<b>Description</b><br>
297 * Stops the UART communication.\n\n
298 * CCR register bitfield \a Mode is reset. This disables the communication.
299 * Before starting the communication again, the channel has to be reconfigured.
300 *
301 * \par<b>Related APIs:</b><BR>
302 * XMC_UART_CH_Init() \n\n\n
303 */
304 XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel);
305
306 /**
307 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
308 * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1 ,XMC_UART1_CH0, XMC_UART1_CH1, XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
309 * @param rate Desired baudrate. \n
310 * \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency\n
311 * and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling)
312 * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data.\n
313 * This can be related to the number of samples for each logic state of the data signal.\n
314 * \b Range: 4 to 32. Value should be chosen based on the protocol used.
315 * @return XMC_UART_CH_STATUS_t Status indicating the baudrate configuration.\n
316 * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured,
317 * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid.
318 *
319 * \par<b>Description:</b><br>
320 * Sets the bus speed in bits per second.\n\n
321 * Derives the values of \a STEP and PDIV to arrive at the optimum realistic speed possible.
322 * \a oversampling is the number of samples to be taken for each symbol of UART protocol.
323 * Default \a oversampling of 16 is considered if the input \a oversampling is less than 4. It is recommended to keep
324 * a minimum oversampling of 4 for UART.
325 *
326 * \par<b>Related APIs:</b><BR>
327 * XMC_UART_CH_Init(), XMC_UART_CH_Stop(), XMC_USIC_CH_GetBaudrate()
328 */
329 XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling);
330
331 /**
332 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
333 * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1 ,XMC_UART1_CH0, XMC_UART1_CH1, XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
334 * @param rate Desired baudrate. \n
335 * \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency\n
336 * and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling)
337 * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data.\n
338 * This can be related to the number of samples for each logic state of the data signal.\n
339 * \b Range: 4 to 32. Value should be chosen based on the protocol used.
340 * @param normal_divider_mode Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter of signal at the cost of frequency selection
341 * @return XMC_UART_CH_STATUS_t Status indicating the baudrate configuration.\n
342 * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured,
343 * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid.
344 *
345 * \par<b>Description:</b><br>
346 * Sets the bus speed in bits per second.\n\n
347 * Derives the values of \a STEP and PDIV to arrive at the optimum realistic speed possible.
348 * \a oversampling is the number of samples to be taken for each symbol of UART protocol.
349 * Default \a oversampling of 16 is considered if the input \a oversampling is less than 4. It is recommended to keep
350 * a minimum oversampling of 4 for UART.
351 *
352 * \par<b>Related APIs:</b><BR>
353 * XMC_UART_CH_Init(), XMC_UART_CH_Stop(), XMC_USIC_CH_GetBaudrate()
354 */
355 XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling, bool normal_divider_mode);
356
357 /**
358 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
359 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
360 * @param data Data to be transmitted. \n
361 * \b Range: 16 bit unsigned data within the range 0 to 65535. Actual size of
362 * data transmitted depends on the configured number of bits for the UART protocol in the register SCTR.
363 * @return None
364 *
365 * \par<b>Description</b><br>
366 * Transmits data over serial communication channel using UART protocol.\n\n
367 * Based on the channel configuration, data is either put to the transmit FIFO or to TBUF register.
368 * Before putting data to TBUF, the API waits for TBUF to finish shifting its contents to shift register.
369 * So user can continuously execute the API without checking for TBUF busy status. Based on the number of
370 * data bits configured, the lower significant bits will be extracted for transmission.
371 *
372 * Note: When FIFO is not configured, the API waits for the TBUF to be available.
373 * This makes the execution a blocking call.
374 *
375 * \par<b>Related APIs:</b><BR>
376 * XMC_UART_CH_GetReceivedData() \n\n\n
377 */
378 void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data);
379
380 /**
381 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
382 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
383 * @return uint16_t Received data over UART communication channel.
384 * \par<b>Description</b><br>
385 * Provides one word of data received over UART communication channel.\n\n
386 * Based on the channel configuration, data is either read from the receive FIFO or RBUF register.
387 * Before returning the value, there is no check for data validity. User should check the appropriate
388 * data receive flags(standard receive/alternative receive/FIFO standard receive/FIFO alternative receive)
389 * before executing the API. Reading from an empty receive FIFO can generate a receive error event.
390 *
391 * \par<b>Related APIs:</b><BR>
392 * XMC_UART_CH_GetStatusFlag(), XMC_UART_CH_Transmit() \n\n\n
393 */
394 uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
395
396 /**
397 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
398 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
399 * @param word_length Data word length. \n
400 * \b Range: minimum= 1, maximum= 16.
401 * @return None
402 *
403 * \par<b>Description</b><br>
404 * Sets the data word length in number of bits.\n\n
405 * Word length can range from 1 to 16. It indicates the number of data bits in a data word.
406 * The value of \a word_length will be decremented by 1 before setting the value to \a SCTR register.
407 * If the UART data bits is more than 16, then the frame length should be set to the actual number of bits and
408 * word length should be configured with the number of bits expected in each transaction. For example, if number of data bits
409 * for UART communication is 20 bits, then the frame length should be set as 20. Word length can be set based on the
410 * transmit and receive handling. If data is stored as 8bit array, then the word length can be set to 8. In this case,
411 * a full message of UART data should be transmitted/ received as 3 data words.
412 *
413 * \par<b>Related APIs:</b><BR>
414 * XMC_UART_CH_SetFrameLength() \n\n\n
415 */
XMC_UART_CH_SetWordLength(XMC_USIC_CH_t * const channel,const uint8_t word_length)416 __STATIC_INLINE void XMC_UART_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length)
417 {
418 XMC_USIC_CH_SetWordLength(channel, word_length);
419 }
420
421 /**
422 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
423 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
424 * @param frame_length Number of data bits in each UART frame. \n
425 * \b Range: minimum= 1, maximum= 64.
426 * @return None
427 *
428 * \par<b>Description</b><br>
429 * Sets the number of data bits for UART communication.\n\n
430 * The frame length is configured by setting the input value to \a SCTR register.
431 * The value of \a frame_length will be decremented by 1, before setting it to the register.
432 * Frame length should not be set to 64 for UART communication.
433 *
434 * \par<b>Related APIs:</b><BR>
435 * XMC_UART_CH_SetWordLength() \n\n\n
436 */
XMC_UART_CH_SetFrameLength(XMC_USIC_CH_t * const channel,const uint8_t frame_length)437 __STATIC_INLINE void XMC_UART_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length)
438 {
439 XMC_USIC_CH_SetFrameLength(channel, frame_length);
440 }
441
442 /**
443 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
444 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
445 * @param event Event bitmasks to enable. Use the type @ref XMC_UART_CH_EVENT_t for naming events. \n
446 * \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST,
447 * @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER,
448 * etc.
449 * @return None
450 *
451 * \par<b>Description</b><br>
452 * Enables interrupt events for UART communication.\n\n
453 * Multiple events can be combined using the bitwise OR operation and configured in one function call.
454 * @ref XMC_UART_CH_EVENT_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
455 * Events are configured by setting bits in the CCR register.
456 * \par<b>Related APIs:</b><BR>
457 * XMC_UART_CH_DisableEvent(), XMC_UART_CH_SetInterruptNodePointer(), XMC_UART_CH_GetStatusFlag() \n\n\n
458 */
459 void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
460
461 /**
462 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
463 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
464 * @param event Bitmask of events to disable. Use the type @ref XMC_UART_CH_EVENT_t for naming events.\n
465 * \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST,
466 * @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER,
467 * etc.
468 * @return None
469 *
470 * \par<b>Description</b><br>
471 * Disables the interrupt events by clearing the bits in CCR register.\n\n
472 * Multiple events can be combined using the bitwise OR operation and configured in one function call.
473 * XMC_UART_CH_EVENT_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
474 *
475 * \par<b>Related APIs:</b><BR>
476 * XMC_UART_CH_ClearStatusFlag(), XMC_UART_CH_EnableEvent() \n\n\n
477 */
478 void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
479
480 /**
481 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
482 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
483 * @param service_request Service request number for generating protocol interrupts.\n
484 * \b Range: 0 to 5.
485 * @return None
486 *
487 * \par<b>Description</b><br>
488 * Sets the interrupt node for UART channel protocol events.\n\n
489 * For all the protocol events enlisted in the enumeration XMC_UART_CH_EVENT_t, one common
490 * interrupt gets generated. The service request connects the interrupt node to the UART
491 * protocol events.
492 * Note: NVIC node should be separately enabled to generate the interrupt.
493 *
494 * \par<b>Related APIs:</b><BR>
495 * XMC_UART_CH_EnableEvent() \n\n\n
496 */
XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t * const channel,const uint8_t service_request)497 __STATIC_INLINE void XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
498 const uint8_t service_request)
499 {
500 XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL,
501 (uint32_t)service_request);
502 }
503
504 /**
505 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
506 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
507 * @param interrupt_node Interrupt node pointer to be configured. \n
508 * \b Range: @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
509 * @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
510 * @param service_request Service request number.\n
511 * \b Range: 0 to 5.
512 * @return None
513 *
514 * \par<b>Description</b><br>
515 * Sets the interrupt node for USIC channel events. \n\n
516 * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
517 * The NVIC node gets linked to the interrupt event by doing so.<br>
518 * Note: NVIC node should be separately enabled to generate the interrupt.
519 *
520 * \par<b>Related APIs:</b><BR>
521 * XMC_UART_CH_EnableEvent() \n\n\n
522 */
XMC_UART_CH_SelectInterruptNodePointer(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INTERRUPT_NODE_POINTER_t interrupt_node,const uint32_t service_request)523 __STATIC_INLINE void XMC_UART_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
524 const XMC_UART_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
525 const uint32_t service_request)
526 {
527 XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
528 (uint32_t)service_request);
529 }
530
531 /**
532 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
533 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
534 * @param service_request_line service request number of the event to be triggered. \n
535 * \b Range: 0 to 5.
536 * @return None
537 *
538 * \par<b>Description</b><br>
539 * Trigger a UART interrupt service request.\n\n
540 * When the UART service request is triggered, the NVIC interrupt associated with it will be
541 * generated if enabled.
542 *
543 * \par<b>Related APIs:</b><BR>
544 * XMC_UART_CH_SelectInterruptNodePointer() \n\n\n
545 */
XMC_UART_CH_TriggerServiceRequest(XMC_USIC_CH_t * const channel,const uint32_t service_request_line)546 __STATIC_INLINE void XMC_UART_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
547 {
548 XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
549 }
550
551 /**
552 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
553 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
554 * @return Status of UART channel events. \n
555 * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for
556 * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE,
557 * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc.
558 *
559 * \par<b>Description</b><br>
560 * Provides the status of UART channel events.\n\n
561 * Status provided by the API represents the status of multiple events at their bit positions. The bitmasks can be
562 * obtained using the enumeration XMC_UART_CH_STATUS_FLAG_t. Event status is obtained by reading
563 * the register PSR_ASCMode.
564 *
565 * \par<b>Related APIs:</b><BR>
566 * XMC_UART_CH_EnableEvent(), XMC_UART_CH_ClearStatusFlag()\n\n\n
567 */
XMC_UART_CH_GetStatusFlag(XMC_USIC_CH_t * const channel)568 __STATIC_INLINE uint32_t XMC_UART_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
569 {
570 return channel->PSR_ASCMode;
571 }
572
573 /**
574 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
575 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
576 * @param flag UART events to be cleared. \n
577 * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for
578 * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE,
579 * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc.
580 * @return None
581 *
582 * \par<b>Description</b><br>
583 * Clears the status of UART channel events.\n\n
584 * Multiple events can be combined using the bitwise OR operation and configured in one function call.
585 * XMC_UART_CH_STATUS_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
586 * Events are cleared by setting the bitmask to the PSCR register.
587 *
588 * \par<b>Related APIs:</b><BR>
589 * XMC_UART_CH_DisableEvent(), XMC_UART_CH_GetStatusFlag()\n\n\n
590 */
XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t * const channel,const uint32_t flag)591 __STATIC_INLINE void XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag)
592 {
593 channel->PSCR = flag;
594 }
595
596 /**
597 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
598 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
599 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
600 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
601 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
602 * @param source Input source select for the input stage. The table provided below maps the decimal value with the input source.
603 * <table><tr><td>0</td><td>DXnA</td></tr><tr><td>1</td><td>DXnB</td></tr><tr><td>2</td><td>DXnC</td></tr><tr><td>3</td><td>DXnD</td></tr>
604 * <tr><td>4</td><td>DXnE</td></tr><tr><td>5</td><td>DXnF</td></tr><tr><td>6</td><td>DXnG</td></tr><tr><td>7</td><td>Always 1</td>
605 * </tr></table>
606 * @return None
607 *
608 * \par<b>Description</b><br>
609 * Sets input soource for the UART communication.\n\n
610 * It is used for configuring the input stage for data reception.
611 * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage.
612 * The API can be used for the input stages DX0, DX3 and DX5.
613 *
614 * \par<b>Related APIs:</b><BR>
615 * XMC_UART_CH_EnableInputInversion() \n\n\n
616 */
XMC_UART_CH_SetInputSource(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INPUT_t input,const uint8_t source)617 __STATIC_INLINE void XMC_UART_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input, const uint8_t source)
618 {
619 channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~(USIC_CH_DX0CR_INSW_Msk|USIC_CH_DX0CR_DSEN_Msk)));
620 XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
621 }
622
623 /**
624 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
625 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
626 * @param pulse_length Length of the zero pulse in number of time quanta. \n
627 * \b Range: 0 to 7.
628 * @return None
629 *
630 * \par<b>Description</b><br>
631 * Sets the length of zero pulse in number of time quanta. Value 0 indicates one time quanta.\n\n
632 * Maximum possible is 8 time quanta with the value configured as 7.\n
633 * The value is set to PCR_ASCMode register.
634 * \par<b>Related APIs:</b><BR>
635 * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n
636 *
637 */
XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t * const channel,const uint8_t pulse_length)638 __STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, const uint8_t pulse_length)
639 {
640 channel->PCR_ASCMode = (uint32_t)(channel->PCR_ASCMode & (~USIC_CH_PCR_ASCMode_PL_Msk)) |
641 ((uint32_t)pulse_length << USIC_CH_PCR_ASCMode_PL_Pos);
642 }
643
644
645 /**
646 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
647 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
648 * @return None
649 *
650 * \par<b>Description</b><br>
651 * Enables the generation of the master clock MCLK.\n\n
652 * \par<b>Related APIs:</b><BR>
653 * XMC_USIC_CH_SetMclkOutputPassiveLevel()\n\n\n
654 *
655 */
XMC_UART_CH_EnableMasterClock(XMC_USIC_CH_t * const channel)656 __STATIC_INLINE void XMC_UART_CH_EnableMasterClock(XMC_USIC_CH_t *const channel)
657 {
658 channel->PCR_ASCMode |= USIC_CH_PCR_ASCMode_MCLK_Msk;
659 }
660
661 /**
662 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
663 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
664 * @return None
665 *
666 * \par<b>Description</b><br>
667 * Disables the generation of the master clock MCLK.\n\n
668 * \par<b>Related APIs:</b><BR>
669 * XMC_USIC_CH_SetMclkOutputPassiveLevel()\n\n\n
670 *
671 */
XMC_UART_CH_DisableMasterClock(XMC_USIC_CH_t * const channel)672 __STATIC_INLINE void XMC_UART_CH_DisableMasterClock(XMC_USIC_CH_t *const channel)
673 {
674 channel->PCR_ASCMode &= (uint32_t)~USIC_CH_PCR_ASCMode_MCLK_Msk;
675 }
676
677 /**
678 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
679 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
680 * @param sample_point Sample point among the number of samples. \n
681 * \b Range: minimum= 0, maximum= \a oversampling (DCTQ).
682 * @return None
683 *
684 * \par<b>Description</b><br>
685 * Sets the sample point among the multiple samples for each UART symbol.\n\n
686 * The sample point is the one sample among number of samples set as oversampling. The value should be less than
687 * the oversampling value. XMC_UART_CH_Init() sets the sample point to the sample at the centre. For
688 * example if the oversampling is 16, then the sample point is set to 9.
689 * \par<b>Related APIs:</b><BR>
690 * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n
691 */
XMC_UART_CH_SetSamplePoint(XMC_USIC_CH_t * const channel,const uint32_t sample_point)692 __STATIC_INLINE void XMC_UART_CH_SetSamplePoint(XMC_USIC_CH_t *const channel, const uint32_t sample_point)
693 {
694 channel->PCR_ASCMode = (uint32_t)((channel->PCR_ASCMode & (uint32_t)(~USIC_CH_PCR_ASCMode_SP_Msk)) |
695 (sample_point << USIC_CH_PCR_ASCMode_SP_Pos));
696 }
697
698 /**
699 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
700 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
701 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
702 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
703 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
704 * @return None
705 *
706 * \par<b>Description</b><br>
707 * Enables input inversion for UART input data signal.\n\n
708 * Polarity of the input source can be changed to provide inverted data input.
709 * \par<b>Related APIs:</b><BR>
710 * XMC_UART_CH_DisableInputInversion()\n\n\n
711 */
XMC_UART_CH_EnableInputInversion(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INPUT_t input)712 __STATIC_INLINE void XMC_UART_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
713 {
714 XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
715 }
716
717 /**
718 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
719 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
720 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
721 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
722 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
723 * @return None
724 *
725 * \par<b>Description</b><br>
726 * Disables input inversion for UART input data signal.\n\n
727 * Resets the input data polarity for the UART input data signal.
728 * \par<b>Related APIs:</b><BR>
729 * XMC_UART_CH_EnableInputInversion()\n\n\n
730 */
XMC_UART_CH_DisableInputInversion(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INPUT_t input)731 __STATIC_INLINE void XMC_UART_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
732 {
733 XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
734 }
735 /**
736 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
737 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
738 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
739 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
740 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
741 * @return None
742 *
743 * \par<b>Description</b><br>
744 * Enables the digital filter for UART input stage.\n\n
745 *
746 * \par<b>Related APIs:</b><BR>
747 * XMC_UART_CH_DisableInputDigitalFilter()\n\n\n
748 */
XMC_UART_CH_EnableInputDigitalFilter(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INPUT_t input)749 __STATIC_INLINE void XMC_UART_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
750 {
751 XMC_USIC_CH_EnableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input);
752 }
753 /**
754 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
755 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
756 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
757 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
758 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
759 * @return None
760 *
761 * \par<b>Description</b><br>
762 * Disables the digital filter for UART input stage.\n\n
763 *
764 * \par<b>Related APIs:</b><BR>
765 * XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
766 */
XMC_UART_CH_DisableInputDigitalFilter(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INPUT_t input)767 __STATIC_INLINE void XMC_UART_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
768 {
769 XMC_USIC_CH_DisableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input);
770 }
771 /**
772 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
773 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
774 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
775 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
776 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
777 * @return None
778 * \par<b>Description</b><br>
779 * Enables synchronous input for the UART input stage.\n\n
780 *
781 * \par<b>Related APIs:</b><BR>
782 * XMC_UART_CH_DisableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
783 */
XMC_UART_CH_EnableInputSync(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INPUT_t input)784 __STATIC_INLINE void XMC_UART_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
785 {
786 XMC_USIC_CH_EnableInputSync(channel, (XMC_USIC_CH_INPUT_t)input);
787 }
788 /**
789 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
790 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
791 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
792 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
793 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
794 * @return None
795 *
796 * \par<b>Description</b><br>
797 * Disables synchronous input for the UART input stage.\n\n
798 *
799 * \par<b>Related APIs:</b><BR>
800 * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
801 */
XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INPUT_t input)802 __STATIC_INLINE void XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
803 {
804 XMC_USIC_CH_DisableInputSync(channel, (XMC_USIC_CH_INPUT_t)input);
805 }
806 /**
807 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
808 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
809 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
810 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
811 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
812 * @param sampling_freq Input sampling frequency. \n
813 * \b Range: @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH, @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER.
814 * @return None
815 *
816 * \par<b>Description</b><br>
817 * Sets the sampling frequency for the UART input stage.\n\n
818 *
819 * \par<b>Related APIs:</b><BR>
820 * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
821 */
XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t * const channel,const XMC_UART_CH_INPUT_t input,const XMC_UART_CH_INPUT_SAMPLING_FREQ_t sampling_freq)822 __STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel,
823 const XMC_UART_CH_INPUT_t input,
824 const XMC_UART_CH_INPUT_SAMPLING_FREQ_t sampling_freq)
825 {
826 XMC_USIC_CH_SetInputSamplingFreq(channel, (XMC_USIC_CH_INPUT_t)input, (XMC_USIC_CH_INPUT_SAMPLING_FREQ_t)sampling_freq);
827 }
828
829 /**
830 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
831 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
832 * @return None
833 *
834 * \par<b>Description</b><br>
835 * Enable data transmission.\n\n
836 * Use this function in combination with XMC_UART_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
837 * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
838 * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
839 *
840 * \par<b>Related APIs:</b><BR>
841 * XMC_UART_CH_DisableDataTransmission()\n\n\n
842 */
XMC_UART_CH_EnableDataTransmission(XMC_USIC_CH_t * const channel)843 __STATIC_INLINE void XMC_UART_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
844 {
845 XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
846 }
847
848 /**
849 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
850 * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
851 * @return None
852 *
853 * \par<b>Description</b><br>
854 * Disable data transmission.\n\n
855 * Use this function in combination with XMC_UART_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
856 * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
857 *
858 * \par<b>Related APIs:</b><BR>
859 * XMC_UART_CH_EnableDataTransmission()\n\n\n
860 */
XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t * const channel)861 __STATIC_INLINE void XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
862 {
863 XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
864 }
865
866 #ifdef __cplusplus
867 }
868 #endif
869
870 /**
871 * @}
872 */
873
874 /**
875 * @}
876 */
877
878 #endif
879
