1 /*
2  * Autogenerated file
3  *
4  * SPDX-License-Identifier: Apache 2.0
5  */
6 
7 #include "gd32vf103xx-afio.h"
8 
9 /* ADC01_IN0 */
10 #define ADC01_IN0_PA0 \
11 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
12 
13 /* ADC01_IN1 */
14 #define ADC01_IN1_PA1 \
15 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
16 
17 /* ADC01_IN10 */
18 #define ADC01_IN10_PC0 \
19 	GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP)
20 
21 /* ADC01_IN11 */
22 #define ADC01_IN11_PC1 \
23 	GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP)
24 
25 /* ADC01_IN12 */
26 #define ADC01_IN12_PC2 \
27 	GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP)
28 
29 /* ADC01_IN13 */
30 #define ADC01_IN13_PC3 \
31 	GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP)
32 
33 /* ADC01_IN14 */
34 #define ADC01_IN14_PC4 \
35 	GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP)
36 
37 /* ADC01_IN15 */
38 #define ADC01_IN15_PC5 \
39 	GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP)
40 
41 /* ADC01_IN2 */
42 #define ADC01_IN2_PA2 \
43 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
44 
45 /* ADC01_IN3 */
46 #define ADC01_IN3_PA3 \
47 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
48 
49 /* ADC01_IN4 */
50 #define ADC01_IN4_PA4 \
51 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
52 
53 /* ADC01_IN5 */
54 #define ADC01_IN5_PA5 \
55 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
56 
57 /* ADC01_IN6 */
58 #define ADC01_IN6_PA6 \
59 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
60 
61 /* ADC01_IN7 */
62 #define ADC01_IN7_PA7 \
63 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
64 
65 /* ADC01_IN8 */
66 #define ADC01_IN8_PB0 \
67 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
68 
69 /* ADC01_IN9 */
70 #define ADC01_IN9_PB1 \
71 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
72 
73 /* ANALOG */
74 #define ANALOG_PA0 \
75 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
76 #define ANALOG_PA1 \
77 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
78 #define ANALOG_PA2 \
79 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
80 #define ANALOG_PA3 \
81 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
82 #define ANALOG_PA4 \
83 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
84 #define ANALOG_PA5 \
85 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
86 #define ANALOG_PA6 \
87 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
88 #define ANALOG_PA7 \
89 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
90 #define ANALOG_PA8 \
91 	GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP)
92 #define ANALOG_PA9 \
93 	GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP)
94 #define ANALOG_PA10 \
95 	GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP)
96 #define ANALOG_PA11 \
97 	GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP)
98 #define ANALOG_PA12 \
99 	GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP)
100 #define ANALOG_PA13 \
101 	GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP)
102 #define ANALOG_PA14 \
103 	GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP)
104 #define ANALOG_PA15 \
105 	GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP)
106 #define ANALOG_PB0 \
107 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
108 #define ANALOG_PB1 \
109 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
110 #define ANALOG_PB2 \
111 	GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP)
112 #define ANALOG_PB3 \
113 	GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP)
114 #define ANALOG_PB4 \
115 	GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP)
116 #define ANALOG_PB5 \
117 	GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP)
118 #define ANALOG_PB6 \
119 	GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP)
120 #define ANALOG_PB7 \
121 	GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP)
122 #define ANALOG_PB8 \
123 	GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP)
124 #define ANALOG_PB9 \
125 	GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP)
126 #define ANALOG_PB10 \
127 	GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP)
128 #define ANALOG_PB11 \
129 	GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP)
130 #define ANALOG_PB12 \
131 	GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP)
132 #define ANALOG_PB13 \
133 	GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP)
134 #define ANALOG_PB14 \
135 	GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP)
136 #define ANALOG_PB15 \
137 	GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP)
138 #define ANALOG_PC0 \
139 	GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP)
140 #define ANALOG_PC1 \
141 	GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP)
142 #define ANALOG_PC2 \
143 	GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP)
144 #define ANALOG_PC3 \
145 	GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP)
146 #define ANALOG_PC4 \
147 	GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP)
148 #define ANALOG_PC5 \
149 	GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP)
150 #define ANALOG_PC6 \
151 	GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP)
152 #define ANALOG_PC7 \
153 	GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP)
154 #define ANALOG_PC8 \
155 	GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP)
156 #define ANALOG_PC9 \
157 	GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP)
158 #define ANALOG_PC10 \
159 	GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP)
160 #define ANALOG_PC11 \
161 	GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP)
162 #define ANALOG_PC12 \
163 	GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP)
164 #define ANALOG_PC13 \
165 	GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP)
166 #define ANALOG_PC14 \
167 	GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP)
168 #define ANALOG_PC15 \
169 	GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP)
170 #define ANALOG_PD0 \
171 	GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP)
172 #define ANALOG_PD1 \
173 	GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP)
174 #define ANALOG_PD2 \
175 	GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP)
176 #define ANALOG_PD3 \
177 	GD32_PINMUX_AFIO('D', 3, ANALOG, NORMP)
178 #define ANALOG_PD4 \
179 	GD32_PINMUX_AFIO('D', 4, ANALOG, NORMP)
180 #define ANALOG_PD5 \
181 	GD32_PINMUX_AFIO('D', 5, ANALOG, NORMP)
182 #define ANALOG_PD6 \
183 	GD32_PINMUX_AFIO('D', 6, ANALOG, NORMP)
184 #define ANALOG_PD7 \
185 	GD32_PINMUX_AFIO('D', 7, ANALOG, NORMP)
186 #define ANALOG_PD8 \
187 	GD32_PINMUX_AFIO('D', 8, ANALOG, NORMP)
188 #define ANALOG_PD9 \
189 	GD32_PINMUX_AFIO('D', 9, ANALOG, NORMP)
190 #define ANALOG_PD10 \
191 	GD32_PINMUX_AFIO('D', 10, ANALOG, NORMP)
192 #define ANALOG_PD11 \
193 	GD32_PINMUX_AFIO('D', 11, ANALOG, NORMP)
194 #define ANALOG_PD12 \
195 	GD32_PINMUX_AFIO('D', 12, ANALOG, NORMP)
196 #define ANALOG_PD13 \
197 	GD32_PINMUX_AFIO('D', 13, ANALOG, NORMP)
198 #define ANALOG_PD14 \
199 	GD32_PINMUX_AFIO('D', 14, ANALOG, NORMP)
200 #define ANALOG_PD15 \
201 	GD32_PINMUX_AFIO('D', 15, ANALOG, NORMP)
202 #define ANALOG_PE0 \
203 	GD32_PINMUX_AFIO('E', 0, ANALOG, NORMP)
204 #define ANALOG_PE1 \
205 	GD32_PINMUX_AFIO('E', 1, ANALOG, NORMP)
206 #define ANALOG_PE2 \
207 	GD32_PINMUX_AFIO('E', 2, ANALOG, NORMP)
208 #define ANALOG_PE3 \
209 	GD32_PINMUX_AFIO('E', 3, ANALOG, NORMP)
210 #define ANALOG_PE4 \
211 	GD32_PINMUX_AFIO('E', 4, ANALOG, NORMP)
212 #define ANALOG_PE5 \
213 	GD32_PINMUX_AFIO('E', 5, ANALOG, NORMP)
214 #define ANALOG_PE6 \
215 	GD32_PINMUX_AFIO('E', 6, ANALOG, NORMP)
216 #define ANALOG_PE7 \
217 	GD32_PINMUX_AFIO('E', 7, ANALOG, NORMP)
218 #define ANALOG_PE8 \
219 	GD32_PINMUX_AFIO('E', 8, ANALOG, NORMP)
220 #define ANALOG_PE9 \
221 	GD32_PINMUX_AFIO('E', 9, ANALOG, NORMP)
222 #define ANALOG_PE10 \
223 	GD32_PINMUX_AFIO('E', 10, ANALOG, NORMP)
224 #define ANALOG_PE11 \
225 	GD32_PINMUX_AFIO('E', 11, ANALOG, NORMP)
226 #define ANALOG_PE12 \
227 	GD32_PINMUX_AFIO('E', 12, ANALOG, NORMP)
228 #define ANALOG_PE13 \
229 	GD32_PINMUX_AFIO('E', 13, ANALOG, NORMP)
230 #define ANALOG_PE14 \
231 	GD32_PINMUX_AFIO('E', 14, ANALOG, NORMP)
232 #define ANALOG_PE15 \
233 	GD32_PINMUX_AFIO('E', 15, ANALOG, NORMP)
234 
235 /* CAN0_RX */
236 #define CAN0_RX_PA11_NORMP \
237 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, CAN0_NORMP)
238 #define CAN0_RX_PB8_PRMP \
239 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, CAN0_PRMP)
240 #define CAN0_RX_PD0_FRMP \
241 	GD32_PINMUX_AFIO('D', 0, GPIO_IN, CAN0_FRMP)
242 
243 /* CAN0_TX */
244 #define CAN0_TX_PA12_NORMP \
245 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, CAN0_NORMP)
246 #define CAN0_TX_PB9_PRMP \
247 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, CAN0_PRMP)
248 #define CAN0_TX_PD1_FRMP \
249 	GD32_PINMUX_AFIO('D', 1, ALTERNATE, CAN0_FRMP)
250 
251 /* CAN1_RX */
252 #define CAN1_RX_PB12_NORMP \
253 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, CAN1_NORMP)
254 #define CAN1_RX_PB5_RMP \
255 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, CAN1_RMP)
256 
257 /* CAN1_TX */
258 #define CAN1_TX_PB13_NORMP \
259 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, CAN1_NORMP)
260 #define CAN1_TX_PB6_RMP \
261 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, CAN1_RMP)
262 
263 /* CK_OUT0 */
264 #define CK_OUT0_PA8 \
265 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
266 
267 /* DAC_OUT0 */
268 #define DAC_OUT0_PA4 \
269 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
270 
271 /* DAC_OUT1 */
272 #define DAC_OUT1_PA5 \
273 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
274 
275 /* EXMC_A16 */
276 #define EXMC_A16_PD11 \
277 	GD32_PINMUX_AFIO('D', 11, ALTERNATE, NORMP)
278 
279 /* EXMC_A17 */
280 #define EXMC_A17_PD12 \
281 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, NORMP)
282 
283 /* EXMC_A18 */
284 #define EXMC_A18_PD13 \
285 	GD32_PINMUX_AFIO('D', 13, ALTERNATE, NORMP)
286 
287 /* EXMC_A19 */
288 #define EXMC_A19_PE3 \
289 	GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP)
290 
291 /* EXMC_A20 */
292 #define EXMC_A20_PE4 \
293 	GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP)
294 
295 /* EXMC_A21 */
296 #define EXMC_A21_PE5 \
297 	GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP)
298 
299 /* EXMC_A22 */
300 #define EXMC_A22_PE6 \
301 	GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP)
302 
303 /* EXMC_A23 */
304 #define EXMC_A23_PE2 \
305 	GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP)
306 
307 /* EXMC_D0 */
308 #define EXMC_D0_PD14 \
309 	GD32_PINMUX_AFIO('D', 14, ALTERNATE, NORMP)
310 
311 /* EXMC_D1 */
312 #define EXMC_D1_PD15 \
313 	GD32_PINMUX_AFIO('D', 15, ALTERNATE, NORMP)
314 
315 /* EXMC_D10 */
316 #define EXMC_D10_PE13 \
317 	GD32_PINMUX_AFIO('E', 13, ALTERNATE, NORMP)
318 
319 /* EXMC_D11 */
320 #define EXMC_D11_PE14 \
321 	GD32_PINMUX_AFIO('E', 14, ALTERNATE, NORMP)
322 
323 /* EXMC_D12 */
324 #define EXMC_D12_PE15 \
325 	GD32_PINMUX_AFIO('E', 15, ALTERNATE, NORMP)
326 
327 /* EXMC_D13 */
328 #define EXMC_D13_PD8 \
329 	GD32_PINMUX_AFIO('D', 8, ALTERNATE, NORMP)
330 
331 /* EXMC_D14 */
332 #define EXMC_D14_PD9 \
333 	GD32_PINMUX_AFIO('D', 9, ALTERNATE, NORMP)
334 
335 /* EXMC_D15 */
336 #define EXMC_D15_PD10 \
337 	GD32_PINMUX_AFIO('D', 10, ALTERNATE, NORMP)
338 
339 /* EXMC_D2 */
340 #define EXMC_D2_PD0 \
341 	GD32_PINMUX_AFIO('D', 0, ALTERNATE, NORMP)
342 
343 /* EXMC_D3 */
344 #define EXMC_D3_PD1 \
345 	GD32_PINMUX_AFIO('D', 1, ALTERNATE, NORMP)
346 
347 /* EXMC_D4 */
348 #define EXMC_D4_PE7 \
349 	GD32_PINMUX_AFIO('E', 7, ALTERNATE, NORMP)
350 
351 /* EXMC_D5 */
352 #define EXMC_D5_PE8 \
353 	GD32_PINMUX_AFIO('E', 8, ALTERNATE, NORMP)
354 
355 /* EXMC_D6 */
356 #define EXMC_D6_PE9 \
357 	GD32_PINMUX_AFIO('E', 9, ALTERNATE, NORMP)
358 
359 /* EXMC_D7 */
360 #define EXMC_D7_PE10 \
361 	GD32_PINMUX_AFIO('E', 10, ALTERNATE, NORMP)
362 
363 /* EXMC_D8 */
364 #define EXMC_D8_PE11 \
365 	GD32_PINMUX_AFIO('E', 11, ALTERNATE, NORMP)
366 
367 /* EXMC_D9 */
368 #define EXMC_D9_PE12 \
369 	GD32_PINMUX_AFIO('E', 12, ALTERNATE, NORMP)
370 
371 /* EXMC_NADV */
372 #define EXMC_NADV_PB7 \
373 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, NORMP)
374 
375 /* EXMC_NBL0 */
376 #define EXMC_NBL0_PE0 \
377 	GD32_PINMUX_AFIO('E', 0, ALTERNATE, NORMP)
378 
379 /* EXMC_NBL1 */
380 #define EXMC_NBL1_PE1 \
381 	GD32_PINMUX_AFIO('E', 1, ALTERNATE, NORMP)
382 
383 /* EXMC_NE0 */
384 #define EXMC_NE0_PD7 \
385 	GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP)
386 
387 /* EXMC_NOE */
388 #define EXMC_NOE_PD4 \
389 	GD32_PINMUX_AFIO('D', 4, ALTERNATE, NORMP)
390 
391 /* EXMC_NWAIT */
392 #define EXMC_NWAIT_PD6 \
393 	GD32_PINMUX_AFIO('D', 6, GPIO_IN, NORMP)
394 
395 /* EXMC_NWE */
396 #define EXMC_NWE_PD5 \
397 	GD32_PINMUX_AFIO('D', 5, ALTERNATE, NORMP)
398 
399 /* I2C0_SCL */
400 #define I2C0_SCL_PB6_NORMP \
401 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP)
402 #define I2C0_SCL_PB8_RMP \
403 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP)
404 
405 /* I2C0_SDA */
406 #define I2C0_SDA_PB7_NORMP \
407 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP)
408 #define I2C0_SDA_PB9_RMP \
409 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP)
410 
411 /* I2C0_SMBA */
412 #define I2C0_SMBA_PB5 \
413 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP)
414 
415 /* I2C1_SCL */
416 #define I2C1_SCL_PB10 \
417 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP)
418 
419 /* I2C1_SDA */
420 #define I2C1_SDA_PB11 \
421 	GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP)
422 
423 /* I2C1_SMBA */
424 #define I2C1_SMBA_PB12 \
425 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
426 
427 /* I2S1_CK */
428 #define I2S1_CK_PB13_INP \
429 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP)
430 #define I2S1_CK_PB13_OUT \
431 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
432 
433 /* I2S1_MCK */
434 #define I2S1_MCK_PC6 \
435 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP)
436 
437 /* I2S1_SD */
438 #define I2S1_SD_PB15_INP \
439 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
440 #define I2S1_SD_PB15_OUT \
441 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
442 
443 /* I2S1_WS */
444 #define I2S1_WS_PB12_INP \
445 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
446 #define I2S1_WS_PB12_OUT \
447 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
448 
449 /* I2S2_CK */
450 #define I2S2_CK_PB3_INP_NORMP \
451 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, I2S2_NORMP)
452 #define I2S2_CK_PB3_OUT_NORMP \
453 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP)
454 #define I2S2_CK_PC10_INP_RMP \
455 	GD32_PINMUX_AFIO('C', 10, GPIO_IN, I2S2_RMP)
456 #define I2S2_CK_PC10_OUT_RMP \
457 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP)
458 
459 /* I2S2_MCK */
460 #define I2S2_MCK_PC7 \
461 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP)
462 
463 /* I2S2_SD */
464 #define I2S2_SD_PB5_INP_NORMP \
465 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP)
466 #define I2S2_SD_PB5_OUT_NORMP \
467 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP)
468 #define I2S2_SD_PC12_INP_RMP \
469 	GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP)
470 #define I2S2_SD_PC12_OUT_RMP \
471 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP)
472 
473 /* I2S2_WS */
474 #define I2S2_WS_PA15_INP_NORMP \
475 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP)
476 #define I2S2_WS_PA15_OUT_NORMP \
477 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP)
478 #define I2S2_WS_PA4_INP_RMP \
479 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP)
480 #define I2S2_WS_PA4_OUT_RMP \
481 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP)
482 
483 /* SPI0_MISO */
484 #define SPI0_MISO_PA6_INP_NORMP \
485 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP)
486 #define SPI0_MISO_PA6_OUT_NORMP \
487 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP)
488 #define SPI0_MISO_PB4_INP_RMP \
489 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP)
490 #define SPI0_MISO_PB4_OUT_RMP \
491 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP)
492 
493 /* SPI0_MOSI */
494 #define SPI0_MOSI_PA7_INP_NORMP \
495 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP)
496 #define SPI0_MOSI_PA7_OUT_NORMP \
497 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP)
498 #define SPI0_MOSI_PB5_INP_RMP \
499 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP)
500 #define SPI0_MOSI_PB5_OUT_RMP \
501 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP)
502 
503 /* SPI0_NSS */
504 #define SPI0_NSS_PA4_INP_NORMP \
505 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP)
506 #define SPI0_NSS_PA4_OUT_NORMP \
507 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP)
508 #define SPI0_NSS_PA15_INP_RMP \
509 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP)
510 #define SPI0_NSS_PA15_OUT_RMP \
511 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP)
512 
513 /* SPI0_SCK */
514 #define SPI0_SCK_PA5_INP_NORMP \
515 	GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP)
516 #define SPI0_SCK_PA5_OUT_NORMP \
517 	GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP)
518 #define SPI0_SCK_PB3_INP_RMP \
519 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP)
520 #define SPI0_SCK_PB3_OUT_RMP \
521 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP)
522 
523 /* SPI1_MISO */
524 #define SPI1_MISO_PB14_INP \
525 	GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP)
526 #define SPI1_MISO_PB14_OUT \
527 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP)
528 
529 /* SPI1_MOSI */
530 #define SPI1_MOSI_PB15_INP \
531 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
532 #define SPI1_MOSI_PB15_OUT \
533 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
534 
535 /* SPI1_NSS */
536 #define SPI1_NSS_PB12_INP \
537 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
538 #define SPI1_NSS_PB12_OUT \
539 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
540 
541 /* SPI1_SCK */
542 #define SPI1_SCK_PB13_INP \
543 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP)
544 #define SPI1_SCK_PB13_OUT \
545 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
546 
547 /* SPI2_MISO */
548 #define SPI2_MISO_PB4_INP_NORMP \
549 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP)
550 #define SPI2_MISO_PB4_OUT_NORMP \
551 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP)
552 #define SPI2_MISO_PC11_INP_RMP \
553 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP)
554 #define SPI2_MISO_PC11_OUT_RMP \
555 	GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP)
556 
557 /* SPI2_MOSI */
558 #define SPI2_MOSI_PB5_INP_NORMP \
559 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP)
560 #define SPI2_MOSI_PB5_OUT_NORMP \
561 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP)
562 #define SPI2_MOSI_PC12_INP_RMP \
563 	GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP)
564 #define SPI2_MOSI_PC12_OUT_RMP \
565 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP)
566 
567 /* SPI2_NSS */
568 #define SPI2_NSS_PA15_INP_NORMP \
569 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP)
570 #define SPI2_NSS_PA15_OUT_NORMP \
571 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP)
572 #define SPI2_NSS_PA4_INP_RMP \
573 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP)
574 #define SPI2_NSS_PA4_OUT_RMP \
575 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP)
576 
577 /* SPI2_SCK */
578 #define SPI2_SCK_PB3_INP_NORMP \
579 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP)
580 #define SPI2_SCK_PB3_OUT_NORMP \
581 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP)
582 #define SPI2_SCK_PC10_INP_RMP \
583 	GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP)
584 #define SPI2_SCK_PC10_OUT_RMP \
585 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP)
586 
587 /* TAMPER */
588 #define TAMPER_PC13 \
589 	GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP)
590 
591 /* TIMER0_BRKIN */
592 #define TIMER0_BRKIN_PB12 \
593 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
594 
595 /* TIMER0_CH0 */
596 #define TIMER0_CH0_PA8_INP_NORMP \
597 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP)
598 #define TIMER0_CH0_PA8_OUT_NORMP \
599 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP)
600 #define TIMER0_CH0_PA8_INP_PRMP \
601 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP)
602 #define TIMER0_CH0_PA8_OUT_PRMP \
603 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP)
604 #define TIMER0_CH0_PE9_INP_FRMP \
605 	GD32_PINMUX_AFIO('E', 9, GPIO_IN, TIMER0_FRMP)
606 #define TIMER0_CH0_PE9_OUT_FRMP \
607 	GD32_PINMUX_AFIO('E', 9, ALTERNATE, TIMER0_FRMP)
608 
609 /* TIMER0_CH0_ON */
610 #define TIMER0_CH0_ON_PB13_NORMP \
611 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP)
612 #define TIMER0_CH0_ON_PA7_PRMP \
613 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP)
614 #define TIMER0_CH0_ON_PE8_FRMP \
615 	GD32_PINMUX_AFIO('E', 8, ALTERNATE, TIMER0_FRMP)
616 
617 /* TIMER0_CH1 */
618 #define TIMER0_CH1_PA9_INP_NORMP \
619 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP)
620 #define TIMER0_CH1_PA9_OUT_NORMP \
621 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP)
622 #define TIMER0_CH1_PA9_INP_PRMP \
623 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP)
624 #define TIMER0_CH1_PA9_OUT_PRMP \
625 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP)
626 #define TIMER0_CH1_PE11_INP_FRMP \
627 	GD32_PINMUX_AFIO('E', 11, GPIO_IN, TIMER0_FRMP)
628 #define TIMER0_CH1_PE11_OUT_FRMP \
629 	GD32_PINMUX_AFIO('E', 11, ALTERNATE, TIMER0_FRMP)
630 
631 /* TIMER0_CH1_ON */
632 #define TIMER0_CH1_ON_PB14_NORMP \
633 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP)
634 #define TIMER0_CH1_ON_PB0_PRMP \
635 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP)
636 #define TIMER0_CH1_ON_PE10_FRMP \
637 	GD32_PINMUX_AFIO('E', 10, ALTERNATE, TIMER0_FRMP)
638 
639 /* TIMER0_CH2 */
640 #define TIMER0_CH2_PA10_INP_NORMP \
641 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP)
642 #define TIMER0_CH2_PA10_OUT_NORMP \
643 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP)
644 #define TIMER0_CH2_PA10_INP_PRMP \
645 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP)
646 #define TIMER0_CH2_PA10_OUT_PRMP \
647 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP)
648 #define TIMER0_CH2_PE13_INP_FRMP \
649 	GD32_PINMUX_AFIO('E', 13, GPIO_IN, TIMER0_FRMP)
650 #define TIMER0_CH2_PE13_OUT_FRMP \
651 	GD32_PINMUX_AFIO('E', 13, ALTERNATE, TIMER0_FRMP)
652 
653 /* TIMER0_CH2_ON */
654 #define TIMER0_CH2_ON_PB15_NORMP \
655 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP)
656 #define TIMER0_CH2_ON_PB1_PRMP \
657 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP)
658 #define TIMER0_CH2_ON_PE12_FRMP \
659 	GD32_PINMUX_AFIO('E', 12, ALTERNATE, TIMER0_FRMP)
660 
661 /* TIMER0_CH3 */
662 #define TIMER0_CH3_PA11_INP_NORMP \
663 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP)
664 #define TIMER0_CH3_PA11_OUT_NORMP \
665 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP)
666 #define TIMER0_CH3_PA11_INP_PRMP \
667 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP)
668 #define TIMER0_CH3_PA11_OUT_PRMP \
669 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP)
670 #define TIMER0_CH3_PE14_INP_FRMP \
671 	GD32_PINMUX_AFIO('E', 14, GPIO_IN, TIMER0_FRMP)
672 #define TIMER0_CH3_PE14_OUT_FRMP \
673 	GD32_PINMUX_AFIO('E', 14, ALTERNATE, TIMER0_FRMP)
674 
675 /* TIMER0_ETI */
676 #define TIMER0_ETI_PA12_NORMP \
677 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP)
678 #define TIMER0_ETI_PA12_PRMP \
679 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP)
680 #define TIMER0_ETI_PE7_FRMP \
681 	GD32_PINMUX_AFIO('E', 7, GPIO_IN, TIMER0_FRMP)
682 
683 /* TIMER1_CH0 */
684 #define TIMER1_CH0_PA0_INP_NORMP \
685 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, TIMER1_NORMP)
686 #define TIMER1_CH0_PA0_OUT_NORMP \
687 	GD32_PINMUX_AFIO('A', 0, ALTERNATE, TIMER1_NORMP)
688 #define TIMER1_CH0_PA0_INP_PRMP2 \
689 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, TIMER1_PRMP2)
690 #define TIMER1_CH0_PA0_OUT_PRMP2 \
691 	GD32_PINMUX_AFIO('A', 0, ALTERNATE, TIMER1_PRMP2)
692 #define TIMER1_CH0_PA15_INP_PRMP1 \
693 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, TIMER1_PRMP1)
694 #define TIMER1_CH0_PA15_OUT_PRMP1 \
695 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, TIMER1_PRMP1)
696 #define TIMER1_CH0_PA15_INP_FRMP \
697 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, TIMER1_FRMP)
698 #define TIMER1_CH0_PA15_OUT_FRMP \
699 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, TIMER1_FRMP)
700 
701 /* TIMER1_CH1 */
702 #define TIMER1_CH1_PA1_INP_NORMP \
703 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP)
704 #define TIMER1_CH1_PA1_OUT_NORMP \
705 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP)
706 #define TIMER1_CH1_PA1_INP_PRMP2 \
707 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2)
708 #define TIMER1_CH1_PA1_OUT_PRMP2 \
709 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2)
710 #define TIMER1_CH1_PB3_INP_PRMP1 \
711 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1)
712 #define TIMER1_CH1_PB3_OUT_PRMP1 \
713 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1)
714 #define TIMER1_CH1_PB3_INP_FRMP \
715 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP)
716 #define TIMER1_CH1_PB3_OUT_FRMP \
717 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP)
718 
719 /* TIMER1_CH2 */
720 #define TIMER1_CH2_PA2_INP_NORMP \
721 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP)
722 #define TIMER1_CH2_PA2_OUT_NORMP \
723 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP)
724 #define TIMER1_CH2_PA2_INP_PRMP1 \
725 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1)
726 #define TIMER1_CH2_PA2_OUT_PRMP1 \
727 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1)
728 #define TIMER1_CH2_PB10_INP_PRMP2 \
729 	GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2)
730 #define TIMER1_CH2_PB10_OUT_PRMP2 \
731 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2)
732 #define TIMER1_CH2_PB10_INP_FRMP \
733 	GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP)
734 #define TIMER1_CH2_PB10_OUT_FRMP \
735 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP)
736 
737 /* TIMER1_CH3 */
738 #define TIMER1_CH3_PA3_INP_NORMP \
739 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP)
740 #define TIMER1_CH3_PA3_OUT_NORMP \
741 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP)
742 #define TIMER1_CH3_PA3_INP_PRMP1 \
743 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1)
744 #define TIMER1_CH3_PA3_OUT_PRMP1 \
745 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1)
746 #define TIMER1_CH3_PB11_INP_PRMP2 \
747 	GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2)
748 #define TIMER1_CH3_PB11_OUT_PRMP2 \
749 	GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2)
750 #define TIMER1_CH3_PB11_INP_FRMP \
751 	GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP)
752 #define TIMER1_CH3_PB11_OUT_FRMP \
753 	GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP)
754 
755 /* TIMER2_CH0 */
756 #define TIMER2_CH0_PA6_INP_NORMP \
757 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP)
758 #define TIMER2_CH0_PA6_OUT_NORMP \
759 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP)
760 #define TIMER2_CH0_PB4_INP_PRMP \
761 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP)
762 #define TIMER2_CH0_PB4_OUT_PRMP \
763 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP)
764 #define TIMER2_CH0_PC6_INP_FRMP \
765 	GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP)
766 #define TIMER2_CH0_PC6_OUT_FRMP \
767 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP)
768 
769 /* TIMER2_CH1 */
770 #define TIMER2_CH1_PA7_INP_NORMP \
771 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP)
772 #define TIMER2_CH1_PA7_OUT_NORMP \
773 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP)
774 #define TIMER2_CH1_PB5_INP_PRMP \
775 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP)
776 #define TIMER2_CH1_PB5_OUT_PRMP \
777 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP)
778 #define TIMER2_CH1_PC7_INP_FRMP \
779 	GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP)
780 #define TIMER2_CH1_PC7_OUT_FRMP \
781 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP)
782 
783 /* TIMER2_CH2 */
784 #define TIMER2_CH2_PB0_INP_NORMP \
785 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP)
786 #define TIMER2_CH2_PB0_OUT_NORMP \
787 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP)
788 #define TIMER2_CH2_PB0_INP_PRMP \
789 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP)
790 #define TIMER2_CH2_PB0_OUT_PRMP \
791 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP)
792 #define TIMER2_CH2_PC8_INP_FRMP \
793 	GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP)
794 #define TIMER2_CH2_PC8_OUT_FRMP \
795 	GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP)
796 
797 /* TIMER2_CH3 */
798 #define TIMER2_CH3_PB1_INP_NORMP \
799 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP)
800 #define TIMER2_CH3_PB1_OUT_NORMP \
801 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP)
802 #define TIMER2_CH3_PB1_INP_PRMP \
803 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP)
804 #define TIMER2_CH3_PB1_OUT_PRMP \
805 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP)
806 #define TIMER2_CH3_PC9_INP_FRMP \
807 	GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP)
808 #define TIMER2_CH3_PC9_OUT_FRMP \
809 	GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP)
810 
811 /* TIMER2_ETI */
812 #define TIMER2_ETI_PD2 \
813 	GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP)
814 
815 /* TIMER3_CH0 */
816 #define TIMER3_CH0_PB6_INP_NORMP \
817 	GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP)
818 #define TIMER3_CH0_PB6_OUT_NORMP \
819 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP)
820 #define TIMER3_CH0_PD12_INP_RMP \
821 	GD32_PINMUX_AFIO('D', 12, GPIO_IN, TIMER3_RMP)
822 #define TIMER3_CH0_PD12_OUT_RMP \
823 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, TIMER3_RMP)
824 
825 /* TIMER3_CH1 */
826 #define TIMER3_CH1_PB7_INP_NORMP \
827 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP)
828 #define TIMER3_CH1_PB7_OUT_NORMP \
829 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP)
830 #define TIMER3_CH1_PD13_INP_RMP \
831 	GD32_PINMUX_AFIO('D', 13, GPIO_IN, TIMER3_RMP)
832 #define TIMER3_CH1_PD13_OUT_RMP \
833 	GD32_PINMUX_AFIO('D', 13, ALTERNATE, TIMER3_RMP)
834 
835 /* TIMER3_CH2 */
836 #define TIMER3_CH2_PB8_INP_NORMP \
837 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP)
838 #define TIMER3_CH2_PB8_OUT_NORMP \
839 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP)
840 #define TIMER3_CH2_PD14_INP_RMP \
841 	GD32_PINMUX_AFIO('D', 14, GPIO_IN, TIMER3_RMP)
842 #define TIMER3_CH2_PD14_OUT_RMP \
843 	GD32_PINMUX_AFIO('D', 14, ALTERNATE, TIMER3_RMP)
844 
845 /* TIMER3_CH3 */
846 #define TIMER3_CH3_PB9_INP_NORMP \
847 	GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP)
848 #define TIMER3_CH3_PB9_OUT_NORMP \
849 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP)
850 #define TIMER3_CH3_PD15_INP_RMP \
851 	GD32_PINMUX_AFIO('D', 15, GPIO_IN, TIMER3_RMP)
852 #define TIMER3_CH3_PD15_OUT_RMP \
853 	GD32_PINMUX_AFIO('D', 15, ALTERNATE, TIMER3_RMP)
854 
855 /* TIMER3_ETI */
856 #define TIMER3_ETI_PE0 \
857 	GD32_PINMUX_AFIO('E', 0, GPIO_IN, NORMP)
858 
859 /* TIMER4_CH1 */
860 #define TIMER4_CH1_PA1_INP \
861 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP)
862 #define TIMER4_CH1_PA1_OUT \
863 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP)
864 
865 /* TIMER4_CH2 */
866 #define TIMER4_CH2_PA2_INP \
867 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP)
868 #define TIMER4_CH2_PA2_OUT \
869 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP)
870 
871 /* TIMER4_CH3 */
872 #define TIMER4_CH3_PA3_INP \
873 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP)
874 #define TIMER4_CH3_PA3_OUT \
875 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP)
876 
877 /* UART3_RX */
878 #define UART3_RX_PC11 \
879 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP)
880 
881 /* UART3_TX */
882 #define UART3_TX_PC10 \
883 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP)
884 
885 /* UART4_RX */
886 #define UART4_RX_PD2 \
887 	GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP)
888 
889 /* UART4_TX */
890 #define UART4_TX_PC12 \
891 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP)
892 
893 /* USART0_CK */
894 #define USART0_CK_PA8 \
895 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
896 
897 /* USART0_CTS */
898 #define USART0_CTS_PA11 \
899 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
900 
901 /* USART0_RTS */
902 #define USART0_RTS_PA12 \
903 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
904 
905 /* USART0_RX */
906 #define USART0_RX_PA10_NORMP \
907 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP)
908 #define USART0_RX_PB7_RMP \
909 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP)
910 
911 /* USART0_TX */
912 #define USART0_TX_PA9_NORMP \
913 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP)
914 #define USART0_TX_PB6_RMP \
915 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP)
916 
917 /* USART1_CK */
918 #define USART1_CK_PA4_NORMP \
919 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP)
920 #define USART1_CK_PD7_RMP \
921 	GD32_PINMUX_AFIO('D', 7, ALTERNATE, USART1_RMP)
922 
923 /* USART1_CTS */
924 #define USART1_CTS_PA0_NORMP \
925 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP)
926 #define USART1_CTS_PD3_RMP \
927 	GD32_PINMUX_AFIO('D', 3, GPIO_IN, USART1_RMP)
928 
929 /* USART1_RTS */
930 #define USART1_RTS_PA1_NORMP \
931 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP)
932 #define USART1_RTS_PD4_RMP \
933 	GD32_PINMUX_AFIO('D', 4, ALTERNATE, USART1_RMP)
934 
935 /* USART1_RX */
936 #define USART1_RX_PA3_NORMP \
937 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP)
938 #define USART1_RX_PD6_RMP \
939 	GD32_PINMUX_AFIO('D', 6, GPIO_IN, USART1_RMP)
940 
941 /* USART1_TX */
942 #define USART1_TX_PA2_NORMP \
943 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP)
944 #define USART1_TX_PD5_RMP \
945 	GD32_PINMUX_AFIO('D', 5, ALTERNATE, USART1_RMP)
946 
947 /* USART2_CK */
948 #define USART2_CK_PB12_NORMP \
949 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP)
950 #define USART2_CK_PC12_PRMP \
951 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP)
952 #define USART2_CK_PD10_FRMP \
953 	GD32_PINMUX_AFIO('D', 10, ALTERNATE, USART2_FRMP)
954 
955 /* USART2_CTS */
956 #define USART2_CTS_PB13_NORMP \
957 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP)
958 #define USART2_CTS_PB13_PRMP \
959 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP)
960 #define USART2_CTS_PD11_FRMP \
961 	GD32_PINMUX_AFIO('D', 11, GPIO_IN, USART2_FRMP)
962 
963 /* USART2_RTS */
964 #define USART2_RTS_PB14_NORMP \
965 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP)
966 #define USART2_RTS_PB14_PRMP \
967 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP)
968 #define USART2_RTS_PD12_FRMP \
969 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, USART2_FRMP)
970 
971 /* USART2_RX */
972 #define USART2_RX_PB11_NORMP \
973 	GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP)
974 #define USART2_RX_PC11_PRMP \
975 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP)
976 #define USART2_RX_PD9_FRMP \
977 	GD32_PINMUX_AFIO('D', 9, GPIO_IN, USART2_FRMP)
978 
979 /* USART2_TX */
980 #define USART2_TX_PB10_NORMP \
981 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP)
982 #define USART2_TX_PC10_PRMP \
983 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP)
984 #define USART2_TX_PD8_FRMP \
985 	GD32_PINMUX_AFIO('D', 8, ALTERNATE, USART2_FRMP)
986 
987 /* USBFS_DM */
988 #define USBFS_DM_PA11_INP \
989 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
990 #define USBFS_DM_PA11_OUT \
991 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP)
992 
993 /* USBFS_DP */
994 #define USBFS_DP_PA12_INP \
995 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP)
996 #define USBFS_DP_PA12_OUT \
997 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
998 
999 /* USBFS_ID */
1000 #define USBFS_ID_PA10_INP \
1001 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP)
1002 #define USBFS_ID_PA10_OUT \
1003 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP)
1004 
1005 /* USBFS_SOF */
1006 #define USBFS_SOF_PA8 \
1007 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
1008 
1009 /* USBFS_VBUS */
1010 #define USBFS_VBUS_PA9 \
1011 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP)
1012 
1013 /* WKUP */
1014 #define WKUP_PA0 \
1015 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
1016