1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32vf103xx-afio.h" 8 9 /* ADC01_IN0 */ 10 #define ADC01_IN0_PA0 \ 11 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 12 13 /* ADC01_IN1 */ 14 #define ADC01_IN1_PA1 \ 15 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 16 17 /* ADC01_IN2 */ 18 #define ADC01_IN2_PA2 \ 19 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 20 21 /* ADC01_IN3 */ 22 #define ADC01_IN3_PA3 \ 23 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 24 25 /* ADC01_IN4 */ 26 #define ADC01_IN4_PA4 \ 27 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 28 29 /* ADC01_IN5 */ 30 #define ADC01_IN5_PA5 \ 31 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 32 33 /* ADC01_IN6 */ 34 #define ADC01_IN6_PA6 \ 35 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 36 37 /* ADC01_IN7 */ 38 #define ADC01_IN7_PA7 \ 39 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 40 41 /* ADC01_IN8 */ 42 #define ADC01_IN8_PB0 \ 43 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 44 45 /* ADC01_IN9 */ 46 #define ADC01_IN9_PB1 \ 47 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 48 49 /* ANALOG */ 50 #define ANALOG_PA0 \ 51 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 52 #define ANALOG_PA1 \ 53 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 54 #define ANALOG_PA2 \ 55 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 56 #define ANALOG_PA3 \ 57 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 58 #define ANALOG_PA4 \ 59 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 60 #define ANALOG_PA5 \ 61 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 62 #define ANALOG_PA6 \ 63 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 64 #define ANALOG_PA7 \ 65 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 66 #define ANALOG_PA8 \ 67 GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) 68 #define ANALOG_PA9 \ 69 GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) 70 #define ANALOG_PA10 \ 71 GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) 72 #define ANALOG_PA11 \ 73 GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) 74 #define ANALOG_PA12 \ 75 GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) 76 #define ANALOG_PA13 \ 77 GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) 78 #define ANALOG_PA14 \ 79 GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) 80 #define ANALOG_PA15 \ 81 GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) 82 #define ANALOG_PB0 \ 83 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 84 #define ANALOG_PB1 \ 85 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 86 #define ANALOG_PB2 \ 87 GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) 88 #define ANALOG_PB3 \ 89 GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) 90 #define ANALOG_PB4 \ 91 GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) 92 #define ANALOG_PB5 \ 93 GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) 94 #define ANALOG_PB6 \ 95 GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) 96 #define ANALOG_PB7 \ 97 GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) 98 #define ANALOG_PD0 \ 99 GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) 100 #define ANALOG_PD1 \ 101 GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) 102 103 /* CAN0_RX */ 104 #define CAN0_RX_PA11_NORMP \ 105 GD32_PINMUX_AFIO('A', 11, GPIO_IN, CAN0_NORMP) 106 #define CAN0_RX_PD0_FRMP \ 107 GD32_PINMUX_AFIO('D', 0, GPIO_IN, CAN0_FRMP) 108 109 /* CAN0_TX */ 110 #define CAN0_TX_PA12_NORMP \ 111 GD32_PINMUX_AFIO('A', 12, ALTERNATE, CAN0_NORMP) 112 #define CAN0_TX_PD1_FRMP \ 113 GD32_PINMUX_AFIO('D', 1, ALTERNATE, CAN0_FRMP) 114 115 /* CAN1_RX */ 116 #define CAN1_RX_PB5_RMP \ 117 GD32_PINMUX_AFIO('B', 5, GPIO_IN, CAN1_RMP) 118 119 /* CAN1_TX */ 120 #define CAN1_TX_PB6_RMP \ 121 GD32_PINMUX_AFIO('B', 6, ALTERNATE, CAN1_RMP) 122 123 /* CK_OUT0 */ 124 #define CK_OUT0_PA8 \ 125 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 126 127 /* DAC_OUT0 */ 128 #define DAC_OUT0_PA4 \ 129 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 130 131 /* DAC_OUT1 */ 132 #define DAC_OUT1_PA5 \ 133 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 134 135 /* I2C0_SCL */ 136 #define I2C0_SCL_PB6_NORMP \ 137 GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) 138 139 /* I2C0_SDA */ 140 #define I2C0_SDA_PB7_NORMP \ 141 GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) 142 143 /* I2C0_SMBA */ 144 #define I2C0_SMBA_PB5 \ 145 GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) 146 147 /* I2S2_CK */ 148 #define I2S2_CK_PB3_INP_NORMP \ 149 GD32_PINMUX_AFIO('B', 3, GPIO_IN, I2S2_NORMP) 150 #define I2S2_CK_PB3_OUT_NORMP \ 151 GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) 152 153 /* I2S2_SD */ 154 #define I2S2_SD_PB5_INP_NORMP \ 155 GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) 156 #define I2S2_SD_PB5_OUT_NORMP \ 157 GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) 158 159 /* I2S2_WS */ 160 #define I2S2_WS_PA15_INP_NORMP \ 161 GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) 162 #define I2S2_WS_PA15_OUT_NORMP \ 163 GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) 164 #define I2S2_WS_PA4_INP_RMP \ 165 GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) 166 #define I2S2_WS_PA4_OUT_RMP \ 167 GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) 168 169 /* SPI0_MISO */ 170 #define SPI0_MISO_PA6_INP_NORMP \ 171 GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) 172 #define SPI0_MISO_PA6_OUT_NORMP \ 173 GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) 174 #define SPI0_MISO_PB4_INP_RMP \ 175 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) 176 #define SPI0_MISO_PB4_OUT_RMP \ 177 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) 178 179 /* SPI0_MOSI */ 180 #define SPI0_MOSI_PA7_INP_NORMP \ 181 GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) 182 #define SPI0_MOSI_PA7_OUT_NORMP \ 183 GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) 184 #define SPI0_MOSI_PB5_INP_RMP \ 185 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) 186 #define SPI0_MOSI_PB5_OUT_RMP \ 187 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) 188 189 /* SPI0_NSS */ 190 #define SPI0_NSS_PA4_INP_NORMP \ 191 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) 192 #define SPI0_NSS_PA4_OUT_NORMP \ 193 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) 194 #define SPI0_NSS_PA15_INP_RMP \ 195 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) 196 #define SPI0_NSS_PA15_OUT_RMP \ 197 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) 198 199 /* SPI0_SCK */ 200 #define SPI0_SCK_PA5_INP_NORMP \ 201 GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) 202 #define SPI0_SCK_PA5_OUT_NORMP \ 203 GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) 204 #define SPI0_SCK_PB3_INP_RMP \ 205 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) 206 #define SPI0_SCK_PB3_OUT_RMP \ 207 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) 208 209 /* SPI2_MISO */ 210 #define SPI2_MISO_PB4_INP_NORMP \ 211 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) 212 #define SPI2_MISO_PB4_OUT_NORMP \ 213 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) 214 215 /* SPI2_MOSI */ 216 #define SPI2_MOSI_PB5_INP_NORMP \ 217 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) 218 #define SPI2_MOSI_PB5_OUT_NORMP \ 219 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) 220 221 /* SPI2_NSS */ 222 #define SPI2_NSS_PA15_INP_NORMP \ 223 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) 224 #define SPI2_NSS_PA15_OUT_NORMP \ 225 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) 226 #define SPI2_NSS_PA4_INP_RMP \ 227 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) 228 #define SPI2_NSS_PA4_OUT_RMP \ 229 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) 230 231 /* SPI2_SCK */ 232 #define SPI2_SCK_PB3_INP_NORMP \ 233 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) 234 #define SPI2_SCK_PB3_OUT_NORMP \ 235 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) 236 237 /* TIMER0_CH0 */ 238 #define TIMER0_CH0_PA8_INP_NORMP \ 239 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) 240 #define TIMER0_CH0_PA8_OUT_NORMP \ 241 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) 242 #define TIMER0_CH0_PA8_INP_PRMP \ 243 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) 244 #define TIMER0_CH0_PA8_OUT_PRMP \ 245 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) 246 247 /* TIMER0_CH0_ON */ 248 #define TIMER0_CH0_ON_PA7_PRMP \ 249 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) 250 251 /* TIMER0_CH1 */ 252 #define TIMER0_CH1_PA9_INP_NORMP \ 253 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) 254 #define TIMER0_CH1_PA9_OUT_NORMP \ 255 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) 256 #define TIMER0_CH1_PA9_INP_PRMP \ 257 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) 258 #define TIMER0_CH1_PA9_OUT_PRMP \ 259 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) 260 261 /* TIMER0_CH1_ON */ 262 #define TIMER0_CH1_ON_PB0_PRMP \ 263 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) 264 265 /* TIMER0_CH2 */ 266 #define TIMER0_CH2_PA10_INP_NORMP \ 267 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) 268 #define TIMER0_CH2_PA10_OUT_NORMP \ 269 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) 270 #define TIMER0_CH2_PA10_INP_PRMP \ 271 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) 272 #define TIMER0_CH2_PA10_OUT_PRMP \ 273 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) 274 275 /* TIMER0_CH2_ON */ 276 #define TIMER0_CH2_ON_PB1_PRMP \ 277 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) 278 279 /* TIMER0_CH3 */ 280 #define TIMER0_CH3_PA11_INP_NORMP \ 281 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) 282 #define TIMER0_CH3_PA11_OUT_NORMP \ 283 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) 284 #define TIMER0_CH3_PA11_INP_PRMP \ 285 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) 286 #define TIMER0_CH3_PA11_OUT_PRMP \ 287 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) 288 289 /* TIMER0_ETI */ 290 #define TIMER0_ETI_PA12_NORMP \ 291 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) 292 #define TIMER0_ETI_PA12_PRMP \ 293 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) 294 295 /* TIMER1_CH0 */ 296 #define TIMER1_CH0_PA0_INP_NORMP \ 297 GD32_PINMUX_AFIO('A', 0, GPIO_IN, TIMER1_NORMP) 298 #define TIMER1_CH0_PA0_OUT_NORMP \ 299 GD32_PINMUX_AFIO('A', 0, ALTERNATE, TIMER1_NORMP) 300 #define TIMER1_CH0_PA0_INP_PRMP2 \ 301 GD32_PINMUX_AFIO('A', 0, GPIO_IN, TIMER1_PRMP2) 302 #define TIMER1_CH0_PA0_OUT_PRMP2 \ 303 GD32_PINMUX_AFIO('A', 0, ALTERNATE, TIMER1_PRMP2) 304 #define TIMER1_CH0_PA15_INP_PRMP1 \ 305 GD32_PINMUX_AFIO('A', 15, GPIO_IN, TIMER1_PRMP1) 306 #define TIMER1_CH0_PA15_OUT_PRMP1 \ 307 GD32_PINMUX_AFIO('A', 15, ALTERNATE, TIMER1_PRMP1) 308 #define TIMER1_CH0_PA15_INP_FRMP \ 309 GD32_PINMUX_AFIO('A', 15, GPIO_IN, TIMER1_FRMP) 310 #define TIMER1_CH0_PA15_OUT_FRMP \ 311 GD32_PINMUX_AFIO('A', 15, ALTERNATE, TIMER1_FRMP) 312 313 /* TIMER1_CH1 */ 314 #define TIMER1_CH1_PA1_INP_NORMP \ 315 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) 316 #define TIMER1_CH1_PA1_OUT_NORMP \ 317 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) 318 #define TIMER1_CH1_PA1_INP_PRMP2 \ 319 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) 320 #define TIMER1_CH1_PA1_OUT_PRMP2 \ 321 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) 322 #define TIMER1_CH1_PB3_INP_PRMP1 \ 323 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) 324 #define TIMER1_CH1_PB3_OUT_PRMP1 \ 325 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) 326 #define TIMER1_CH1_PB3_INP_FRMP \ 327 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) 328 #define TIMER1_CH1_PB3_OUT_FRMP \ 329 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) 330 331 /* TIMER1_CH2 */ 332 #define TIMER1_CH2_PA2_INP_NORMP \ 333 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) 334 #define TIMER1_CH2_PA2_OUT_NORMP \ 335 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) 336 #define TIMER1_CH2_PA2_INP_PRMP1 \ 337 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) 338 #define TIMER1_CH2_PA2_OUT_PRMP1 \ 339 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) 340 341 /* TIMER1_CH3 */ 342 #define TIMER1_CH3_PA3_INP_NORMP \ 343 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) 344 #define TIMER1_CH3_PA3_OUT_NORMP \ 345 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) 346 #define TIMER1_CH3_PA3_INP_PRMP1 \ 347 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) 348 #define TIMER1_CH3_PA3_OUT_PRMP1 \ 349 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) 350 351 /* TIMER2_CH0 */ 352 #define TIMER2_CH0_PA6_INP_NORMP \ 353 GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) 354 #define TIMER2_CH0_PA6_OUT_NORMP \ 355 GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) 356 #define TIMER2_CH0_PB4_INP_PRMP \ 357 GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) 358 #define TIMER2_CH0_PB4_OUT_PRMP \ 359 GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) 360 361 /* TIMER2_CH1 */ 362 #define TIMER2_CH1_PA7_INP_NORMP \ 363 GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) 364 #define TIMER2_CH1_PA7_OUT_NORMP \ 365 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) 366 #define TIMER2_CH1_PB5_INP_PRMP \ 367 GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) 368 #define TIMER2_CH1_PB5_OUT_PRMP \ 369 GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) 370 371 /* TIMER2_CH2 */ 372 #define TIMER2_CH2_PB0_INP_NORMP \ 373 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) 374 #define TIMER2_CH2_PB0_OUT_NORMP \ 375 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) 376 #define TIMER2_CH2_PB0_INP_PRMP \ 377 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) 378 #define TIMER2_CH2_PB0_OUT_PRMP \ 379 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) 380 381 /* TIMER2_CH3 */ 382 #define TIMER2_CH3_PB1_INP_NORMP \ 383 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) 384 #define TIMER2_CH3_PB1_OUT_NORMP \ 385 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) 386 #define TIMER2_CH3_PB1_INP_PRMP \ 387 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) 388 #define TIMER2_CH3_PB1_OUT_PRMP \ 389 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) 390 391 /* TIMER3_CH0 */ 392 #define TIMER3_CH0_PB6_INP_NORMP \ 393 GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) 394 #define TIMER3_CH0_PB6_OUT_NORMP \ 395 GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) 396 397 /* TIMER3_CH1 */ 398 #define TIMER3_CH1_PB7_INP_NORMP \ 399 GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) 400 #define TIMER3_CH1_PB7_OUT_NORMP \ 401 GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) 402 403 /* TIMER4_CH1 */ 404 #define TIMER4_CH1_PA1_INP \ 405 GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) 406 #define TIMER4_CH1_PA1_OUT \ 407 GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) 408 409 /* TIMER4_CH2 */ 410 #define TIMER4_CH2_PA2_INP \ 411 GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) 412 #define TIMER4_CH2_PA2_OUT \ 413 GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) 414 415 /* TIMER4_CH3 */ 416 #define TIMER4_CH3_PA3_INP \ 417 GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) 418 #define TIMER4_CH3_PA3_OUT \ 419 GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) 420 421 /* USART0_CK */ 422 #define USART0_CK_PA8 \ 423 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 424 425 /* USART0_CTS */ 426 #define USART0_CTS_PA11 \ 427 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 428 429 /* USART0_RTS */ 430 #define USART0_RTS_PA12 \ 431 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 432 433 /* USART0_RX */ 434 #define USART0_RX_PA10_NORMP \ 435 GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) 436 #define USART0_RX_PB7_RMP \ 437 GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) 438 439 /* USART0_TX */ 440 #define USART0_TX_PA9_NORMP \ 441 GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) 442 #define USART0_TX_PB6_RMP \ 443 GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) 444 445 /* USART1_CK */ 446 #define USART1_CK_PA4_NORMP \ 447 GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) 448 449 /* USART1_CTS */ 450 #define USART1_CTS_PA0_NORMP \ 451 GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) 452 453 /* USART1_RTS */ 454 #define USART1_RTS_PA1_NORMP \ 455 GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) 456 457 /* USART1_RX */ 458 #define USART1_RX_PA3_NORMP \ 459 GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) 460 461 /* USART1_TX */ 462 #define USART1_TX_PA2_NORMP \ 463 GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) 464 465 /* USBFS_DM */ 466 #define USBFS_DM_PA11_INP \ 467 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 468 #define USBFS_DM_PA11_OUT \ 469 GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) 470 471 /* USBFS_DP */ 472 #define USBFS_DP_PA12_INP \ 473 GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) 474 #define USBFS_DP_PA12_OUT \ 475 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 476 477 /* USBFS_ID */ 478 #define USBFS_ID_PA10_INP \ 479 GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) 480 #define USBFS_ID_PA10_OUT \ 481 GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) 482 483 /* USBFS_SOF */ 484 #define USBFS_SOF_PA8 \ 485 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 486 487 /* USBFS_VBUS */ 488 #define USBFS_VBUS_PA9 \ 489 GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) 490 491 /* WKUP */ 492 #define WKUP_PA0 \ 493 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 494
