1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32vf103xx-afio.h" 8 9 /* ADC01_IN0 */ 10 #define ADC01_IN0_PA0 \ 11 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 12 13 /* ADC01_IN1 */ 14 #define ADC01_IN1_PA1 \ 15 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 16 17 /* ADC01_IN2 */ 18 #define ADC01_IN2_PA2 \ 19 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 20 21 /* ADC01_IN3 */ 22 #define ADC01_IN3_PA3 \ 23 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 24 25 /* ADC01_IN4 */ 26 #define ADC01_IN4_PA4 \ 27 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 28 29 /* ADC01_IN5 */ 30 #define ADC01_IN5_PA5 \ 31 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 32 33 /* ADC01_IN6 */ 34 #define ADC01_IN6_PA6 \ 35 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 36 37 /* ADC01_IN7 */ 38 #define ADC01_IN7_PA7 \ 39 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 40 41 /* ADC01_IN8 */ 42 #define ADC01_IN8_PB0 \ 43 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 44 45 /* ADC01_IN9 */ 46 #define ADC01_IN9_PB1 \ 47 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 48 49 /* ANALOG */ 50 #define ANALOG_PA0 \ 51 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 52 #define ANALOG_PA1 \ 53 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 54 #define ANALOG_PA2 \ 55 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 56 #define ANALOG_PA3 \ 57 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 58 #define ANALOG_PA4 \ 59 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 60 #define ANALOG_PA5 \ 61 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 62 #define ANALOG_PA6 \ 63 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 64 #define ANALOG_PA7 \ 65 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 66 #define ANALOG_PA8 \ 67 GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) 68 #define ANALOG_PA9 \ 69 GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) 70 #define ANALOG_PA10 \ 71 GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) 72 #define ANALOG_PA11 \ 73 GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) 74 #define ANALOG_PA12 \ 75 GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) 76 #define ANALOG_PA13 \ 77 GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) 78 #define ANALOG_PA14 \ 79 GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) 80 #define ANALOG_PA15 \ 81 GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) 82 #define ANALOG_PB0 \ 83 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 84 #define ANALOG_PB1 \ 85 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 86 #define ANALOG_PB2 \ 87 GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) 88 #define ANALOG_PB3 \ 89 GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) 90 #define ANALOG_PB4 \ 91 GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) 92 #define ANALOG_PB5 \ 93 GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) 94 #define ANALOG_PB6 \ 95 GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) 96 #define ANALOG_PB7 \ 97 GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) 98 #define ANALOG_PB8 \ 99 GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) 100 #define ANALOG_PB9 \ 101 GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) 102 #define ANALOG_PB10 \ 103 GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) 104 #define ANALOG_PB11 \ 105 GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) 106 #define ANALOG_PB12 \ 107 GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) 108 #define ANALOG_PB13 \ 109 GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) 110 #define ANALOG_PB14 \ 111 GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) 112 #define ANALOG_PB15 \ 113 GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) 114 #define ANALOG_PC13 \ 115 GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) 116 #define ANALOG_PC14 \ 117 GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) 118 #define ANALOG_PC15 \ 119 GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) 120 #define ANALOG_PD0 \ 121 GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) 122 #define ANALOG_PD1 \ 123 GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) 124 125 /* CAN0_RX */ 126 #define CAN0_RX_PA11_NORMP \ 127 GD32_PINMUX_AFIO('A', 11, GPIO_IN, CAN0_NORMP) 128 #define CAN0_RX_PB8_PRMP \ 129 GD32_PINMUX_AFIO('B', 8, GPIO_IN, CAN0_PRMP) 130 #define CAN0_RX_PD0_FRMP \ 131 GD32_PINMUX_AFIO('D', 0, GPIO_IN, CAN0_FRMP) 132 133 /* CAN0_TX */ 134 #define CAN0_TX_PA12_NORMP \ 135 GD32_PINMUX_AFIO('A', 12, ALTERNATE, CAN0_NORMP) 136 #define CAN0_TX_PB9_PRMP \ 137 GD32_PINMUX_AFIO('B', 9, ALTERNATE, CAN0_PRMP) 138 #define CAN0_TX_PD1_FRMP \ 139 GD32_PINMUX_AFIO('D', 1, ALTERNATE, CAN0_FRMP) 140 141 /* CAN1_RX */ 142 #define CAN1_RX_PB12_NORMP \ 143 GD32_PINMUX_AFIO('B', 12, GPIO_IN, CAN1_NORMP) 144 #define CAN1_RX_PB5_RMP \ 145 GD32_PINMUX_AFIO('B', 5, GPIO_IN, CAN1_RMP) 146 147 /* CAN1_TX */ 148 #define CAN1_TX_PB13_NORMP \ 149 GD32_PINMUX_AFIO('B', 13, ALTERNATE, CAN1_NORMP) 150 #define CAN1_TX_PB6_RMP \ 151 GD32_PINMUX_AFIO('B', 6, ALTERNATE, CAN1_RMP) 152 153 /* CK_OUT0 */ 154 #define CK_OUT0_PA8 \ 155 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 156 157 /* DAC_OUT0 */ 158 #define DAC_OUT0_PA4 \ 159 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 160 161 /* DAC_OUT1 */ 162 #define DAC_OUT1_PA5 \ 163 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 164 165 /* I2C0_SCL */ 166 #define I2C0_SCL_PB6_NORMP \ 167 GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) 168 #define I2C0_SCL_PB8_RMP \ 169 GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) 170 171 /* I2C0_SDA */ 172 #define I2C0_SDA_PB7_NORMP \ 173 GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) 174 #define I2C0_SDA_PB9_RMP \ 175 GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) 176 177 /* I2C0_SMBA */ 178 #define I2C0_SMBA_PB5 \ 179 GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) 180 181 /* I2S1_CK */ 182 #define I2S1_CK_PB13_INP \ 183 GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) 184 #define I2S1_CK_PB13_OUT \ 185 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 186 187 /* I2S1_SD */ 188 #define I2S1_SD_PB15_INP \ 189 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 190 #define I2S1_SD_PB15_OUT \ 191 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 192 193 /* I2S1_WS */ 194 #define I2S1_WS_PB12_INP \ 195 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 196 #define I2S1_WS_PB12_OUT \ 197 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 198 199 /* SPI0_MISO */ 200 #define SPI0_MISO_PA6_INP_NORMP \ 201 GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) 202 #define SPI0_MISO_PA6_OUT_NORMP \ 203 GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) 204 #define SPI0_MISO_PB4_INP_RMP \ 205 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) 206 #define SPI0_MISO_PB4_OUT_RMP \ 207 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) 208 209 /* SPI0_MOSI */ 210 #define SPI0_MOSI_PA7_INP_NORMP \ 211 GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) 212 #define SPI0_MOSI_PA7_OUT_NORMP \ 213 GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) 214 #define SPI0_MOSI_PB5_INP_RMP \ 215 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) 216 #define SPI0_MOSI_PB5_OUT_RMP \ 217 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) 218 219 /* SPI0_NSS */ 220 #define SPI0_NSS_PA4_INP_NORMP \ 221 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) 222 #define SPI0_NSS_PA4_OUT_NORMP \ 223 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) 224 #define SPI0_NSS_PA15_INP_RMP \ 225 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) 226 #define SPI0_NSS_PA15_OUT_RMP \ 227 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) 228 229 /* SPI0_SCK */ 230 #define SPI0_SCK_PA5_INP_NORMP \ 231 GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) 232 #define SPI0_SCK_PA5_OUT_NORMP \ 233 GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) 234 #define SPI0_SCK_PB3_INP_RMP \ 235 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) 236 #define SPI0_SCK_PB3_OUT_RMP \ 237 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) 238 239 /* SPI1_MISO */ 240 #define SPI1_MISO_PB14_INP \ 241 GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) 242 #define SPI1_MISO_PB14_OUT \ 243 GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) 244 245 /* SPI1_MOSI */ 246 #define SPI1_MOSI_PB15_INP \ 247 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 248 #define SPI1_MOSI_PB15_OUT \ 249 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 250 251 /* SPI1_NSS */ 252 #define SPI1_NSS_PB12_INP \ 253 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 254 #define SPI1_NSS_PB12_OUT \ 255 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 256 257 /* SPI1_SCK */ 258 #define SPI1_SCK_PB13_INP \ 259 GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) 260 #define SPI1_SCK_PB13_OUT \ 261 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 262 263 /* TAMPER */ 264 #define TAMPER_PC13 \ 265 GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) 266 267 /* TIMER0_BRKIN */ 268 #define TIMER0_BRKIN_PB12 \ 269 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 270 271 /* TIMER0_CH0 */ 272 #define TIMER0_CH0_PA8_INP_NORMP \ 273 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) 274 #define TIMER0_CH0_PA8_OUT_NORMP \ 275 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) 276 #define TIMER0_CH0_PA8_INP_PRMP \ 277 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) 278 #define TIMER0_CH0_PA8_OUT_PRMP \ 279 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) 280 281 /* TIMER0_CH0_ON */ 282 #define TIMER0_CH0_ON_PB13_NORMP \ 283 GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) 284 #define TIMER0_CH0_ON_PA7_PRMP \ 285 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) 286 287 /* TIMER0_CH1 */ 288 #define TIMER0_CH1_PA9_INP_NORMP \ 289 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) 290 #define TIMER0_CH1_PA9_OUT_NORMP \ 291 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) 292 #define TIMER0_CH1_PA9_INP_PRMP \ 293 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) 294 #define TIMER0_CH1_PA9_OUT_PRMP \ 295 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) 296 297 /* TIMER0_CH1_ON */ 298 #define TIMER0_CH1_ON_PB14_NORMP \ 299 GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) 300 #define TIMER0_CH1_ON_PB0_PRMP \ 301 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) 302 303 /* TIMER0_CH2 */ 304 #define TIMER0_CH2_PA10_INP_NORMP \ 305 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) 306 #define TIMER0_CH2_PA10_OUT_NORMP \ 307 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) 308 #define TIMER0_CH2_PA10_INP_PRMP \ 309 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) 310 #define TIMER0_CH2_PA10_OUT_PRMP \ 311 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) 312 313 /* TIMER0_CH2_ON */ 314 #define TIMER0_CH2_ON_PB15_NORMP \ 315 GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) 316 #define TIMER0_CH2_ON_PB1_PRMP \ 317 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) 318 319 /* TIMER0_CH3 */ 320 #define TIMER0_CH3_PA11_INP_NORMP \ 321 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) 322 #define TIMER0_CH3_PA11_OUT_NORMP \ 323 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) 324 #define TIMER0_CH3_PA11_INP_PRMP \ 325 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) 326 #define TIMER0_CH3_PA11_OUT_PRMP \ 327 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) 328 329 /* TIMER0_ETI */ 330 #define TIMER0_ETI_PA12_NORMP \ 331 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) 332 #define TIMER0_ETI_PA12_PRMP \ 333 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) 334 335 /* TIMER1_CH0 */ 336 #define TIMER1_CH0_PA0_INP_NORMP \ 337 GD32_PINMUX_AFIO('A', 0, GPIO_IN, TIMER1_NORMP) 338 #define TIMER1_CH0_PA0_OUT_NORMP \ 339 GD32_PINMUX_AFIO('A', 0, ALTERNATE, TIMER1_NORMP) 340 #define TIMER1_CH0_PA0_INP_PRMP2 \ 341 GD32_PINMUX_AFIO('A', 0, GPIO_IN, TIMER1_PRMP2) 342 #define TIMER1_CH0_PA0_OUT_PRMP2 \ 343 GD32_PINMUX_AFIO('A', 0, ALTERNATE, TIMER1_PRMP2) 344 #define TIMER1_CH0_PA15_INP_PRMP1 \ 345 GD32_PINMUX_AFIO('A', 15, GPIO_IN, TIMER1_PRMP1) 346 #define TIMER1_CH0_PA15_OUT_PRMP1 \ 347 GD32_PINMUX_AFIO('A', 15, ALTERNATE, TIMER1_PRMP1) 348 #define TIMER1_CH0_PA15_INP_FRMP \ 349 GD32_PINMUX_AFIO('A', 15, GPIO_IN, TIMER1_FRMP) 350 #define TIMER1_CH0_PA15_OUT_FRMP \ 351 GD32_PINMUX_AFIO('A', 15, ALTERNATE, TIMER1_FRMP) 352 353 /* TIMER1_CH1 */ 354 #define TIMER1_CH1_PA1_INP_NORMP \ 355 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) 356 #define TIMER1_CH1_PA1_OUT_NORMP \ 357 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) 358 #define TIMER1_CH1_PA1_INP_PRMP2 \ 359 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) 360 #define TIMER1_CH1_PA1_OUT_PRMP2 \ 361 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) 362 #define TIMER1_CH1_PB3_INP_PRMP1 \ 363 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) 364 #define TIMER1_CH1_PB3_OUT_PRMP1 \ 365 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) 366 #define TIMER1_CH1_PB3_INP_FRMP \ 367 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) 368 #define TIMER1_CH1_PB3_OUT_FRMP \ 369 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) 370 371 /* TIMER1_CH2 */ 372 #define TIMER1_CH2_PA2_INP_NORMP \ 373 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) 374 #define TIMER1_CH2_PA2_OUT_NORMP \ 375 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) 376 #define TIMER1_CH2_PA2_INP_PRMP1 \ 377 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) 378 #define TIMER1_CH2_PA2_OUT_PRMP1 \ 379 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) 380 #define TIMER1_CH2_PB10_INP_PRMP2 \ 381 GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2) 382 #define TIMER1_CH2_PB10_OUT_PRMP2 \ 383 GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2) 384 #define TIMER1_CH2_PB10_INP_FRMP \ 385 GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP) 386 #define TIMER1_CH2_PB10_OUT_FRMP \ 387 GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP) 388 389 /* TIMER1_CH3 */ 390 #define TIMER1_CH3_PA3_INP_NORMP \ 391 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) 392 #define TIMER1_CH3_PA3_OUT_NORMP \ 393 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) 394 #define TIMER1_CH3_PA3_INP_PRMP1 \ 395 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) 396 #define TIMER1_CH3_PA3_OUT_PRMP1 \ 397 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) 398 #define TIMER1_CH3_PB11_INP_PRMP2 \ 399 GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2) 400 #define TIMER1_CH3_PB11_OUT_PRMP2 \ 401 GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2) 402 #define TIMER1_CH3_PB11_INP_FRMP \ 403 GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP) 404 #define TIMER1_CH3_PB11_OUT_FRMP \ 405 GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP) 406 407 /* TIMER2_CH0 */ 408 #define TIMER2_CH0_PA6_INP_NORMP \ 409 GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) 410 #define TIMER2_CH0_PA6_OUT_NORMP \ 411 GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) 412 #define TIMER2_CH0_PB4_INP_PRMP \ 413 GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) 414 #define TIMER2_CH0_PB4_OUT_PRMP \ 415 GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) 416 417 /* TIMER2_CH1 */ 418 #define TIMER2_CH1_PA7_INP_NORMP \ 419 GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) 420 #define TIMER2_CH1_PA7_OUT_NORMP \ 421 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) 422 #define TIMER2_CH1_PB5_INP_PRMP \ 423 GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) 424 #define TIMER2_CH1_PB5_OUT_PRMP \ 425 GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) 426 427 /* TIMER2_CH2 */ 428 #define TIMER2_CH2_PB0_INP_NORMP \ 429 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) 430 #define TIMER2_CH2_PB0_OUT_NORMP \ 431 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) 432 #define TIMER2_CH2_PB0_INP_PRMP \ 433 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) 434 #define TIMER2_CH2_PB0_OUT_PRMP \ 435 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) 436 437 /* TIMER2_CH3 */ 438 #define TIMER2_CH3_PB1_INP_NORMP \ 439 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) 440 #define TIMER2_CH3_PB1_OUT_NORMP \ 441 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) 442 #define TIMER2_CH3_PB1_INP_PRMP \ 443 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) 444 #define TIMER2_CH3_PB1_OUT_PRMP \ 445 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) 446 447 /* USART0_CK */ 448 #define USART0_CK_PA8 \ 449 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 450 451 /* USART0_CTS */ 452 #define USART0_CTS_PA11 \ 453 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 454 455 /* USART0_RTS */ 456 #define USART0_RTS_PA12 \ 457 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 458 459 /* USART0_RX */ 460 #define USART0_RX_PA10_NORMP \ 461 GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) 462 #define USART0_RX_PB7_RMP \ 463 GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) 464 465 /* USART0_TX */ 466 #define USART0_TX_PA9_NORMP \ 467 GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) 468 #define USART0_TX_PB6_RMP \ 469 GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) 470 471 /* USART1_CK */ 472 #define USART1_CK_PA4_NORMP \ 473 GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) 474 475 /* USART1_CTS */ 476 #define USART1_CTS_PA0_NORMP \ 477 GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) 478 479 /* USART1_RTS */ 480 #define USART1_RTS_PA1_NORMP \ 481 GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) 482 483 /* USART1_RX */ 484 #define USART1_RX_PA3_NORMP \ 485 GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) 486 487 /* USART1_TX */ 488 #define USART1_TX_PA2_NORMP \ 489 GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) 490 491 /* USBFS_DM */ 492 #define USBFS_DM_PA11_INP \ 493 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 494 #define USBFS_DM_PA11_OUT \ 495 GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) 496 497 /* USBFS_DP */ 498 #define USBFS_DP_PA12_INP \ 499 GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) 500 #define USBFS_DP_PA12_OUT \ 501 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 502 503 /* USBFS_ID */ 504 #define USBFS_ID_PA10_INP \ 505 GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) 506 #define USBFS_ID_PA10_OUT \ 507 GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) 508 509 /* USBFS_SOF */ 510 #define USBFS_SOF_PA8 \ 511 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 512 513 /* USBFS_VBUS */ 514 #define USBFS_VBUS_PA9 \ 515 GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) 516 517 /* WKUP */ 518 #define WKUP_PA0 \ 519 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 520
