1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32-af.h" 8 9 /* ADC_IN0 */ 10 #define ADC_IN0_PA0 \ 11 GD32_PINMUX_AF('A', 0, ANALOG) 12 13 /* ADC_IN1 */ 14 #define ADC_IN1_PA1 \ 15 GD32_PINMUX_AF('A', 1, ANALOG) 16 17 /* ADC_IN2 */ 18 #define ADC_IN2_PA2 \ 19 GD32_PINMUX_AF('A', 2, ANALOG) 20 21 /* ADC_IN3 */ 22 #define ADC_IN3_PA3 \ 23 GD32_PINMUX_AF('A', 3, ANALOG) 24 25 /* ADC_IN4 */ 26 #define ADC_IN4_PA4 \ 27 GD32_PINMUX_AF('A', 4, ANALOG) 28 29 /* ADC_IN5 */ 30 #define ADC_IN5_PA5 \ 31 GD32_PINMUX_AF('A', 5, ANALOG) 32 33 /* ADC_IN6 */ 34 #define ADC_IN6_PA6 \ 35 GD32_PINMUX_AF('A', 6, ANALOG) 36 37 /* ADC_IN7 */ 38 #define ADC_IN7_PA7 \ 39 GD32_PINMUX_AF('A', 7, ANALOG) 40 41 /* ADC_IN8 */ 42 #define ADC_IN8_PB0 \ 43 GD32_PINMUX_AF('B', 0, ANALOG) 44 45 /* ADC_IN9 */ 46 #define ADC_IN9_PB1 \ 47 GD32_PINMUX_AF('B', 1, ANALOG) 48 49 /* ANALOG */ 50 #define ANALOG_PA0 \ 51 GD32_PINMUX_AF('A', 0, ANALOG) 52 #define ANALOG_PA1 \ 53 GD32_PINMUX_AF('A', 1, ANALOG) 54 #define ANALOG_PA10 \ 55 GD32_PINMUX_AF('A', 10, ANALOG) 56 #define ANALOG_PA11 \ 57 GD32_PINMUX_AF('A', 11, ANALOG) 58 #define ANALOG_PA12 \ 59 GD32_PINMUX_AF('A', 12, ANALOG) 60 #define ANALOG_PA13 \ 61 GD32_PINMUX_AF('A', 13, ANALOG) 62 #define ANALOG_PA14 \ 63 GD32_PINMUX_AF('A', 14, ANALOG) 64 #define ANALOG_PA15 \ 65 GD32_PINMUX_AF('A', 15, ANALOG) 66 #define ANALOG_PA2 \ 67 GD32_PINMUX_AF('A', 2, ANALOG) 68 #define ANALOG_PA3 \ 69 GD32_PINMUX_AF('A', 3, ANALOG) 70 #define ANALOG_PA4 \ 71 GD32_PINMUX_AF('A', 4, ANALOG) 72 #define ANALOG_PA5 \ 73 GD32_PINMUX_AF('A', 5, ANALOG) 74 #define ANALOG_PA6 \ 75 GD32_PINMUX_AF('A', 6, ANALOG) 76 #define ANALOG_PA7 \ 77 GD32_PINMUX_AF('A', 7, ANALOG) 78 #define ANALOG_PA8 \ 79 GD32_PINMUX_AF('A', 8, ANALOG) 80 #define ANALOG_PA9 \ 81 GD32_PINMUX_AF('A', 9, ANALOG) 82 #define ANALOG_PB0 \ 83 GD32_PINMUX_AF('B', 0, ANALOG) 84 #define ANALOG_PB1 \ 85 GD32_PINMUX_AF('B', 1, ANALOG) 86 #define ANALOG_PB10 \ 87 GD32_PINMUX_AF('B', 10, ANALOG) 88 #define ANALOG_PB11 \ 89 GD32_PINMUX_AF('B', 11, ANALOG) 90 #define ANALOG_PB12 \ 91 GD32_PINMUX_AF('B', 12, ANALOG) 92 #define ANALOG_PB13 \ 93 GD32_PINMUX_AF('B', 13, ANALOG) 94 #define ANALOG_PB14 \ 95 GD32_PINMUX_AF('B', 14, ANALOG) 96 #define ANALOG_PB15 \ 97 GD32_PINMUX_AF('B', 15, ANALOG) 98 #define ANALOG_PB2 \ 99 GD32_PINMUX_AF('B', 2, ANALOG) 100 #define ANALOG_PB3 \ 101 GD32_PINMUX_AF('B', 3, ANALOG) 102 #define ANALOG_PB4 \ 103 GD32_PINMUX_AF('B', 4, ANALOG) 104 #define ANALOG_PB5 \ 105 GD32_PINMUX_AF('B', 5, ANALOG) 106 #define ANALOG_PB6 \ 107 GD32_PINMUX_AF('B', 6, ANALOG) 108 #define ANALOG_PB7 \ 109 GD32_PINMUX_AF('B', 7, ANALOG) 110 #define ANALOG_PB8 \ 111 GD32_PINMUX_AF('B', 8, ANALOG) 112 #define ANALOG_PB9 \ 113 GD32_PINMUX_AF('B', 9, ANALOG) 114 #define ANALOG_PC10 \ 115 GD32_PINMUX_AF('C', 10, ANALOG) 116 #define ANALOG_PC11 \ 117 GD32_PINMUX_AF('C', 11, ANALOG) 118 #define ANALOG_PC12 \ 119 GD32_PINMUX_AF('C', 12, ANALOG) 120 #define ANALOG_PC13 \ 121 GD32_PINMUX_AF('C', 13, ANALOG) 122 #define ANALOG_PC14 \ 123 GD32_PINMUX_AF('C', 14, ANALOG) 124 #define ANALOG_PC15 \ 125 GD32_PINMUX_AF('C', 15, ANALOG) 126 #define ANALOG_PC6 \ 127 GD32_PINMUX_AF('C', 6, ANALOG) 128 #define ANALOG_PC7 \ 129 GD32_PINMUX_AF('C', 7, ANALOG) 130 #define ANALOG_PD3 \ 131 GD32_PINMUX_AF('D', 3, ANALOG) 132 #define ANALOG_PF0 \ 133 GD32_PINMUX_AF('F', 0, ANALOG) 134 #define ANALOG_PF1 \ 135 GD32_PINMUX_AF('F', 1, ANALOG) 136 137 /* CK_OUT */ 138 #define CK_OUT_PA8 \ 139 GD32_PINMUX_AF('A', 8, AF0) 140 #define CK_OUT_PA9 \ 141 GD32_PINMUX_AF('A', 9, AF0) 142 #define CK_OUT_PB13 \ 143 GD32_PINMUX_AF('B', 13, AF0) 144 145 /* CMP0_OUT */ 146 #define CMP0_OUT_PA0 \ 147 GD32_PINMUX_AF('A', 0, AF6) 148 #define CMP0_OUT_PA11 \ 149 GD32_PINMUX_AF('A', 11, AF6) 150 #define CMP0_OUT_PA6 \ 151 GD32_PINMUX_AF('A', 6, AF6) 152 #define CMP0_OUT_PB0 \ 153 GD32_PINMUX_AF('B', 0, AF6) 154 #define CMP0_OUT_PB10 \ 155 GD32_PINMUX_AF('B', 10, AF6) 156 #define CMP0_OUT_PB8 \ 157 GD32_PINMUX_AF('B', 8, AF6) 158 159 /* CMP1_OUT */ 160 #define CMP1_OUT_PA12 \ 161 GD32_PINMUX_AF('A', 12, AF6) 162 #define CMP1_OUT_PA2 \ 163 GD32_PINMUX_AF('A', 2, AF6) 164 #define CMP1_OUT_PA7 \ 165 GD32_PINMUX_AF('A', 7, AF6) 166 #define CMP1_OUT_PB11 \ 167 GD32_PINMUX_AF('B', 11, AF6) 168 #define CMP1_OUT_PB5 \ 169 GD32_PINMUX_AF('B', 5, AF8) 170 #define CMP1_OUT_PB9 \ 171 GD32_PINMUX_AF('B', 9, AF6) 172 173 /* CTC_SYNC */ 174 #define CTC_SYNC_PA8 \ 175 GD32_PINMUX_AF('A', 8, AF8) 176 177 /* DAC_OUT */ 178 #define DAC_OUT_PA4 \ 179 GD32_PINMUX_AF('A', 4, ANALOG) 180 181 /* EVENTOUT */ 182 #define EVENTOUT_PA0 \ 183 GD32_PINMUX_AF('A', 0, AF9) 184 #define EVENTOUT_PA1 \ 185 GD32_PINMUX_AF('A', 1, AF9) 186 #define EVENTOUT_PA10 \ 187 GD32_PINMUX_AF('A', 10, AF9) 188 #define EVENTOUT_PA11 \ 189 GD32_PINMUX_AF('A', 11, AF9) 190 #define EVENTOUT_PA12 \ 191 GD32_PINMUX_AF('A', 12, AF9) 192 #define EVENTOUT_PA13 \ 193 GD32_PINMUX_AF('A', 13, AF9) 194 #define EVENTOUT_PA14 \ 195 GD32_PINMUX_AF('A', 14, AF9) 196 #define EVENTOUT_PA15 \ 197 GD32_PINMUX_AF('A', 15, AF9) 198 #define EVENTOUT_PA2 \ 199 GD32_PINMUX_AF('A', 2, AF9) 200 #define EVENTOUT_PA3 \ 201 GD32_PINMUX_AF('A', 3, AF9) 202 #define EVENTOUT_PA4 \ 203 GD32_PINMUX_AF('A', 4, AF9) 204 #define EVENTOUT_PA5 \ 205 GD32_PINMUX_AF('A', 5, AF9) 206 #define EVENTOUT_PA6 \ 207 GD32_PINMUX_AF('A', 6, AF9) 208 #define EVENTOUT_PA7 \ 209 GD32_PINMUX_AF('A', 7, AF9) 210 #define EVENTOUT_PA8 \ 211 GD32_PINMUX_AF('A', 8, AF9) 212 #define EVENTOUT_PA9 \ 213 GD32_PINMUX_AF('A', 9, AF9) 214 #define EVENTOUT_PB0 \ 215 GD32_PINMUX_AF('B', 0, AF9) 216 #define EVENTOUT_PB1 \ 217 GD32_PINMUX_AF('B', 1, AF9) 218 #define EVENTOUT_PB10 \ 219 GD32_PINMUX_AF('B', 10, AF9) 220 #define EVENTOUT_PB11 \ 221 GD32_PINMUX_AF('B', 11, AF9) 222 #define EVENTOUT_PB12 \ 223 GD32_PINMUX_AF('B', 12, AF9) 224 #define EVENTOUT_PB13 \ 225 GD32_PINMUX_AF('B', 13, AF9) 226 #define EVENTOUT_PB14 \ 227 GD32_PINMUX_AF('B', 14, AF9) 228 #define EVENTOUT_PB15 \ 229 GD32_PINMUX_AF('B', 15, AF9) 230 #define EVENTOUT_PB2 \ 231 GD32_PINMUX_AF('B', 2, AF9) 232 #define EVENTOUT_PB3 \ 233 GD32_PINMUX_AF('B', 3, AF9) 234 #define EVENTOUT_PB4 \ 235 GD32_PINMUX_AF('B', 4, AF9) 236 #define EVENTOUT_PB5 \ 237 GD32_PINMUX_AF('B', 5, AF9) 238 #define EVENTOUT_PB6 \ 239 GD32_PINMUX_AF('B', 6, AF9) 240 #define EVENTOUT_PB7 \ 241 GD32_PINMUX_AF('B', 7, AF9) 242 #define EVENTOUT_PB8 \ 243 GD32_PINMUX_AF('B', 8, AF9) 244 #define EVENTOUT_PB9 \ 245 GD32_PINMUX_AF('B', 9, AF9) 246 #define EVENTOUT_PC10 \ 247 GD32_PINMUX_AF('C', 10, AF9) 248 #define EVENTOUT_PC11 \ 249 GD32_PINMUX_AF('C', 11, AF9) 250 #define EVENTOUT_PC12 \ 251 GD32_PINMUX_AF('C', 12, AF9) 252 #define EVENTOUT_PC13 \ 253 GD32_PINMUX_AF('C', 13, AF9) 254 #define EVENTOUT_PC14 \ 255 GD32_PINMUX_AF('C', 14, AF9) 256 #define EVENTOUT_PC15 \ 257 GD32_PINMUX_AF('C', 15, AF9) 258 #define EVENTOUT_PC6 \ 259 GD32_PINMUX_AF('C', 6, AF9) 260 #define EVENTOUT_PC7 \ 261 GD32_PINMUX_AF('C', 7, AF9) 262 #define EVENTOUT_PF0 \ 263 GD32_PINMUX_AF('F', 0, AF9) 264 #define EVENTOUT_PF1 \ 265 GD32_PINMUX_AF('F', 1, AF9) 266 267 /* I2C0_SCL */ 268 #define I2C0_SCL_PA13 \ 269 GD32_PINMUX_AF('A', 13, AF4) 270 #define I2C0_SCL_PA9 \ 271 GD32_PINMUX_AF('A', 9, AF4) 272 #define I2C0_SCL_PB6 \ 273 GD32_PINMUX_AF('B', 6, AF4) 274 #define I2C0_SCL_PB8 \ 275 GD32_PINMUX_AF('B', 8, AF4) 276 277 /* I2C0_SDA */ 278 #define I2C0_SDA_PA10 \ 279 GD32_PINMUX_AF('A', 10, AF4) 280 #define I2C0_SDA_PA14 \ 281 GD32_PINMUX_AF('A', 14, AF4) 282 #define I2C0_SDA_PB7 \ 283 GD32_PINMUX_AF('B', 7, AF4) 284 #define I2C0_SDA_PB9 \ 285 GD32_PINMUX_AF('B', 9, AF4) 286 287 /* I2C0_SMBA */ 288 #define I2C0_SMBA_PA1 \ 289 GD32_PINMUX_AF('A', 1, AF4) 290 #define I2C0_SMBA_PB5 \ 291 GD32_PINMUX_AF('B', 5, AF4) 292 293 /* I2C1_SCL */ 294 #define I2C1_SCL_PB10 \ 295 GD32_PINMUX_AF('B', 10, AF4) 296 #define I2C1_SCL_PB13 \ 297 GD32_PINMUX_AF('B', 13, AF4) 298 #define I2C1_SCL_PB6 \ 299 GD32_PINMUX_AF('B', 6, AF8) 300 #define I2C1_SCL_PB8 \ 301 GD32_PINMUX_AF('B', 8, AF8) 302 303 /* I2C1_SDA */ 304 #define I2C1_SDA_PB11 \ 305 GD32_PINMUX_AF('B', 11, AF4) 306 #define I2C1_SDA_PB14 \ 307 GD32_PINMUX_AF('B', 14, AF4) 308 #define I2C1_SDA_PB7 \ 309 GD32_PINMUX_AF('B', 7, AF8) 310 #define I2C1_SDA_PB9 \ 311 GD32_PINMUX_AF('B', 9, AF8) 312 313 /* I2C1_SMBA */ 314 #define I2C1_SMBA_PB12 \ 315 GD32_PINMUX_AF('B', 12, AF4) 316 317 /* I2S1_CK */ 318 #define I2S1_CK_PB10 \ 319 GD32_PINMUX_AF('B', 10, AF5) 320 #define I2S1_CK_PB13 \ 321 GD32_PINMUX_AF('B', 13, AF6) 322 #define I2S1_CK_PB3 \ 323 GD32_PINMUX_AF('B', 3, AF6) 324 #define I2S1_CK_PC10 \ 325 GD32_PINMUX_AF('C', 10, AF5) 326 #define I2S1_CK_PF1 \ 327 GD32_PINMUX_AF('F', 1, AF5) 328 329 /* I2S1_MCK */ 330 #define I2S1_MCK_PC6 \ 331 GD32_PINMUX_AF('C', 6, AF5) 332 #define I2S1_MCK_PD3 \ 333 GD32_PINMUX_AF('D', 3, AF6) 334 335 /* I2S1_SD */ 336 #define I2S1_SD_PB15 \ 337 GD32_PINMUX_AF('B', 15, AF6) 338 #define I2S1_SD_PB5 \ 339 GD32_PINMUX_AF('B', 5, AF6) 340 #define I2S1_SD_PC12 \ 341 GD32_PINMUX_AF('C', 12, AF5) 342 343 /* I2S1_WS */ 344 #define I2S1_WS_PA14 \ 345 GD32_PINMUX_AF('A', 14, AF6) 346 #define I2S1_WS_PA15 \ 347 GD32_PINMUX_AF('A', 15, AF6) 348 #define I2S1_WS_PA4 \ 349 GD32_PINMUX_AF('A', 4, AF6) 350 #define I2S1_WS_PB12 \ 351 GD32_PINMUX_AF('B', 12, AF6) 352 #define I2S1_WS_PB9 \ 353 GD32_PINMUX_AF('B', 9, AF5) 354 #define I2S1_WS_PF0 \ 355 GD32_PINMUX_AF('F', 0, AF5) 356 357 /* LPTIMER_ETI0 */ 358 #define LPTIMER_ETI0_PA5 \ 359 GD32_PINMUX_AF('A', 5, AF2) 360 #define LPTIMER_ETI0_PA7 \ 361 GD32_PINMUX_AF('A', 7, AF2) 362 #define LPTIMER_ETI0_PB6 \ 363 GD32_PINMUX_AF('B', 6, AF2) 364 365 /* LPTIMER_IN0 */ 366 #define LPTIMER_IN0_PA6 \ 367 GD32_PINMUX_AF('A', 6, AF2) 368 #define LPTIMER_IN0_PB1 \ 369 GD32_PINMUX_AF('B', 1, AF2) 370 #define LPTIMER_IN0_PB5 \ 371 GD32_PINMUX_AF('B', 5, AF2) 372 373 /* LPTIMER_IN1 */ 374 #define LPTIMER_IN1_PA9 \ 375 GD32_PINMUX_AF('A', 9, AF2) 376 #define LPTIMER_IN1_PB3 \ 377 GD32_PINMUX_AF('B', 3, AF2) 378 379 /* LPTIMER_OUT */ 380 #define LPTIMER_OUT_PA4 \ 381 GD32_PINMUX_AF('A', 4, AF2) 382 #define LPTIMER_OUT_PA8 \ 383 GD32_PINMUX_AF('A', 8, AF2) 384 #define LPTIMER_OUT_PB0 \ 385 GD32_PINMUX_AF('B', 0, AF2) 386 #define LPTIMER_OUT_PB2 \ 387 GD32_PINMUX_AF('B', 2, AF2) 388 389 /* LPUART_CTS */ 390 #define LPUART_CTS_PA6 \ 391 GD32_PINMUX_AF('A', 6, AF8) 392 #define LPUART_CTS_PB13 \ 393 GD32_PINMUX_AF('B', 13, AF8) 394 395 /* LPUART_RTS */ 396 #define LPUART_RTS_PB1 \ 397 GD32_PINMUX_AF('B', 1, AF8) 398 #define LPUART_RTS_PB12 \ 399 GD32_PINMUX_AF('B', 12, AF8) 400 #define LPUART_RTS_PB14 \ 401 GD32_PINMUX_AF('B', 14, AF8) 402 403 /* LPUART_RX */ 404 #define LPUART_RX_PA13 \ 405 GD32_PINMUX_AF('A', 13, AF2) 406 #define LPUART_RX_PA3 \ 407 GD32_PINMUX_AF('A', 3, AF8) 408 #define LPUART_RX_PB10 \ 409 GD32_PINMUX_AF('B', 10, AF8) 410 #define LPUART_RX_PB11 \ 411 GD32_PINMUX_AF('B', 11, AF7) 412 #define LPUART_RX_PC11 \ 413 GD32_PINMUX_AF('C', 11, AF8) 414 415 /* LPUART_TX */ 416 #define LPUART_TX_PA14 \ 417 GD32_PINMUX_AF('A', 14, AF2) 418 #define LPUART_TX_PA2 \ 419 GD32_PINMUX_AF('A', 2, AF8) 420 #define LPUART_TX_PB10 \ 421 GD32_PINMUX_AF('B', 10, AF7) 422 #define LPUART_TX_PB11 \ 423 GD32_PINMUX_AF('B', 11, AF8) 424 #define LPUART_TX_PC10 \ 425 GD32_PINMUX_AF('C', 10, AF8) 426 427 /* RTC_OUT */ 428 #define RTC_OUT_PB14 \ 429 GD32_PINMUX_AF('B', 14, AF0) 430 #define RTC_OUT_PB2 \ 431 GD32_PINMUX_AF('B', 2, AF0) 432 433 /* SPI0_IO2 */ 434 #define SPI0_IO2_PA13 \ 435 GD32_PINMUX_AF('A', 13, AF5) 436 #define SPI0_IO2_PA2 \ 437 GD32_PINMUX_AF('A', 2, AF5) 438 #define SPI0_IO2_PB6 \ 439 GD32_PINMUX_AF('B', 6, AF5) 440 441 /* SPI0_IO3 */ 442 #define SPI0_IO3_PA14 \ 443 GD32_PINMUX_AF('A', 14, AF5) 444 #define SPI0_IO3_PA3 \ 445 GD32_PINMUX_AF('A', 3, AF5) 446 #define SPI0_IO3_PB7 \ 447 GD32_PINMUX_AF('B', 7, AF5) 448 449 /* SPI0_MISO */ 450 #define SPI0_MISO_PA11 \ 451 GD32_PINMUX_AF('A', 11, AF5) 452 #define SPI0_MISO_PA6 \ 453 GD32_PINMUX_AF('A', 6, AF5) 454 #define SPI0_MISO_PB4 \ 455 GD32_PINMUX_AF('B', 4, AF5) 456 457 /* SPI0_MOSI */ 458 #define SPI0_MOSI_PA12 \ 459 GD32_PINMUX_AF('A', 12, AF5) 460 #define SPI0_MOSI_PA7 \ 461 GD32_PINMUX_AF('A', 7, AF5) 462 #define SPI0_MOSI_PB5 \ 463 GD32_PINMUX_AF('B', 5, AF5) 464 465 /* SPI0_NSS */ 466 #define SPI0_NSS_PA13 \ 467 GD32_PINMUX_AF('A', 13, AF6) 468 #define SPI0_NSS_PA15 \ 469 GD32_PINMUX_AF('A', 15, AF5) 470 #define SPI0_NSS_PA4 \ 471 GD32_PINMUX_AF('A', 4, AF5) 472 #define SPI0_NSS_PB0 \ 473 GD32_PINMUX_AF('B', 0, AF5) 474 475 /* SPI0_SCK */ 476 #define SPI0_SCK_PA1 \ 477 GD32_PINMUX_AF('A', 1, AF5) 478 #define SPI0_SCK_PA5 \ 479 GD32_PINMUX_AF('A', 5, AF5) 480 #define SPI0_SCK_PB3 \ 481 GD32_PINMUX_AF('B', 3, AF5) 482 483 /* SPI1_MISO */ 484 #define SPI1_MISO_PB14 \ 485 GD32_PINMUX_AF('B', 14, AF6) 486 #define SPI1_MISO_PB4 \ 487 GD32_PINMUX_AF('B', 4, AF6) 488 #define SPI1_MISO_PC11 \ 489 GD32_PINMUX_AF('C', 11, AF5) 490 #define SPI1_MISO_PD3 \ 491 GD32_PINMUX_AF('D', 3, AF5) 492 493 /* SPI1_MOSI */ 494 #define SPI1_MOSI_PB15 \ 495 GD32_PINMUX_AF('B', 15, AF6) 496 #define SPI1_MOSI_PB5 \ 497 GD32_PINMUX_AF('B', 5, AF6) 498 #define SPI1_MOSI_PC12 \ 499 GD32_PINMUX_AF('C', 12, AF5) 500 501 /* SPI1_NSS */ 502 #define SPI1_NSS_PA14 \ 503 GD32_PINMUX_AF('A', 14, AF6) 504 #define SPI1_NSS_PA15 \ 505 GD32_PINMUX_AF('A', 15, AF6) 506 #define SPI1_NSS_PA4 \ 507 GD32_PINMUX_AF('A', 4, AF6) 508 #define SPI1_NSS_PB12 \ 509 GD32_PINMUX_AF('B', 12, AF6) 510 #define SPI1_NSS_PB9 \ 511 GD32_PINMUX_AF('B', 9, AF5) 512 #define SPI1_NSS_PF0 \ 513 GD32_PINMUX_AF('F', 0, AF5) 514 515 /* SPI1_SCK */ 516 #define SPI1_SCK_PB10 \ 517 GD32_PINMUX_AF('B', 10, AF5) 518 #define SPI1_SCK_PB13 \ 519 GD32_PINMUX_AF('B', 13, AF6) 520 #define SPI1_SCK_PB3 \ 521 GD32_PINMUX_AF('B', 3, AF6) 522 #define SPI1_SCK_PC10 \ 523 GD32_PINMUX_AF('C', 10, AF5) 524 #define SPI1_SCK_PF1 \ 525 GD32_PINMUX_AF('F', 1, AF5) 526 527 /* SWCLK */ 528 #define SWCLK_PA14 \ 529 GD32_PINMUX_AF('A', 14, AF0) 530 531 /* SWDIO */ 532 #define SWDIO_PA13 \ 533 GD32_PINMUX_AF('A', 13, AF0) 534 535 /* TIMER1_CH0_ETI */ 536 #define TIMER1_CH0_ETI_PA0 \ 537 GD32_PINMUX_AF('A', 0, AF1) 538 #define TIMER1_CH0_ETI_PA15 \ 539 GD32_PINMUX_AF('A', 15, AF1) 540 #define TIMER1_CH0_ETI_PA5 \ 541 GD32_PINMUX_AF('A', 5, AF1) 542 543 /* TIMER1_CH1 */ 544 #define TIMER1_CH1_PA1 \ 545 GD32_PINMUX_AF('A', 1, AF1) 546 #define TIMER1_CH1_PB3 \ 547 GD32_PINMUX_AF('B', 3, AF1) 548 549 /* TIMER1_CH2 */ 550 #define TIMER1_CH2_PA2 \ 551 GD32_PINMUX_AF('A', 2, AF1) 552 #define TIMER1_CH2_PB10 \ 553 GD32_PINMUX_AF('B', 10, AF1) 554 555 /* TIMER1_CH3 */ 556 #define TIMER1_CH3_PA3 \ 557 GD32_PINMUX_AF('A', 3, AF1) 558 #define TIMER1_CH3_PB11 \ 559 GD32_PINMUX_AF('B', 11, AF1) 560 561 /* TIMER2_CH0 */ 562 #define TIMER2_CH0_PA6 \ 563 GD32_PINMUX_AF('A', 6, AF1) 564 #define TIMER2_CH0_PB4 \ 565 GD32_PINMUX_AF('B', 4, AF1) 566 #define TIMER2_CH0_PC6 \ 567 GD32_PINMUX_AF('C', 6, AF1) 568 569 /* TIMER2_CH1 */ 570 #define TIMER2_CH1_PA7 \ 571 GD32_PINMUX_AF('A', 7, AF1) 572 #define TIMER2_CH1_PB5 \ 573 GD32_PINMUX_AF('B', 5, AF1) 574 #define TIMER2_CH1_PC7 \ 575 GD32_PINMUX_AF('C', 7, AF1) 576 577 /* TIMER2_CH2 */ 578 #define TIMER2_CH2_PB0 \ 579 GD32_PINMUX_AF('B', 0, AF1) 580 581 /* TIMER2_CH3 */ 582 #define TIMER2_CH3_PB1 \ 583 GD32_PINMUX_AF('B', 1, AF1) 584 585 /* TIMER8_CH0 */ 586 #define TIMER8_CH0_PA2 \ 587 GD32_PINMUX_AF('A', 2, AF2) 588 589 /* TIMER8_CH1 */ 590 #define TIMER8_CH1_PA3 \ 591 GD32_PINMUX_AF('A', 3, AF2) 592 593 /* UART3_RX */ 594 #define UART3_RX_PA1 \ 595 GD32_PINMUX_AF('A', 1, AF8) 596 #define UART3_RX_PC11 \ 597 GD32_PINMUX_AF('C', 11, AF7) 598 599 /* UART3_TX */ 600 #define UART3_TX_PA0 \ 601 GD32_PINMUX_AF('A', 0, AF8) 602 #define UART3_TX_PC10 \ 603 GD32_PINMUX_AF('C', 10, AF7) 604 605 /* USART0_CK */ 606 #define USART0_CK_PA8 \ 607 GD32_PINMUX_AF('A', 8, AF7) 608 #define USART0_CK_PB5 \ 609 GD32_PINMUX_AF('B', 5, AF7) 610 611 /* USART0_CTS */ 612 #define USART0_CTS_PA11 \ 613 GD32_PINMUX_AF('A', 11, AF7) 614 #define USART0_CTS_PB4 \ 615 GD32_PINMUX_AF('B', 4, AF7) 616 617 /* USART0_DE */ 618 #define USART0_DE_PA12 \ 619 GD32_PINMUX_AF('A', 12, AF7) 620 #define USART0_DE_PB3 \ 621 GD32_PINMUX_AF('B', 3, AF7) 622 623 /* USART0_RTS */ 624 #define USART0_RTS_PA12 \ 625 GD32_PINMUX_AF('A', 12, AF7) 626 #define USART0_RTS_PB3 \ 627 GD32_PINMUX_AF('B', 3, AF7) 628 629 /* USART0_RX */ 630 #define USART0_RX_PA10 \ 631 GD32_PINMUX_AF('A', 10, AF7) 632 #define USART0_RX_PA14 \ 633 GD32_PINMUX_AF('A', 14, AF7) 634 #define USART0_RX_PB7 \ 635 GD32_PINMUX_AF('B', 7, AF7) 636 637 /* USART0_TX */ 638 #define USART0_TX_PA13 \ 639 GD32_PINMUX_AF('A', 13, AF7) 640 #define USART0_TX_PA9 \ 641 GD32_PINMUX_AF('A', 9, AF7) 642 #define USART0_TX_PB6 \ 643 GD32_PINMUX_AF('B', 6, AF7) 644 645 /* USART1_CK */ 646 #define USART1_CK_PA4 \ 647 GD32_PINMUX_AF('A', 4, AF7) 648 649 /* USART1_CTS */ 650 #define USART1_CTS_PA0 \ 651 GD32_PINMUX_AF('A', 0, AF7) 652 #define USART1_CTS_PD3 \ 653 GD32_PINMUX_AF('D', 3, AF7) 654 655 /* USART1_DE */ 656 #define USART1_DE_PA1 \ 657 GD32_PINMUX_AF('A', 1, AF7) 658 659 /* USART1_RTS */ 660 #define USART1_RTS_PA1 \ 661 GD32_PINMUX_AF('A', 1, AF7) 662 663 /* USART1_RX */ 664 #define USART1_RX_PA15 \ 665 GD32_PINMUX_AF('A', 15, AF7) 666 #define USART1_RX_PA3 \ 667 GD32_PINMUX_AF('A', 3, AF7) 668 669 /* USART1_TX */ 670 #define USART1_TX_PA14 \ 671 GD32_PINMUX_AF('A', 14, AF8) 672 #define USART1_TX_PA2 \ 673 GD32_PINMUX_AF('A', 2, AF7) 674
