1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32-af.h" 8 9 /* ADC012_IN0 */ 10 #define ADC012_IN0_PA0 \ 11 GD32_PINMUX_AF('A', 0, ANALOG) 12 13 /* ADC012_IN1 */ 14 #define ADC012_IN1_PA1 \ 15 GD32_PINMUX_AF('A', 1, ANALOG) 16 17 /* ADC012_IN10 */ 18 #define ADC012_IN10_PC0 \ 19 GD32_PINMUX_AF('C', 0, ANALOG) 20 21 /* ADC012_IN11 */ 22 #define ADC012_IN11_PC1 \ 23 GD32_PINMUX_AF('C', 1, ANALOG) 24 25 /* ADC012_IN12 */ 26 #define ADC012_IN12_PC2 \ 27 GD32_PINMUX_AF('C', 2, ANALOG) 28 29 /* ADC012_IN13 */ 30 #define ADC012_IN13_PC3 \ 31 GD32_PINMUX_AF('C', 3, ANALOG) 32 33 /* ADC012_IN2 */ 34 #define ADC012_IN2_PA2 \ 35 GD32_PINMUX_AF('A', 2, ANALOG) 36 37 /* ADC012_IN3 */ 38 #define ADC012_IN3_PA3 \ 39 GD32_PINMUX_AF('A', 3, ANALOG) 40 41 /* ADC01_IN14 */ 42 #define ADC01_IN14_PC4 \ 43 GD32_PINMUX_AF('C', 4, ANALOG) 44 45 /* ADC01_IN15 */ 46 #define ADC01_IN15_PC5 \ 47 GD32_PINMUX_AF('C', 5, ANALOG) 48 49 /* ADC01_IN4 */ 50 #define ADC01_IN4_PA4 \ 51 GD32_PINMUX_AF('A', 4, ANALOG) 52 53 /* ADC01_IN5 */ 54 #define ADC01_IN5_PA5 \ 55 GD32_PINMUX_AF('A', 5, ANALOG) 56 57 /* ADC01_IN6 */ 58 #define ADC01_IN6_PA6 \ 59 GD32_PINMUX_AF('A', 6, ANALOG) 60 61 /* ADC01_IN7 */ 62 #define ADC01_IN7_PA7 \ 63 GD32_PINMUX_AF('A', 7, ANALOG) 64 65 /* ADC01_IN8 */ 66 #define ADC01_IN8_PB0 \ 67 GD32_PINMUX_AF('B', 0, ANALOG) 68 69 /* ADC01_IN9 */ 70 #define ADC01_IN9_PB1 \ 71 GD32_PINMUX_AF('B', 1, ANALOG) 72 73 /* ANALOG */ 74 #define ANALOG_PA0 \ 75 GD32_PINMUX_AF('A', 0, ANALOG) 76 #define ANALOG_PA1 \ 77 GD32_PINMUX_AF('A', 1, ANALOG) 78 #define ANALOG_PA2 \ 79 GD32_PINMUX_AF('A', 2, ANALOG) 80 #define ANALOG_PA3 \ 81 GD32_PINMUX_AF('A', 3, ANALOG) 82 #define ANALOG_PA4 \ 83 GD32_PINMUX_AF('A', 4, ANALOG) 84 #define ANALOG_PA5 \ 85 GD32_PINMUX_AF('A', 5, ANALOG) 86 #define ANALOG_PA6 \ 87 GD32_PINMUX_AF('A', 6, ANALOG) 88 #define ANALOG_PA7 \ 89 GD32_PINMUX_AF('A', 7, ANALOG) 90 #define ANALOG_PA8 \ 91 GD32_PINMUX_AF('A', 8, ANALOG) 92 #define ANALOG_PA9 \ 93 GD32_PINMUX_AF('A', 9, ANALOG) 94 #define ANALOG_PA10 \ 95 GD32_PINMUX_AF('A', 10, ANALOG) 96 #define ANALOG_PA11 \ 97 GD32_PINMUX_AF('A', 11, ANALOG) 98 #define ANALOG_PA12 \ 99 GD32_PINMUX_AF('A', 12, ANALOG) 100 #define ANALOG_PA13 \ 101 GD32_PINMUX_AF('A', 13, ANALOG) 102 #define ANALOG_PA14 \ 103 GD32_PINMUX_AF('A', 14, ANALOG) 104 #define ANALOG_PA15 \ 105 GD32_PINMUX_AF('A', 15, ANALOG) 106 #define ANALOG_PB0 \ 107 GD32_PINMUX_AF('B', 0, ANALOG) 108 #define ANALOG_PB1 \ 109 GD32_PINMUX_AF('B', 1, ANALOG) 110 #define ANALOG_PB2 \ 111 GD32_PINMUX_AF('B', 2, ANALOG) 112 #define ANALOG_PB3 \ 113 GD32_PINMUX_AF('B', 3, ANALOG) 114 #define ANALOG_PB4 \ 115 GD32_PINMUX_AF('B', 4, ANALOG) 116 #define ANALOG_PB5 \ 117 GD32_PINMUX_AF('B', 5, ANALOG) 118 #define ANALOG_PB6 \ 119 GD32_PINMUX_AF('B', 6, ANALOG) 120 #define ANALOG_PB7 \ 121 GD32_PINMUX_AF('B', 7, ANALOG) 122 #define ANALOG_PB8 \ 123 GD32_PINMUX_AF('B', 8, ANALOG) 124 #define ANALOG_PB9 \ 125 GD32_PINMUX_AF('B', 9, ANALOG) 126 #define ANALOG_PB10 \ 127 GD32_PINMUX_AF('B', 10, ANALOG) 128 #define ANALOG_PB11 \ 129 GD32_PINMUX_AF('B', 11, ANALOG) 130 #define ANALOG_PB12 \ 131 GD32_PINMUX_AF('B', 12, ANALOG) 132 #define ANALOG_PB13 \ 133 GD32_PINMUX_AF('B', 13, ANALOG) 134 #define ANALOG_PB14 \ 135 GD32_PINMUX_AF('B', 14, ANALOG) 136 #define ANALOG_PB15 \ 137 GD32_PINMUX_AF('B', 15, ANALOG) 138 #define ANALOG_PC0 \ 139 GD32_PINMUX_AF('C', 0, ANALOG) 140 #define ANALOG_PC1 \ 141 GD32_PINMUX_AF('C', 1, ANALOG) 142 #define ANALOG_PC2 \ 143 GD32_PINMUX_AF('C', 2, ANALOG) 144 #define ANALOG_PC3 \ 145 GD32_PINMUX_AF('C', 3, ANALOG) 146 #define ANALOG_PC4 \ 147 GD32_PINMUX_AF('C', 4, ANALOG) 148 #define ANALOG_PC5 \ 149 GD32_PINMUX_AF('C', 5, ANALOG) 150 #define ANALOG_PC6 \ 151 GD32_PINMUX_AF('C', 6, ANALOG) 152 #define ANALOG_PC7 \ 153 GD32_PINMUX_AF('C', 7, ANALOG) 154 #define ANALOG_PC8 \ 155 GD32_PINMUX_AF('C', 8, ANALOG) 156 #define ANALOG_PC9 \ 157 GD32_PINMUX_AF('C', 9, ANALOG) 158 #define ANALOG_PC10 \ 159 GD32_PINMUX_AF('C', 10, ANALOG) 160 #define ANALOG_PC11 \ 161 GD32_PINMUX_AF('C', 11, ANALOG) 162 #define ANALOG_PC12 \ 163 GD32_PINMUX_AF('C', 12, ANALOG) 164 #define ANALOG_PC13 \ 165 GD32_PINMUX_AF('C', 13, ANALOG) 166 #define ANALOG_PC14 \ 167 GD32_PINMUX_AF('C', 14, ANALOG) 168 #define ANALOG_PC15 \ 169 GD32_PINMUX_AF('C', 15, ANALOG) 170 #define ANALOG_PD0 \ 171 GD32_PINMUX_AF('D', 0, ANALOG) 172 #define ANALOG_PD1 \ 173 GD32_PINMUX_AF('D', 1, ANALOG) 174 #define ANALOG_PD2 \ 175 GD32_PINMUX_AF('D', 2, ANALOG) 176 #define ANALOG_PD3 \ 177 GD32_PINMUX_AF('D', 3, ANALOG) 178 #define ANALOG_PD4 \ 179 GD32_PINMUX_AF('D', 4, ANALOG) 180 #define ANALOG_PD5 \ 181 GD32_PINMUX_AF('D', 5, ANALOG) 182 #define ANALOG_PD6 \ 183 GD32_PINMUX_AF('D', 6, ANALOG) 184 #define ANALOG_PD7 \ 185 GD32_PINMUX_AF('D', 7, ANALOG) 186 #define ANALOG_PD8 \ 187 GD32_PINMUX_AF('D', 8, ANALOG) 188 #define ANALOG_PD9 \ 189 GD32_PINMUX_AF('D', 9, ANALOG) 190 #define ANALOG_PD10 \ 191 GD32_PINMUX_AF('D', 10, ANALOG) 192 #define ANALOG_PD11 \ 193 GD32_PINMUX_AF('D', 11, ANALOG) 194 #define ANALOG_PD12 \ 195 GD32_PINMUX_AF('D', 12, ANALOG) 196 #define ANALOG_PD13 \ 197 GD32_PINMUX_AF('D', 13, ANALOG) 198 #define ANALOG_PD14 \ 199 GD32_PINMUX_AF('D', 14, ANALOG) 200 #define ANALOG_PD15 \ 201 GD32_PINMUX_AF('D', 15, ANALOG) 202 #define ANALOG_PE0 \ 203 GD32_PINMUX_AF('E', 0, ANALOG) 204 #define ANALOG_PE1 \ 205 GD32_PINMUX_AF('E', 1, ANALOG) 206 #define ANALOG_PE2 \ 207 GD32_PINMUX_AF('E', 2, ANALOG) 208 #define ANALOG_PE3 \ 209 GD32_PINMUX_AF('E', 3, ANALOG) 210 #define ANALOG_PE4 \ 211 GD32_PINMUX_AF('E', 4, ANALOG) 212 #define ANALOG_PE5 \ 213 GD32_PINMUX_AF('E', 5, ANALOG) 214 #define ANALOG_PE6 \ 215 GD32_PINMUX_AF('E', 6, ANALOG) 216 #define ANALOG_PE7 \ 217 GD32_PINMUX_AF('E', 7, ANALOG) 218 #define ANALOG_PE8 \ 219 GD32_PINMUX_AF('E', 8, ANALOG) 220 #define ANALOG_PE9 \ 221 GD32_PINMUX_AF('E', 9, ANALOG) 222 #define ANALOG_PE10 \ 223 GD32_PINMUX_AF('E', 10, ANALOG) 224 #define ANALOG_PE11 \ 225 GD32_PINMUX_AF('E', 11, ANALOG) 226 #define ANALOG_PE12 \ 227 GD32_PINMUX_AF('E', 12, ANALOG) 228 #define ANALOG_PE13 \ 229 GD32_PINMUX_AF('E', 13, ANALOG) 230 #define ANALOG_PE14 \ 231 GD32_PINMUX_AF('E', 14, ANALOG) 232 #define ANALOG_PE15 \ 233 GD32_PINMUX_AF('E', 15, ANALOG) 234 #define ANALOG_PH0 \ 235 GD32_PINMUX_AF('H', 0, ANALOG) 236 #define ANALOG_PH1 \ 237 GD32_PINMUX_AF('H', 1, ANALOG) 238 239 /* CAN0_RX */ 240 #define CAN0_RX_PA11 \ 241 GD32_PINMUX_AF('A', 11, AF9) 242 #define CAN0_RX_PB8 \ 243 GD32_PINMUX_AF('B', 8, AF9) 244 #define CAN0_RX_PD0 \ 245 GD32_PINMUX_AF('D', 0, AF9) 246 247 /* CAN0_TX */ 248 #define CAN0_TX_PA12 \ 249 GD32_PINMUX_AF('A', 12, AF9) 250 #define CAN0_TX_PB9 \ 251 GD32_PINMUX_AF('B', 9, AF9) 252 #define CAN0_TX_PD1 \ 253 GD32_PINMUX_AF('D', 1, AF9) 254 255 /* CAN1_RX */ 256 #define CAN1_RX_PB5 \ 257 GD32_PINMUX_AF('B', 5, AF9) 258 #define CAN1_RX_PB12 \ 259 GD32_PINMUX_AF('B', 12, AF9) 260 261 /* CAN1_TX */ 262 #define CAN1_TX_PB6 \ 263 GD32_PINMUX_AF('B', 6, AF9) 264 #define CAN1_TX_PB13 \ 265 GD32_PINMUX_AF('B', 13, AF9) 266 267 /* CK_OUT0 */ 268 #define CK_OUT0_PA8 \ 269 GD32_PINMUX_AF('A', 8, AF0) 270 271 /* CK_OUT1 */ 272 #define CK_OUT1_PC9 \ 273 GD32_PINMUX_AF('C', 9, AF0) 274 275 /* CTC_SYNC */ 276 #define CTC_SYNC_PA8 \ 277 GD32_PINMUX_AF('A', 8, AF9) 278 #define CTC_SYNC_PD15 \ 279 GD32_PINMUX_AF('D', 15, AF0) 280 281 /* DAC_OUT0 */ 282 #define DAC_OUT0_PA4 \ 283 GD32_PINMUX_AF('A', 4, ANALOG) 284 285 /* DAC_OUT1 */ 286 #define DAC_OUT1_PA5 \ 287 GD32_PINMUX_AF('A', 5, ANALOG) 288 289 /* DCI_D0 */ 290 #define DCI_D0_PA9 \ 291 GD32_PINMUX_AF('A', 9, AF13) 292 #define DCI_D0_PC6 \ 293 GD32_PINMUX_AF('C', 6, AF13) 294 295 /* DCI_D1 */ 296 #define DCI_D1_PA10 \ 297 GD32_PINMUX_AF('A', 10, AF13) 298 #define DCI_D1_PC7 \ 299 GD32_PINMUX_AF('C', 7, AF13) 300 301 /* DCI_D10 */ 302 #define DCI_D10_PB5 \ 303 GD32_PINMUX_AF('B', 5, AF13) 304 #define DCI_D10_PD6 \ 305 GD32_PINMUX_AF('D', 6, AF13) 306 307 /* DCI_D11 */ 308 #define DCI_D11_PD2 \ 309 GD32_PINMUX_AF('D', 2, AF13) 310 311 /* DCI_D2 */ 312 #define DCI_D2_PC8 \ 313 GD32_PINMUX_AF('C', 8, AF13) 314 #define DCI_D2_PE0 \ 315 GD32_PINMUX_AF('E', 0, AF13) 316 317 /* DCI_D3 */ 318 #define DCI_D3_PC9 \ 319 GD32_PINMUX_AF('C', 9, AF13) 320 #define DCI_D3_PE1 \ 321 GD32_PINMUX_AF('E', 1, AF13) 322 323 /* DCI_D4 */ 324 #define DCI_D4_PC11 \ 325 GD32_PINMUX_AF('C', 11, AF13) 326 #define DCI_D4_PE4 \ 327 GD32_PINMUX_AF('E', 4, AF13) 328 329 /* DCI_D5 */ 330 #define DCI_D5_PB6 \ 331 GD32_PINMUX_AF('B', 6, AF13) 332 #define DCI_D5_PD3 \ 333 GD32_PINMUX_AF('D', 3, AF13) 334 335 /* DCI_D6 */ 336 #define DCI_D6_PB8 \ 337 GD32_PINMUX_AF('B', 8, AF13) 338 #define DCI_D6_PE5 \ 339 GD32_PINMUX_AF('E', 5, AF13) 340 341 /* DCI_D7 */ 342 #define DCI_D7_PB9 \ 343 GD32_PINMUX_AF('B', 9, AF13) 344 #define DCI_D7_PE6 \ 345 GD32_PINMUX_AF('E', 6, AF13) 346 347 /* DCI_D8 */ 348 #define DCI_D8_PC10 \ 349 GD32_PINMUX_AF('C', 10, AF13) 350 351 /* DCI_D9 */ 352 #define DCI_D9_PC12 \ 353 GD32_PINMUX_AF('C', 12, AF13) 354 355 /* DCI_HSYNC */ 356 #define DCI_HSYNC_PA4 \ 357 GD32_PINMUX_AF('A', 4, AF13) 358 359 /* DCI_PIXCLK */ 360 #define DCI_PIXCLK_PA6 \ 361 GD32_PINMUX_AF('A', 6, AF13) 362 363 /* DCI_VSYNC */ 364 #define DCI_VSYNC_PB7 \ 365 GD32_PINMUX_AF('B', 7, AF13) 366 367 /* ETH_MDC */ 368 #define ETH_MDC_PC1 \ 369 GD32_PINMUX_AF('C', 1, AF11) 370 371 /* ETH_MDIO */ 372 #define ETH_MDIO_PA2 \ 373 GD32_PINMUX_AF('A', 2, AF11) 374 375 /* ETH_MII_COL */ 376 #define ETH_MII_COL_PA3 \ 377 GD32_PINMUX_AF('A', 3, AF11) 378 379 /* ETH_MII_CRS */ 380 #define ETH_MII_CRS_PA0 \ 381 GD32_PINMUX_AF('A', 0, AF11) 382 383 /* ETH_MII_RXD0 */ 384 #define ETH_MII_RXD0_PC4 \ 385 GD32_PINMUX_AF('C', 4, AF11) 386 387 /* ETH_MII_RXD1 */ 388 #define ETH_MII_RXD1_PC5 \ 389 GD32_PINMUX_AF('C', 5, AF11) 390 391 /* ETH_MII_RXD2 */ 392 #define ETH_MII_RXD2_PB0 \ 393 GD32_PINMUX_AF('B', 0, AF11) 394 395 /* ETH_MII_RXD3 */ 396 #define ETH_MII_RXD3_PB1 \ 397 GD32_PINMUX_AF('B', 1, AF11) 398 399 /* ETH_MII_RX_CLK */ 400 #define ETH_MII_RX_CLK_PA1 \ 401 GD32_PINMUX_AF('A', 1, AF11) 402 403 /* ETH_MII_RX_DV */ 404 #define ETH_MII_RX_DV_PA7 \ 405 GD32_PINMUX_AF('A', 7, AF11) 406 407 /* ETH_MII_RX_ER */ 408 #define ETH_MII_RX_ER_PB10 \ 409 GD32_PINMUX_AF('B', 10, AF11) 410 411 /* ETH_MII_TXD0 */ 412 #define ETH_MII_TXD0_PB12 \ 413 GD32_PINMUX_AF('B', 12, AF11) 414 415 /* ETH_MII_TXD1 */ 416 #define ETH_MII_TXD1_PB13 \ 417 GD32_PINMUX_AF('B', 13, AF11) 418 419 /* ETH_MII_TXD2 */ 420 #define ETH_MII_TXD2_PC2 \ 421 GD32_PINMUX_AF('C', 2, AF11) 422 423 /* ETH_MII_TXD3 */ 424 #define ETH_MII_TXD3_PB8 \ 425 GD32_PINMUX_AF('B', 8, AF11) 426 #define ETH_MII_TXD3_PE2 \ 427 GD32_PINMUX_AF('E', 2, AF11) 428 429 /* ETH_MII_TX_CLK */ 430 #define ETH_MII_TX_CLK_PC3 \ 431 GD32_PINMUX_AF('C', 3, AF11) 432 433 /* ETH_MII_TX_EN */ 434 #define ETH_MII_TX_EN_PB11 \ 435 GD32_PINMUX_AF('B', 11, AF11) 436 437 /* ETH_PPS_OUT */ 438 #define ETH_PPS_OUT_PB5 \ 439 GD32_PINMUX_AF('B', 5, AF11) 440 441 /* ETH_RMII_CRS_DV */ 442 #define ETH_RMII_CRS_DV_PA7 \ 443 GD32_PINMUX_AF('A', 7, AF11) 444 445 /* ETH_RMII_REF_CLK */ 446 #define ETH_RMII_REF_CLK_PA1 \ 447 GD32_PINMUX_AF('A', 1, AF11) 448 449 /* ETH_RMII_RXD0 */ 450 #define ETH_RMII_RXD0_PC4 \ 451 GD32_PINMUX_AF('C', 4, AF11) 452 453 /* ETH_RMII_RXD1 */ 454 #define ETH_RMII_RXD1_PC5 \ 455 GD32_PINMUX_AF('C', 5, AF11) 456 457 /* ETH_RMII_TXD0 */ 458 #define ETH_RMII_TXD0_PB12 \ 459 GD32_PINMUX_AF('B', 12, AF11) 460 461 /* ETH_RMII_TXD1 */ 462 #define ETH_RMII_TXD1_PB13 \ 463 GD32_PINMUX_AF('B', 13, AF11) 464 465 /* ETH_RMII_TX_EN */ 466 #define ETH_RMII_TX_EN_PB11 \ 467 GD32_PINMUX_AF('B', 11, AF11) 468 469 /* EVENTOUT */ 470 #define EVENTOUT_PA0 \ 471 GD32_PINMUX_AF('A', 0, AF15) 472 #define EVENTOUT_PA1 \ 473 GD32_PINMUX_AF('A', 1, AF15) 474 #define EVENTOUT_PA2 \ 475 GD32_PINMUX_AF('A', 2, AF15) 476 #define EVENTOUT_PA3 \ 477 GD32_PINMUX_AF('A', 3, AF15) 478 #define EVENTOUT_PA4 \ 479 GD32_PINMUX_AF('A', 4, AF15) 480 #define EVENTOUT_PA5 \ 481 GD32_PINMUX_AF('A', 5, AF15) 482 #define EVENTOUT_PA6 \ 483 GD32_PINMUX_AF('A', 6, AF15) 484 #define EVENTOUT_PA7 \ 485 GD32_PINMUX_AF('A', 7, AF15) 486 #define EVENTOUT_PA8 \ 487 GD32_PINMUX_AF('A', 8, AF15) 488 #define EVENTOUT_PA9 \ 489 GD32_PINMUX_AF('A', 9, AF15) 490 #define EVENTOUT_PA10 \ 491 GD32_PINMUX_AF('A', 10, AF15) 492 #define EVENTOUT_PA11 \ 493 GD32_PINMUX_AF('A', 11, AF15) 494 #define EVENTOUT_PA12 \ 495 GD32_PINMUX_AF('A', 12, AF15) 496 #define EVENTOUT_PA13 \ 497 GD32_PINMUX_AF('A', 13, AF15) 498 #define EVENTOUT_PA14 \ 499 GD32_PINMUX_AF('A', 14, AF15) 500 #define EVENTOUT_PA15 \ 501 GD32_PINMUX_AF('A', 15, AF15) 502 #define EVENTOUT_PB0 \ 503 GD32_PINMUX_AF('B', 0, AF15) 504 #define EVENTOUT_PB1 \ 505 GD32_PINMUX_AF('B', 1, AF15) 506 #define EVENTOUT_PB2 \ 507 GD32_PINMUX_AF('B', 2, AF15) 508 #define EVENTOUT_PB3 \ 509 GD32_PINMUX_AF('B', 3, AF15) 510 #define EVENTOUT_PB4 \ 511 GD32_PINMUX_AF('B', 4, AF15) 512 #define EVENTOUT_PB5 \ 513 GD32_PINMUX_AF('B', 5, AF15) 514 #define EVENTOUT_PB6 \ 515 GD32_PINMUX_AF('B', 6, AF15) 516 #define EVENTOUT_PB7 \ 517 GD32_PINMUX_AF('B', 7, AF15) 518 #define EVENTOUT_PB8 \ 519 GD32_PINMUX_AF('B', 8, AF15) 520 #define EVENTOUT_PB9 \ 521 GD32_PINMUX_AF('B', 9, AF15) 522 #define EVENTOUT_PB10 \ 523 GD32_PINMUX_AF('B', 10, AF15) 524 #define EVENTOUT_PB11 \ 525 GD32_PINMUX_AF('B', 11, AF15) 526 #define EVENTOUT_PB12 \ 527 GD32_PINMUX_AF('B', 12, AF15) 528 #define EVENTOUT_PB13 \ 529 GD32_PINMUX_AF('B', 13, AF15) 530 #define EVENTOUT_PB14 \ 531 GD32_PINMUX_AF('B', 14, AF15) 532 #define EVENTOUT_PB15 \ 533 GD32_PINMUX_AF('B', 15, AF15) 534 #define EVENTOUT_PC0 \ 535 GD32_PINMUX_AF('C', 0, AF15) 536 #define EVENTOUT_PC1 \ 537 GD32_PINMUX_AF('C', 1, AF15) 538 #define EVENTOUT_PC2 \ 539 GD32_PINMUX_AF('C', 2, AF15) 540 #define EVENTOUT_PC3 \ 541 GD32_PINMUX_AF('C', 3, AF15) 542 #define EVENTOUT_PC4 \ 543 GD32_PINMUX_AF('C', 4, AF15) 544 #define EVENTOUT_PC5 \ 545 GD32_PINMUX_AF('C', 5, AF15) 546 #define EVENTOUT_PC6 \ 547 GD32_PINMUX_AF('C', 6, AF15) 548 #define EVENTOUT_PC7 \ 549 GD32_PINMUX_AF('C', 7, AF15) 550 #define EVENTOUT_PC8 \ 551 GD32_PINMUX_AF('C', 8, AF15) 552 #define EVENTOUT_PC9 \ 553 GD32_PINMUX_AF('C', 9, AF15) 554 #define EVENTOUT_PC10 \ 555 GD32_PINMUX_AF('C', 10, AF15) 556 #define EVENTOUT_PC11 \ 557 GD32_PINMUX_AF('C', 11, AF15) 558 #define EVENTOUT_PC12 \ 559 GD32_PINMUX_AF('C', 12, AF15) 560 #define EVENTOUT_PC13 \ 561 GD32_PINMUX_AF('C', 13, AF15) 562 #define EVENTOUT_PC14 \ 563 GD32_PINMUX_AF('C', 14, AF15) 564 #define EVENTOUT_PC15 \ 565 GD32_PINMUX_AF('C', 15, AF15) 566 #define EVENTOUT_PD0 \ 567 GD32_PINMUX_AF('D', 0, AF15) 568 #define EVENTOUT_PD1 \ 569 GD32_PINMUX_AF('D', 1, AF15) 570 #define EVENTOUT_PD2 \ 571 GD32_PINMUX_AF('D', 2, AF15) 572 #define EVENTOUT_PD3 \ 573 GD32_PINMUX_AF('D', 3, AF15) 574 #define EVENTOUT_PD4 \ 575 GD32_PINMUX_AF('D', 4, AF15) 576 #define EVENTOUT_PD5 \ 577 GD32_PINMUX_AF('D', 5, AF15) 578 #define EVENTOUT_PD6 \ 579 GD32_PINMUX_AF('D', 6, AF15) 580 #define EVENTOUT_PD7 \ 581 GD32_PINMUX_AF('D', 7, AF15) 582 #define EVENTOUT_PD8 \ 583 GD32_PINMUX_AF('D', 8, AF15) 584 #define EVENTOUT_PD9 \ 585 GD32_PINMUX_AF('D', 9, AF15) 586 #define EVENTOUT_PD10 \ 587 GD32_PINMUX_AF('D', 10, AF15) 588 #define EVENTOUT_PD11 \ 589 GD32_PINMUX_AF('D', 11, AF15) 590 #define EVENTOUT_PD12 \ 591 GD32_PINMUX_AF('D', 12, AF15) 592 #define EVENTOUT_PD13 \ 593 GD32_PINMUX_AF('D', 13, AF15) 594 #define EVENTOUT_PD14 \ 595 GD32_PINMUX_AF('D', 14, AF15) 596 #define EVENTOUT_PD15 \ 597 GD32_PINMUX_AF('D', 15, AF15) 598 #define EVENTOUT_PE0 \ 599 GD32_PINMUX_AF('E', 0, AF15) 600 #define EVENTOUT_PE1 \ 601 GD32_PINMUX_AF('E', 1, AF15) 602 #define EVENTOUT_PE2 \ 603 GD32_PINMUX_AF('E', 2, AF15) 604 #define EVENTOUT_PE3 \ 605 GD32_PINMUX_AF('E', 3, AF15) 606 #define EVENTOUT_PE4 \ 607 GD32_PINMUX_AF('E', 4, AF15) 608 #define EVENTOUT_PE5 \ 609 GD32_PINMUX_AF('E', 5, AF15) 610 #define EVENTOUT_PE6 \ 611 GD32_PINMUX_AF('E', 6, AF15) 612 #define EVENTOUT_PE7 \ 613 GD32_PINMUX_AF('E', 7, AF15) 614 #define EVENTOUT_PE8 \ 615 GD32_PINMUX_AF('E', 8, AF15) 616 #define EVENTOUT_PE9 \ 617 GD32_PINMUX_AF('E', 9, AF15) 618 #define EVENTOUT_PE10 \ 619 GD32_PINMUX_AF('E', 10, AF15) 620 #define EVENTOUT_PE11 \ 621 GD32_PINMUX_AF('E', 11, AF15) 622 #define EVENTOUT_PE12 \ 623 GD32_PINMUX_AF('E', 12, AF15) 624 #define EVENTOUT_PE13 \ 625 GD32_PINMUX_AF('E', 13, AF15) 626 #define EVENTOUT_PE14 \ 627 GD32_PINMUX_AF('E', 14, AF15) 628 #define EVENTOUT_PE15 \ 629 GD32_PINMUX_AF('E', 15, AF15) 630 #define EVENTOUT_PH0 \ 631 GD32_PINMUX_AF('H', 0, AF15) 632 #define EVENTOUT_PH1 \ 633 GD32_PINMUX_AF('H', 1, AF15) 634 635 /* EXMC_A16 */ 636 #define EXMC_A16_PD11 \ 637 GD32_PINMUX_AF('D', 11, AF12) 638 639 /* EXMC_A17 */ 640 #define EXMC_A17_PD12 \ 641 GD32_PINMUX_AF('D', 12, AF12) 642 643 /* EXMC_A18 */ 644 #define EXMC_A18_PD13 \ 645 GD32_PINMUX_AF('D', 13, AF12) 646 647 /* EXMC_A19 */ 648 #define EXMC_A19_PE3 \ 649 GD32_PINMUX_AF('E', 3, AF12) 650 651 /* EXMC_A20 */ 652 #define EXMC_A20_PE4 \ 653 GD32_PINMUX_AF('E', 4, AF12) 654 655 /* EXMC_A21 */ 656 #define EXMC_A21_PE5 \ 657 GD32_PINMUX_AF('E', 5, AF12) 658 659 /* EXMC_A22 */ 660 #define EXMC_A22_PE6 \ 661 GD32_PINMUX_AF('E', 6, AF12) 662 663 /* EXMC_A23 */ 664 #define EXMC_A23_PE2 \ 665 GD32_PINMUX_AF('E', 2, AF12) 666 667 /* EXMC_CLK */ 668 #define EXMC_CLK_PD3 \ 669 GD32_PINMUX_AF('D', 3, AF12) 670 671 /* EXMC_D0 */ 672 #define EXMC_D0_PD14 \ 673 GD32_PINMUX_AF('D', 14, AF12) 674 675 /* EXMC_D1 */ 676 #define EXMC_D1_PD15 \ 677 GD32_PINMUX_AF('D', 15, AF12) 678 679 /* EXMC_D10 */ 680 #define EXMC_D10_PE13 \ 681 GD32_PINMUX_AF('E', 13, AF12) 682 683 /* EXMC_D11 */ 684 #define EXMC_D11_PE14 \ 685 GD32_PINMUX_AF('E', 14, AF12) 686 687 /* EXMC_D12 */ 688 #define EXMC_D12_PE15 \ 689 GD32_PINMUX_AF('E', 15, AF12) 690 691 /* EXMC_D13 */ 692 #define EXMC_D13_PD8 \ 693 GD32_PINMUX_AF('D', 8, AF12) 694 695 /* EXMC_D14 */ 696 #define EXMC_D14_PD9 \ 697 GD32_PINMUX_AF('D', 9, AF12) 698 699 /* EXMC_D15 */ 700 #define EXMC_D15_PD10 \ 701 GD32_PINMUX_AF('D', 10, AF12) 702 703 /* EXMC_D2 */ 704 #define EXMC_D2_PD0 \ 705 GD32_PINMUX_AF('D', 0, AF12) 706 707 /* EXMC_D3 */ 708 #define EXMC_D3_PD1 \ 709 GD32_PINMUX_AF('D', 1, AF12) 710 711 /* EXMC_D4 */ 712 #define EXMC_D4_PE7 \ 713 GD32_PINMUX_AF('E', 7, AF12) 714 715 /* EXMC_D5 */ 716 #define EXMC_D5_PE8 \ 717 GD32_PINMUX_AF('E', 8, AF12) 718 719 /* EXMC_D6 */ 720 #define EXMC_D6_PE9 \ 721 GD32_PINMUX_AF('E', 9, AF12) 722 723 /* EXMC_D7 */ 724 #define EXMC_D7_PE10 \ 725 GD32_PINMUX_AF('E', 10, AF12) 726 727 /* EXMC_D8 */ 728 #define EXMC_D8_PE11 \ 729 GD32_PINMUX_AF('E', 11, AF12) 730 731 /* EXMC_D9 */ 732 #define EXMC_D9_PE12 \ 733 GD32_PINMUX_AF('E', 12, AF12) 734 735 /* EXMC_NBL0 */ 736 #define EXMC_NBL0_PE0 \ 737 GD32_PINMUX_AF('E', 0, AF12) 738 739 /* EXMC_NBL1 */ 740 #define EXMC_NBL1_PE1 \ 741 GD32_PINMUX_AF('E', 1, AF12) 742 743 /* EXMC_NCE1 */ 744 #define EXMC_NCE1_PD7 \ 745 GD32_PINMUX_AF('D', 7, AF12) 746 747 /* EXMC_NE0 */ 748 #define EXMC_NE0_PD7 \ 749 GD32_PINMUX_AF('D', 7, AF12) 750 751 /* EXMC_NL */ 752 #define EXMC_NL_PB7 \ 753 GD32_PINMUX_AF('B', 7, AF12) 754 755 /* EXMC_NOE */ 756 #define EXMC_NOE_PD4 \ 757 GD32_PINMUX_AF('D', 4, AF12) 758 759 /* EXMC_NWAIT */ 760 #define EXMC_NWAIT_PD6 \ 761 GD32_PINMUX_AF('D', 6, AF12) 762 763 /* EXMC_NWE */ 764 #define EXMC_NWE_PD5 \ 765 GD32_PINMUX_AF('D', 5, AF12) 766 767 /* EXMC_SDCKE0 */ 768 #define EXMC_SDCKE0_PC3 \ 769 GD32_PINMUX_AF('C', 3, AF12) 770 #define EXMC_SDCKE0_PC5 \ 771 GD32_PINMUX_AF('C', 5, AF12) 772 773 /* EXMC_SDCKE1 */ 774 #define EXMC_SDCKE1_PB5 \ 775 GD32_PINMUX_AF('B', 5, AF12) 776 777 /* EXMC_SDNE0 */ 778 #define EXMC_SDNE0_PC2 \ 779 GD32_PINMUX_AF('C', 2, AF12) 780 781 /* EXMC_SDNE1 */ 782 #define EXMC_SDNE1_PB6 \ 783 GD32_PINMUX_AF('B', 6, AF12) 784 785 /* EXMC_SDNWE */ 786 #define EXMC_SDNWE_PA7 \ 787 GD32_PINMUX_AF('A', 7, AF12) 788 #define EXMC_SDNWE_PC0 \ 789 GD32_PINMUX_AF('C', 0, AF12) 790 791 /* I2C0_SCL */ 792 #define I2C0_SCL_PB6 \ 793 GD32_PINMUX_AF('B', 6, AF4) 794 #define I2C0_SCL_PB8 \ 795 GD32_PINMUX_AF('B', 8, AF4) 796 797 /* I2C0_SDA */ 798 #define I2C0_SDA_PB7 \ 799 GD32_PINMUX_AF('B', 7, AF4) 800 #define I2C0_SDA_PB9 \ 801 GD32_PINMUX_AF('B', 9, AF4) 802 803 /* I2C0_SMBA */ 804 #define I2C0_SMBA_PB5 \ 805 GD32_PINMUX_AF('B', 5, AF4) 806 807 /* I2C0_TXFRAME */ 808 #define I2C0_TXFRAME_PB4 \ 809 GD32_PINMUX_AF('B', 4, AF4) 810 811 /* I2C1_SCL */ 812 #define I2C1_SCL_PB10 \ 813 GD32_PINMUX_AF('B', 10, AF4) 814 815 /* I2C1_SDA */ 816 #define I2C1_SDA_PB3 \ 817 GD32_PINMUX_AF('B', 3, AF9) 818 #define I2C1_SDA_PB11 \ 819 GD32_PINMUX_AF('B', 11, AF4) 820 #define I2C1_SDA_PC12 \ 821 GD32_PINMUX_AF('C', 12, AF4) 822 823 /* I2C1_SMBA */ 824 #define I2C1_SMBA_PB12 \ 825 GD32_PINMUX_AF('B', 12, AF4) 826 827 /* I2C1_TXFRAME */ 828 #define I2C1_TXFRAME_PB13 \ 829 GD32_PINMUX_AF('B', 13, AF4) 830 831 /* I2C2_SCL */ 832 #define I2C2_SCL_PA8 \ 833 GD32_PINMUX_AF('A', 8, AF4) 834 835 /* I2C2_SDA */ 836 #define I2C2_SDA_PB4 \ 837 GD32_PINMUX_AF('B', 4, AF9) 838 #define I2C2_SDA_PC9 \ 839 GD32_PINMUX_AF('C', 9, AF4) 840 841 /* I2C2_SMBA */ 842 #define I2C2_SMBA_PA9 \ 843 GD32_PINMUX_AF('A', 9, AF4) 844 845 /* I2C2_TXFRAME */ 846 #define I2C2_TXFRAME_PA10 \ 847 GD32_PINMUX_AF('A', 10, AF4) 848 849 /* I2S1_ADD_SD */ 850 #define I2S1_ADD_SD_PB14 \ 851 GD32_PINMUX_AF('B', 14, AF6) 852 #define I2S1_ADD_SD_PC2 \ 853 GD32_PINMUX_AF('C', 2, AF6) 854 855 /* I2S1_CK */ 856 #define I2S1_CK_PA9 \ 857 GD32_PINMUX_AF('A', 9, AF5) 858 #define I2S1_CK_PB10 \ 859 GD32_PINMUX_AF('B', 10, AF5) 860 #define I2S1_CK_PB13 \ 861 GD32_PINMUX_AF('B', 13, AF5) 862 #define I2S1_CK_PC7 \ 863 GD32_PINMUX_AF('C', 7, AF5) 864 #define I2S1_CK_PD3 \ 865 GD32_PINMUX_AF('D', 3, AF5) 866 867 /* I2S1_MCK */ 868 #define I2S1_MCK_PA3 \ 869 GD32_PINMUX_AF('A', 3, AF5) 870 #define I2S1_MCK_PA6 \ 871 GD32_PINMUX_AF('A', 6, AF6) 872 #define I2S1_MCK_PC6 \ 873 GD32_PINMUX_AF('C', 6, AF5) 874 875 /* I2S1_NSS */ 876 #define I2S1_NSS_PB9 \ 877 GD32_PINMUX_AF('B', 9, AF5) 878 879 /* I2S1_SD */ 880 #define I2S1_SD_PB15 \ 881 GD32_PINMUX_AF('B', 15, AF5) 882 #define I2S1_SD_PC1 \ 883 GD32_PINMUX_AF('C', 1, AF7) 884 #define I2S1_SD_PC3 \ 885 GD32_PINMUX_AF('C', 3, AF5) 886 887 /* I2S1_WS */ 888 #define I2S1_WS_PB12 \ 889 GD32_PINMUX_AF('B', 12, AF5) 890 #define I2S1_WS_PD1 \ 891 GD32_PINMUX_AF('D', 1, AF7) 892 893 /* I2S2_ADD_SD */ 894 #define I2S2_ADD_SD_PB4 \ 895 GD32_PINMUX_AF('B', 4, AF7) 896 #define I2S2_ADD_SD_PC11 \ 897 GD32_PINMUX_AF('C', 11, AF5) 898 899 /* I2S2_CK */ 900 #define I2S2_CK_PB3 \ 901 GD32_PINMUX_AF('B', 3, AF6) 902 #define I2S2_CK_PC10 \ 903 GD32_PINMUX_AF('C', 10, AF6) 904 905 /* I2S2_MCK */ 906 #define I2S2_MCK_PB10 \ 907 GD32_PINMUX_AF('B', 10, AF6) 908 #define I2S2_MCK_PC7 \ 909 GD32_PINMUX_AF('C', 7, AF6) 910 911 /* I2S2_SD */ 912 #define I2S2_SD_PB0 \ 913 GD32_PINMUX_AF('B', 0, AF7) 914 #define I2S2_SD_PB2 \ 915 GD32_PINMUX_AF('B', 2, AF7) 916 #define I2S2_SD_PB5 \ 917 GD32_PINMUX_AF('B', 5, AF6) 918 #define I2S2_SD_PC1 \ 919 GD32_PINMUX_AF('C', 1, AF5) 920 #define I2S2_SD_PC12 \ 921 GD32_PINMUX_AF('C', 12, AF6) 922 #define I2S2_SD_PD0 \ 923 GD32_PINMUX_AF('D', 0, AF6) 924 #define I2S2_SD_PD6 \ 925 GD32_PINMUX_AF('D', 6, AF5) 926 927 /* I2S2_WS */ 928 #define I2S2_WS_PA4 \ 929 GD32_PINMUX_AF('A', 4, AF6) 930 #define I2S2_WS_PA15 \ 931 GD32_PINMUX_AF('A', 15, AF6) 932 933 /* I2S_CKIN */ 934 #define I2S_CKIN_PA2 \ 935 GD32_PINMUX_AF('A', 2, AF5) 936 #define I2S_CKIN_PB11 \ 937 GD32_PINMUX_AF('B', 11, AF5) 938 #define I2S_CKIN_PC9 \ 939 GD32_PINMUX_AF('C', 9, AF5) 940 941 /* JNTRST */ 942 #define JNTRST_PB4 \ 943 GD32_PINMUX_AF('B', 4, AF0) 944 945 /* JTCK */ 946 #define JTCK_PA14 \ 947 GD32_PINMUX_AF('A', 14, AF0) 948 949 /* JTDI */ 950 #define JTDI_PA15 \ 951 GD32_PINMUX_AF('A', 15, AF0) 952 953 /* JTDO */ 954 #define JTDO_PB3 \ 955 GD32_PINMUX_AF('B', 3, AF0) 956 957 /* JTMS */ 958 #define JTMS_PA13 \ 959 GD32_PINMUX_AF('A', 13, AF0) 960 961 /* RTC_REFIN */ 962 #define RTC_REFIN_PB15 \ 963 GD32_PINMUX_AF('B', 15, AF0) 964 965 /* SDIO_CK */ 966 #define SDIO_CK_PB2 \ 967 GD32_PINMUX_AF('B', 2, AF12) 968 #define SDIO_CK_PC12 \ 969 GD32_PINMUX_AF('C', 12, AF12) 970 971 /* SDIO_CMD */ 972 #define SDIO_CMD_PA6 \ 973 GD32_PINMUX_AF('A', 6, AF12) 974 #define SDIO_CMD_PD2 \ 975 GD32_PINMUX_AF('D', 2, AF12) 976 977 /* SDIO_D0 */ 978 #define SDIO_D0_PB4 \ 979 GD32_PINMUX_AF('B', 4, AF12) 980 #define SDIO_D0_PC8 \ 981 GD32_PINMUX_AF('C', 8, AF12) 982 983 /* SDIO_D1 */ 984 #define SDIO_D1_PA8 \ 985 GD32_PINMUX_AF('A', 8, AF12) 986 #define SDIO_D1_PB0 \ 987 GD32_PINMUX_AF('B', 0, AF12) 988 #define SDIO_D1_PC9 \ 989 GD32_PINMUX_AF('C', 9, AF12) 990 991 /* SDIO_D2 */ 992 #define SDIO_D2_PA9 \ 993 GD32_PINMUX_AF('A', 9, AF12) 994 #define SDIO_D2_PB1 \ 995 GD32_PINMUX_AF('B', 1, AF12) 996 #define SDIO_D2_PC10 \ 997 GD32_PINMUX_AF('C', 10, AF12) 998 999 /* SDIO_D3 */ 1000 #define SDIO_D3_PC11 \ 1001 GD32_PINMUX_AF('C', 11, AF12) 1002 1003 /* SDIO_D4 */ 1004 #define SDIO_D4_PB8 \ 1005 GD32_PINMUX_AF('B', 8, AF12) 1006 1007 /* SDIO_D5 */ 1008 #define SDIO_D5_PB9 \ 1009 GD32_PINMUX_AF('B', 9, AF12) 1010 1011 /* SDIO_D6 */ 1012 #define SDIO_D6_PC6 \ 1013 GD32_PINMUX_AF('C', 6, AF12) 1014 1015 /* SDIO_D7 */ 1016 #define SDIO_D7_PB10 \ 1017 GD32_PINMUX_AF('B', 10, AF12) 1018 #define SDIO_D7_PC7 \ 1019 GD32_PINMUX_AF('C', 7, AF12) 1020 1021 /* SPI0_MISO */ 1022 #define SPI0_MISO_PA6 \ 1023 GD32_PINMUX_AF('A', 6, AF5) 1024 #define SPI0_MISO_PB4 \ 1025 GD32_PINMUX_AF('B', 4, AF5) 1026 1027 /* SPI0_MOSI */ 1028 #define SPI0_MOSI_PA7 \ 1029 GD32_PINMUX_AF('A', 7, AF5) 1030 #define SPI0_MOSI_PB5 \ 1031 GD32_PINMUX_AF('B', 5, AF5) 1032 1033 /* SPI0_NSS */ 1034 #define SPI0_NSS_PA4 \ 1035 GD32_PINMUX_AF('A', 4, AF5) 1036 #define SPI0_NSS_PA15 \ 1037 GD32_PINMUX_AF('A', 15, AF5) 1038 1039 /* SPI0_SCK */ 1040 #define SPI0_SCK_PA5 \ 1041 GD32_PINMUX_AF('A', 5, AF5) 1042 #define SPI0_SCK_PB3 \ 1043 GD32_PINMUX_AF('B', 3, AF5) 1044 1045 /* SPI1_MISO */ 1046 #define SPI1_MISO_PB14 \ 1047 GD32_PINMUX_AF('B', 14, AF5) 1048 #define SPI1_MISO_PC2 \ 1049 GD32_PINMUX_AF('C', 2, AF5) 1050 1051 /* SPI1_MOSI */ 1052 #define SPI1_MOSI_PB15 \ 1053 GD32_PINMUX_AF('B', 15, AF5) 1054 #define SPI1_MOSI_PC1 \ 1055 GD32_PINMUX_AF('C', 1, AF7) 1056 #define SPI1_MOSI_PC3 \ 1057 GD32_PINMUX_AF('C', 3, AF5) 1058 1059 /* SPI1_NSS */ 1060 #define SPI1_NSS_PB9 \ 1061 GD32_PINMUX_AF('B', 9, AF5) 1062 #define SPI1_NSS_PB12 \ 1063 GD32_PINMUX_AF('B', 12, AF5) 1064 #define SPI1_NSS_PD1 \ 1065 GD32_PINMUX_AF('D', 1, AF7) 1066 1067 /* SPI1_SCK */ 1068 #define SPI1_SCK_PA9 \ 1069 GD32_PINMUX_AF('A', 9, AF5) 1070 #define SPI1_SCK_PB10 \ 1071 GD32_PINMUX_AF('B', 10, AF5) 1072 #define SPI1_SCK_PB13 \ 1073 GD32_PINMUX_AF('B', 13, AF5) 1074 #define SPI1_SCK_PC7 \ 1075 GD32_PINMUX_AF('C', 7, AF5) 1076 #define SPI1_SCK_PD3 \ 1077 GD32_PINMUX_AF('D', 3, AF5) 1078 1079 /* SPI2_MISO */ 1080 #define SPI2_MISO_PB4 \ 1081 GD32_PINMUX_AF('B', 4, AF6) 1082 #define SPI2_MISO_PC11 \ 1083 GD32_PINMUX_AF('C', 11, AF6) 1084 1085 /* SPI2_MOSI */ 1086 #define SPI2_MOSI_PB0 \ 1087 GD32_PINMUX_AF('B', 0, AF7) 1088 #define SPI2_MOSI_PB2 \ 1089 GD32_PINMUX_AF('B', 2, AF7) 1090 #define SPI2_MOSI_PB5 \ 1091 GD32_PINMUX_AF('B', 5, AF6) 1092 #define SPI2_MOSI_PC1 \ 1093 GD32_PINMUX_AF('C', 1, AF5) 1094 #define SPI2_MOSI_PC12 \ 1095 GD32_PINMUX_AF('C', 12, AF6) 1096 #define SPI2_MOSI_PD0 \ 1097 GD32_PINMUX_AF('D', 0, AF6) 1098 #define SPI2_MOSI_PD6 \ 1099 GD32_PINMUX_AF('D', 6, AF5) 1100 1101 /* SPI2_NSS */ 1102 #define SPI2_NSS_PA4 \ 1103 GD32_PINMUX_AF('A', 4, AF6) 1104 #define SPI2_NSS_PA15 \ 1105 GD32_PINMUX_AF('A', 15, AF6) 1106 1107 /* SPI2_SCK */ 1108 #define SPI2_SCK_PB3 \ 1109 GD32_PINMUX_AF('B', 3, AF6) 1110 #define SPI2_SCK_PC10 \ 1111 GD32_PINMUX_AF('C', 10, AF6) 1112 1113 /* SPI3_MISO */ 1114 #define SPI3_MISO_PA11 \ 1115 GD32_PINMUX_AF('A', 11, AF6) 1116 #define SPI3_MISO_PD0 \ 1117 GD32_PINMUX_AF('D', 0, AF5) 1118 #define SPI3_MISO_PE5 \ 1119 GD32_PINMUX_AF('E', 5, AF5) 1120 #define SPI3_MISO_PE13 \ 1121 GD32_PINMUX_AF('E', 13, AF5) 1122 1123 /* SPI3_MOSI */ 1124 #define SPI3_MOSI_PA1 \ 1125 GD32_PINMUX_AF('A', 1, AF5) 1126 #define SPI3_MOSI_PE6 \ 1127 GD32_PINMUX_AF('E', 6, AF5) 1128 #define SPI3_MOSI_PE14 \ 1129 GD32_PINMUX_AF('E', 14, AF5) 1130 1131 /* SPI3_NSS */ 1132 #define SPI3_NSS_PB12 \ 1133 GD32_PINMUX_AF('B', 12, AF6) 1134 #define SPI3_NSS_PE4 \ 1135 GD32_PINMUX_AF('E', 4, AF5) 1136 #define SPI3_NSS_PE11 \ 1137 GD32_PINMUX_AF('E', 11, AF5) 1138 1139 /* SPI3_SCK */ 1140 #define SPI3_SCK_PB13 \ 1141 GD32_PINMUX_AF('B', 13, AF6) 1142 #define SPI3_SCK_PE2 \ 1143 GD32_PINMUX_AF('E', 2, AF5) 1144 #define SPI3_SCK_PE12 \ 1145 GD32_PINMUX_AF('E', 12, AF5) 1146 1147 /* SPI4_MISO */ 1148 #define SPI4_MISO_PA12 \ 1149 GD32_PINMUX_AF('A', 12, AF6) 1150 #define SPI4_MISO_PE13 \ 1151 GD32_PINMUX_AF('E', 13, AF6) 1152 1153 /* SPI4_MOSI */ 1154 #define SPI4_MOSI_PA10 \ 1155 GD32_PINMUX_AF('A', 10, AF6) 1156 #define SPI4_MOSI_PB8 \ 1157 GD32_PINMUX_AF('B', 8, AF6) 1158 #define SPI4_MOSI_PE14 \ 1159 GD32_PINMUX_AF('E', 14, AF6) 1160 1161 /* SPI4_NSS */ 1162 #define SPI4_NSS_PB1 \ 1163 GD32_PINMUX_AF('B', 1, AF6) 1164 #define SPI4_NSS_PE11 \ 1165 GD32_PINMUX_AF('E', 11, AF6) 1166 1167 /* SPI4_SCK */ 1168 #define SPI4_SCK_PB0 \ 1169 GD32_PINMUX_AF('B', 0, AF6) 1170 #define SPI4_SCK_PE12 \ 1171 GD32_PINMUX_AF('E', 12, AF6) 1172 1173 /* SWCLK */ 1174 #define SWCLK_PA14 \ 1175 GD32_PINMUX_AF('A', 14, AF0) 1176 1177 /* SWDIO */ 1178 #define SWDIO_PA13 \ 1179 GD32_PINMUX_AF('A', 13, AF0) 1180 1181 /* TIMER0_BRKIN */ 1182 #define TIMER0_BRKIN_PA6 \ 1183 GD32_PINMUX_AF('A', 6, AF1) 1184 #define TIMER0_BRKIN_PB12 \ 1185 GD32_PINMUX_AF('B', 12, AF1) 1186 #define TIMER0_BRKIN_PE15 \ 1187 GD32_PINMUX_AF('E', 15, AF1) 1188 1189 /* TIMER0_CH0 */ 1190 #define TIMER0_CH0_PA8 \ 1191 GD32_PINMUX_AF('A', 8, AF1) 1192 #define TIMER0_CH0_PE9 \ 1193 GD32_PINMUX_AF('E', 9, AF1) 1194 1195 /* TIMER0_CH0_ON */ 1196 #define TIMER0_CH0_ON_PA7 \ 1197 GD32_PINMUX_AF('A', 7, AF1) 1198 #define TIMER0_CH0_ON_PB13 \ 1199 GD32_PINMUX_AF('B', 13, AF1) 1200 #define TIMER0_CH0_ON_PE8 \ 1201 GD32_PINMUX_AF('E', 8, AF1) 1202 1203 /* TIMER0_CH1 */ 1204 #define TIMER0_CH1_PA9 \ 1205 GD32_PINMUX_AF('A', 9, AF1) 1206 #define TIMER0_CH1_PE11 \ 1207 GD32_PINMUX_AF('E', 11, AF1) 1208 1209 /* TIMER0_CH1_ON */ 1210 #define TIMER0_CH1_ON_PB0 \ 1211 GD32_PINMUX_AF('B', 0, AF1) 1212 #define TIMER0_CH1_ON_PB1 \ 1213 GD32_PINMUX_AF('B', 1, AF1) 1214 #define TIMER0_CH1_ON_PB14 \ 1215 GD32_PINMUX_AF('B', 14, AF1) 1216 #define TIMER0_CH1_ON_PE1 \ 1217 GD32_PINMUX_AF('E', 1, AF1) 1218 #define TIMER0_CH1_ON_PE10 \ 1219 GD32_PINMUX_AF('E', 10, AF1) 1220 1221 /* TIMER0_CH2 */ 1222 #define TIMER0_CH2_PA10 \ 1223 GD32_PINMUX_AF('A', 10, AF1) 1224 #define TIMER0_CH2_PE13 \ 1225 GD32_PINMUX_AF('E', 13, AF1) 1226 1227 /* TIMER0_CH2_ON */ 1228 #define TIMER0_CH2_ON_PB15 \ 1229 GD32_PINMUX_AF('B', 15, AF1) 1230 #define TIMER0_CH2_ON_PE12 \ 1231 GD32_PINMUX_AF('E', 12, AF1) 1232 1233 /* TIMER0_CH3 */ 1234 #define TIMER0_CH3_PA11 \ 1235 GD32_PINMUX_AF('A', 11, AF1) 1236 #define TIMER0_CH3_PE14 \ 1237 GD32_PINMUX_AF('E', 14, AF1) 1238 1239 /* TIMER0_ETI */ 1240 #define TIMER0_ETI_PA12 \ 1241 GD32_PINMUX_AF('A', 12, AF1) 1242 #define TIMER0_ETI_PE7 \ 1243 GD32_PINMUX_AF('E', 7, AF1) 1244 1245 /* TIMER10_CH0 */ 1246 #define TIMER10_CH0_PB9 \ 1247 GD32_PINMUX_AF('B', 9, AF3) 1248 1249 /* TIMER11_CH0 */ 1250 #define TIMER11_CH0_PB14 \ 1251 GD32_PINMUX_AF('B', 14, AF9) 1252 1253 /* TIMER11_CH1 */ 1254 #define TIMER11_CH1_PB15 \ 1255 GD32_PINMUX_AF('B', 15, AF9) 1256 1257 /* TIMER12_CH0 */ 1258 #define TIMER12_CH0_PA6 \ 1259 GD32_PINMUX_AF('A', 6, AF9) 1260 1261 /* TIMER13_CH0 */ 1262 #define TIMER13_CH0_PA7 \ 1263 GD32_PINMUX_AF('A', 7, AF9) 1264 1265 /* TIMER1_CH0 */ 1266 #define TIMER1_CH0_PA0 \ 1267 GD32_PINMUX_AF('A', 0, AF1) 1268 #define TIMER1_CH0_PA5 \ 1269 GD32_PINMUX_AF('A', 5, AF1) 1270 #define TIMER1_CH0_PA15 \ 1271 GD32_PINMUX_AF('A', 15, AF1) 1272 #define TIMER1_CH0_PB8 \ 1273 GD32_PINMUX_AF('B', 8, AF1) 1274 1275 /* TIMER1_CH1 */ 1276 #define TIMER1_CH1_PA1 \ 1277 GD32_PINMUX_AF('A', 1, AF1) 1278 #define TIMER1_CH1_PB3 \ 1279 GD32_PINMUX_AF('B', 3, AF1) 1280 #define TIMER1_CH1_PB9 \ 1281 GD32_PINMUX_AF('B', 9, AF1) 1282 1283 /* TIMER1_CH2 */ 1284 #define TIMER1_CH2_PA2 \ 1285 GD32_PINMUX_AF('A', 2, AF1) 1286 #define TIMER1_CH2_PB10 \ 1287 GD32_PINMUX_AF('B', 10, AF1) 1288 1289 /* TIMER1_CH3 */ 1290 #define TIMER1_CH3_PA3 \ 1291 GD32_PINMUX_AF('A', 3, AF1) 1292 #define TIMER1_CH3_PB2 \ 1293 GD32_PINMUX_AF('B', 2, AF1) 1294 #define TIMER1_CH3_PB11 \ 1295 GD32_PINMUX_AF('B', 11, AF1) 1296 1297 /* TIMER1_ETI */ 1298 #define TIMER1_ETI_PA0 \ 1299 GD32_PINMUX_AF('A', 0, AF1) 1300 #define TIMER1_ETI_PA5 \ 1301 GD32_PINMUX_AF('A', 5, AF1) 1302 #define TIMER1_ETI_PA15 \ 1303 GD32_PINMUX_AF('A', 15, AF1) 1304 #define TIMER1_ETI_PB8 \ 1305 GD32_PINMUX_AF('B', 8, AF1) 1306 1307 /* TIMER2_CH0 */ 1308 #define TIMER2_CH0_PA6 \ 1309 GD32_PINMUX_AF('A', 6, AF2) 1310 #define TIMER2_CH0_PB4 \ 1311 GD32_PINMUX_AF('B', 4, AF2) 1312 #define TIMER2_CH0_PC6 \ 1313 GD32_PINMUX_AF('C', 6, AF2) 1314 1315 /* TIMER2_CH1 */ 1316 #define TIMER2_CH1_PA7 \ 1317 GD32_PINMUX_AF('A', 7, AF2) 1318 #define TIMER2_CH1_PB5 \ 1319 GD32_PINMUX_AF('B', 5, AF2) 1320 #define TIMER2_CH1_PC7 \ 1321 GD32_PINMUX_AF('C', 7, AF2) 1322 1323 /* TIMER2_CH2 */ 1324 #define TIMER2_CH2_PB0 \ 1325 GD32_PINMUX_AF('B', 0, AF2) 1326 #define TIMER2_CH2_PC8 \ 1327 GD32_PINMUX_AF('C', 8, AF2) 1328 1329 /* TIMER2_CH3 */ 1330 #define TIMER2_CH3_PB1 \ 1331 GD32_PINMUX_AF('B', 1, AF2) 1332 #define TIMER2_CH3_PC9 \ 1333 GD32_PINMUX_AF('C', 9, AF2) 1334 1335 /* TIMER2_ETI */ 1336 #define TIMER2_ETI_PD2 \ 1337 GD32_PINMUX_AF('D', 2, AF2) 1338 1339 /* TIMER3_CH0 */ 1340 #define TIMER3_CH0_PB6 \ 1341 GD32_PINMUX_AF('B', 6, AF2) 1342 #define TIMER3_CH0_PD12 \ 1343 GD32_PINMUX_AF('D', 12, AF2) 1344 1345 /* TIMER3_CH1 */ 1346 #define TIMER3_CH1_PB7 \ 1347 GD32_PINMUX_AF('B', 7, AF2) 1348 #define TIMER3_CH1_PD13 \ 1349 GD32_PINMUX_AF('D', 13, AF2) 1350 1351 /* TIMER3_CH2 */ 1352 #define TIMER3_CH2_PB8 \ 1353 GD32_PINMUX_AF('B', 8, AF2) 1354 #define TIMER3_CH2_PD14 \ 1355 GD32_PINMUX_AF('D', 14, AF2) 1356 1357 /* TIMER3_CH3 */ 1358 #define TIMER3_CH3_PB9 \ 1359 GD32_PINMUX_AF('B', 9, AF2) 1360 #define TIMER3_CH3_PD15 \ 1361 GD32_PINMUX_AF('D', 15, AF2) 1362 1363 /* TIMER3_ETI */ 1364 #define TIMER3_ETI_PE0 \ 1365 GD32_PINMUX_AF('E', 0, AF2) 1366 1367 /* TIMER4_CH0 */ 1368 #define TIMER4_CH0_PA0 \ 1369 GD32_PINMUX_AF('A', 0, AF2) 1370 1371 /* TIMER4_CH1 */ 1372 #define TIMER4_CH1_PA1 \ 1373 GD32_PINMUX_AF('A', 1, AF2) 1374 1375 /* TIMER4_CH2 */ 1376 #define TIMER4_CH2_PA2 \ 1377 GD32_PINMUX_AF('A', 2, AF2) 1378 1379 /* TIMER4_CH3 */ 1380 #define TIMER4_CH3_PA3 \ 1381 GD32_PINMUX_AF('A', 3, AF2) 1382 1383 /* TIMER7_BRKIN */ 1384 #define TIMER7_BRKIN_PA6 \ 1385 GD32_PINMUX_AF('A', 6, AF3) 1386 1387 /* TIMER7_CH0 */ 1388 #define TIMER7_CH0_PC6 \ 1389 GD32_PINMUX_AF('C', 6, AF3) 1390 1391 /* TIMER7_CH0_ON */ 1392 #define TIMER7_CH0_ON_PA5 \ 1393 GD32_PINMUX_AF('A', 5, AF3) 1394 #define TIMER7_CH0_ON_PA7 \ 1395 GD32_PINMUX_AF('A', 7, AF3) 1396 1397 /* TIMER7_CH1 */ 1398 #define TIMER7_CH1_PC7 \ 1399 GD32_PINMUX_AF('C', 7, AF3) 1400 1401 /* TIMER7_CH1_ON */ 1402 #define TIMER7_CH1_ON_PB0 \ 1403 GD32_PINMUX_AF('B', 0, AF3) 1404 #define TIMER7_CH1_ON_PB14 \ 1405 GD32_PINMUX_AF('B', 14, AF3) 1406 1407 /* TIMER7_CH2 */ 1408 #define TIMER7_CH2_PC8 \ 1409 GD32_PINMUX_AF('C', 8, AF3) 1410 1411 /* TIMER7_CH2_ON */ 1412 #define TIMER7_CH2_ON_PB1 \ 1413 GD32_PINMUX_AF('B', 1, AF3) 1414 #define TIMER7_CH2_ON_PB15 \ 1415 GD32_PINMUX_AF('B', 15, AF3) 1416 1417 /* TIMER7_CH3 */ 1418 #define TIMER7_CH3_PC9 \ 1419 GD32_PINMUX_AF('C', 9, AF3) 1420 1421 /* TIMER7_ETI */ 1422 #define TIMER7_ETI_PA0 \ 1423 GD32_PINMUX_AF('A', 0, AF3) 1424 1425 /* TIMER8_CH0 */ 1426 #define TIMER8_CH0_PA2 \ 1427 GD32_PINMUX_AF('A', 2, AF3) 1428 #define TIMER8_CH0_PE5 \ 1429 GD32_PINMUX_AF('E', 5, AF3) 1430 1431 /* TIMER8_CH1 */ 1432 #define TIMER8_CH1_PA3 \ 1433 GD32_PINMUX_AF('A', 3, AF3) 1434 #define TIMER8_CH1_PE6 \ 1435 GD32_PINMUX_AF('E', 6, AF3) 1436 1437 /* TIMER9_CH0 */ 1438 #define TIMER9_CH0_PB8 \ 1439 GD32_PINMUX_AF('B', 8, AF3) 1440 1441 /* TLI_B0 */ 1442 #define TLI_B0_PE4 \ 1443 GD32_PINMUX_AF('E', 4, AF14) 1444 1445 /* TLI_B2 */ 1446 #define TLI_B2_PD6 \ 1447 GD32_PINMUX_AF('D', 6, AF14) 1448 1449 /* TLI_B3 */ 1450 #define TLI_B3_PD10 \ 1451 GD32_PINMUX_AF('D', 10, AF14) 1452 1453 /* TLI_B4 */ 1454 #define TLI_B4_PE12 \ 1455 GD32_PINMUX_AF('E', 12, AF14) 1456 1457 /* TLI_B5 */ 1458 #define TLI_B5_PA3 \ 1459 GD32_PINMUX_AF('A', 3, AF14) 1460 1461 /* TLI_B6 */ 1462 #define TLI_B6_PB8 \ 1463 GD32_PINMUX_AF('B', 8, AF14) 1464 1465 /* TLI_B7 */ 1466 #define TLI_B7_PB9 \ 1467 GD32_PINMUX_AF('B', 9, AF14) 1468 1469 /* TLI_DE */ 1470 #define TLI_DE_PE13 \ 1471 GD32_PINMUX_AF('E', 13, AF14) 1472 1473 /* TLI_G0 */ 1474 #define TLI_G0_PE5 \ 1475 GD32_PINMUX_AF('E', 5, AF14) 1476 1477 /* TLI_G1 */ 1478 #define TLI_G1_PE6 \ 1479 GD32_PINMUX_AF('E', 6, AF14) 1480 1481 /* TLI_G2 */ 1482 #define TLI_G2_PA6 \ 1483 GD32_PINMUX_AF('A', 6, AF14) 1484 1485 /* TLI_G3 */ 1486 #define TLI_G3_PE11 \ 1487 GD32_PINMUX_AF('E', 11, AF14) 1488 1489 /* TLI_G4 */ 1490 #define TLI_G4_PB10 \ 1491 GD32_PINMUX_AF('B', 10, AF14) 1492 1493 /* TLI_G5 */ 1494 #define TLI_G5_PB11 \ 1495 GD32_PINMUX_AF('B', 11, AF14) 1496 1497 /* TLI_G6 */ 1498 #define TLI_G6_PC7 \ 1499 GD32_PINMUX_AF('C', 7, AF14) 1500 1501 /* TLI_G7 */ 1502 #define TLI_G7_PD3 \ 1503 GD32_PINMUX_AF('D', 3, AF14) 1504 1505 /* TLI_HSYNC */ 1506 #define TLI_HSYNC_PC6 \ 1507 GD32_PINMUX_AF('C', 6, AF14) 1508 1509 /* TLI_PIXCLK */ 1510 #define TLI_PIXCLK_PE14 \ 1511 GD32_PINMUX_AF('E', 14, AF14) 1512 1513 /* TLI_R2 */ 1514 #define TLI_R2_PC10 \ 1515 GD32_PINMUX_AF('C', 10, AF14) 1516 1517 /* TLI_R3 */ 1518 #define TLI_R3_PB0 \ 1519 GD32_PINMUX_AF('B', 0, AF9) 1520 1521 /* TLI_R4 */ 1522 #define TLI_R4_PA11 \ 1523 GD32_PINMUX_AF('A', 11, AF14) 1524 1525 /* TLI_R5 */ 1526 #define TLI_R5_PA12 \ 1527 GD32_PINMUX_AF('A', 12, AF14) 1528 1529 /* TLI_R6 */ 1530 #define TLI_R6_PA8 \ 1531 GD32_PINMUX_AF('A', 8, AF14) 1532 #define TLI_R6_PB1 \ 1533 GD32_PINMUX_AF('B', 1, AF9) 1534 1535 /* TLI_R7 */ 1536 #define TLI_R7_PE15 \ 1537 GD32_PINMUX_AF('E', 15, AF14) 1538 1539 /* TLI_VSYNC */ 1540 #define TLI_VSYNC_PA4 \ 1541 GD32_PINMUX_AF('A', 4, AF14) 1542 1543 /* TRACESWO */ 1544 #define TRACESWO_PB3 \ 1545 GD32_PINMUX_AF('B', 3, AF0) 1546 1547 /* UART3_RX */ 1548 #define UART3_RX_PA1 \ 1549 GD32_PINMUX_AF('A', 1, AF8) 1550 #define UART3_RX_PC11 \ 1551 GD32_PINMUX_AF('C', 11, AF8) 1552 1553 /* UART3_TX */ 1554 #define UART3_TX_PA0 \ 1555 GD32_PINMUX_AF('A', 0, AF8) 1556 #define UART3_TX_PC10 \ 1557 GD32_PINMUX_AF('C', 10, AF8) 1558 1559 /* UART4_RX */ 1560 #define UART4_RX_PC12 \ 1561 GD32_PINMUX_AF('C', 12, AF8) 1562 #define UART4_RX_PD2 \ 1563 GD32_PINMUX_AF('D', 2, AF8) 1564 1565 /* UART6_RX */ 1566 #define UART6_RX_PE7 \ 1567 GD32_PINMUX_AF('E', 7, AF8) 1568 1569 /* UART6_TX */ 1570 #define UART6_TX_PE8 \ 1571 GD32_PINMUX_AF('E', 8, AF8) 1572 1573 /* UART7_RX */ 1574 #define UART7_RX_PE0 \ 1575 GD32_PINMUX_AF('E', 0, AF8) 1576 1577 /* UART7_TX */ 1578 #define UART7_TX_PE1 \ 1579 GD32_PINMUX_AF('E', 1, AF8) 1580 1581 /* USART0_CK */ 1582 #define USART0_CK_PA8 \ 1583 GD32_PINMUX_AF('A', 8, AF7) 1584 1585 /* USART0_CTS */ 1586 #define USART0_CTS_PA11 \ 1587 GD32_PINMUX_AF('A', 11, AF7) 1588 1589 /* USART0_RTS */ 1590 #define USART0_RTS_PA12 \ 1591 GD32_PINMUX_AF('A', 12, AF7) 1592 1593 /* USART0_RX */ 1594 #define USART0_RX_PA10 \ 1595 GD32_PINMUX_AF('A', 10, AF7) 1596 #define USART0_RX_PB3 \ 1597 GD32_PINMUX_AF('B', 3, AF7) 1598 #define USART0_RX_PB7 \ 1599 GD32_PINMUX_AF('B', 7, AF7) 1600 1601 /* USART0_TX */ 1602 #define USART0_TX_PA9 \ 1603 GD32_PINMUX_AF('A', 9, AF7) 1604 #define USART0_TX_PA15 \ 1605 GD32_PINMUX_AF('A', 15, AF7) 1606 #define USART0_TX_PB6 \ 1607 GD32_PINMUX_AF('B', 6, AF7) 1608 1609 /* USART1_CK */ 1610 #define USART1_CK_PA4 \ 1611 GD32_PINMUX_AF('A', 4, AF7) 1612 #define USART1_CK_PD7 \ 1613 GD32_PINMUX_AF('D', 7, AF7) 1614 1615 /* USART1_CTS */ 1616 #define USART1_CTS_PA0 \ 1617 GD32_PINMUX_AF('A', 0, AF7) 1618 #define USART1_CTS_PD3 \ 1619 GD32_PINMUX_AF('D', 3, AF7) 1620 1621 /* USART1_RTS */ 1622 #define USART1_RTS_PA1 \ 1623 GD32_PINMUX_AF('A', 1, AF7) 1624 #define USART1_RTS_PD4 \ 1625 GD32_PINMUX_AF('D', 4, AF7) 1626 1627 /* USART1_RX */ 1628 #define USART1_RX_PA3 \ 1629 GD32_PINMUX_AF('A', 3, AF7) 1630 #define USART1_RX_PD6 \ 1631 GD32_PINMUX_AF('D', 6, AF7) 1632 1633 /* USART1_TX */ 1634 #define USART1_TX_PA2 \ 1635 GD32_PINMUX_AF('A', 2, AF7) 1636 #define USART1_TX_PD5 \ 1637 GD32_PINMUX_AF('D', 5, AF7) 1638 1639 /* USART2_CK */ 1640 #define USART2_CK_PB12 \ 1641 GD32_PINMUX_AF('B', 12, AF7) 1642 #define USART2_CK_PC12 \ 1643 GD32_PINMUX_AF('C', 12, AF7) 1644 #define USART2_CK_PD10 \ 1645 GD32_PINMUX_AF('D', 10, AF7) 1646 1647 /* USART2_CTS */ 1648 #define USART2_CTS_PB13 \ 1649 GD32_PINMUX_AF('B', 13, AF7) 1650 #define USART2_CTS_PD11 \ 1651 GD32_PINMUX_AF('D', 11, AF7) 1652 1653 /* USART2_RTS */ 1654 #define USART2_RTS_PB14 \ 1655 GD32_PINMUX_AF('B', 14, AF7) 1656 #define USART2_RTS_PD12 \ 1657 GD32_PINMUX_AF('D', 12, AF7) 1658 1659 /* USART2_RX */ 1660 #define USART2_RX_PB11 \ 1661 GD32_PINMUX_AF('B', 11, AF7) 1662 #define USART2_RX_PC5 \ 1663 GD32_PINMUX_AF('C', 5, AF7) 1664 #define USART2_RX_PC11 \ 1665 GD32_PINMUX_AF('C', 11, AF7) 1666 #define USART2_RX_PD9 \ 1667 GD32_PINMUX_AF('D', 9, AF7) 1668 1669 /* USART2_TX */ 1670 #define USART2_TX_PB10 \ 1671 GD32_PINMUX_AF('B', 10, AF7) 1672 #define USART2_TX_PC10 \ 1673 GD32_PINMUX_AF('C', 10, AF7) 1674 #define USART2_TX_PD8 \ 1675 GD32_PINMUX_AF('D', 8, AF7) 1676 1677 /* USART5_CK */ 1678 #define USART5_CK_PC8 \ 1679 GD32_PINMUX_AF('C', 8, AF8) 1680 1681 /* USART5_RX */ 1682 #define USART5_RX_PA12 \ 1683 GD32_PINMUX_AF('A', 12, AF8) 1684 #define USART5_RX_PC7 \ 1685 GD32_PINMUX_AF('C', 7, AF8) 1686 1687 /* USART5_TX */ 1688 #define USART5_TX_PA11 \ 1689 GD32_PINMUX_AF('A', 11, AF8) 1690 #define USART5_TX_PC6 \ 1691 GD32_PINMUX_AF('C', 6, AF8) 1692 1693 /* USBFS_DM */ 1694 #define USBFS_DM_PA11 \ 1695 GD32_PINMUX_AF('A', 11, AF10) 1696 1697 /* USBFS_DP */ 1698 #define USBFS_DP_PA12 \ 1699 GD32_PINMUX_AF('A', 12, AF10) 1700 1701 /* USBFS_ID */ 1702 #define USBFS_ID_PA10 \ 1703 GD32_PINMUX_AF('A', 10, AF10) 1704 1705 /* USBFS_SOF */ 1706 #define USBFS_SOF_PA8 \ 1707 GD32_PINMUX_AF('A', 8, AF10) 1708 1709 /* USBHS_DM */ 1710 #define USBHS_DM_PB14 \ 1711 GD32_PINMUX_AF('B', 14, AF12) 1712 1713 /* USBHS_DP */ 1714 #define USBHS_DP_PB15 \ 1715 GD32_PINMUX_AF('B', 15, AF12) 1716 1717 /* USBHS_ID */ 1718 #define USBHS_ID_PB12 \ 1719 GD32_PINMUX_AF('B', 12, AF12) 1720 1721 /* USBHS_SOF */ 1722 #define USBHS_SOF_PA4 \ 1723 GD32_PINMUX_AF('A', 4, AF12) 1724 1725 /* USBHS_ULPI_CK */ 1726 #define USBHS_ULPI_CK_PA5 \ 1727 GD32_PINMUX_AF('A', 5, AF10) 1728 1729 /* USBHS_ULPI_D0 */ 1730 #define USBHS_ULPI_D0_PA3 \ 1731 GD32_PINMUX_AF('A', 3, AF10) 1732 1733 /* USBHS_ULPI_D1 */ 1734 #define USBHS_ULPI_D1_PB0 \ 1735 GD32_PINMUX_AF('B', 0, AF10) 1736 1737 /* USBHS_ULPI_D2 */ 1738 #define USBHS_ULPI_D2_PB1 \ 1739 GD32_PINMUX_AF('B', 1, AF10) 1740 1741 /* USBHS_ULPI_D3 */ 1742 #define USBHS_ULPI_D3_PB10 \ 1743 GD32_PINMUX_AF('B', 10, AF10) 1744 1745 /* USBHS_ULPI_D4 */ 1746 #define USBHS_ULPI_D4_PB2 \ 1747 GD32_PINMUX_AF('B', 2, AF10) 1748 #define USBHS_ULPI_D4_PB11 \ 1749 GD32_PINMUX_AF('B', 11, AF10) 1750 1751 /* USBHS_ULPI_D5 */ 1752 #define USBHS_ULPI_D5_PB12 \ 1753 GD32_PINMUX_AF('B', 12, AF10) 1754 1755 /* USBHS_ULPI_D6 */ 1756 #define USBHS_ULPI_D6_PB13 \ 1757 GD32_PINMUX_AF('B', 13, AF10) 1758 1759 /* USBHS_ULPI_D7 */ 1760 #define USBHS_ULPI_D7_PB5 \ 1761 GD32_PINMUX_AF('B', 5, AF10) 1762 1763 /* USBHS_ULPI_DIR */ 1764 #define USBHS_ULPI_DIR_PC2 \ 1765 GD32_PINMUX_AF('C', 2, AF10) 1766 1767 /* USBHS_ULPI_NXT */ 1768 #define USBHS_ULPI_NXT_PC3 \ 1769 GD32_PINMUX_AF('C', 3, AF10) 1770 1771 /* USBHS_ULPI_STP */ 1772 #define USBHS_ULPI_STP_PC0 \ 1773 GD32_PINMUX_AF('C', 0, AF10) 1774
