1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32-af.h" 8 9 /* ADC012_IN0 */ 10 #define ADC012_IN0_PA0 \ 11 GD32_PINMUX_AF('A', 0, ANALOG) 12 13 /* ADC012_IN1 */ 14 #define ADC012_IN1_PA1 \ 15 GD32_PINMUX_AF('A', 1, ANALOG) 16 17 /* ADC012_IN10 */ 18 #define ADC012_IN10_PC0 \ 19 GD32_PINMUX_AF('C', 0, ANALOG) 20 21 /* ADC012_IN11 */ 22 #define ADC012_IN11_PC1 \ 23 GD32_PINMUX_AF('C', 1, ANALOG) 24 25 /* ADC012_IN12 */ 26 #define ADC012_IN12_PC2 \ 27 GD32_PINMUX_AF('C', 2, ANALOG) 28 29 /* ADC012_IN13 */ 30 #define ADC012_IN13_PC3 \ 31 GD32_PINMUX_AF('C', 3, ANALOG) 32 33 /* ADC012_IN2 */ 34 #define ADC012_IN2_PA2 \ 35 GD32_PINMUX_AF('A', 2, ANALOG) 36 37 /* ADC012_IN3 */ 38 #define ADC012_IN3_PA3 \ 39 GD32_PINMUX_AF('A', 3, ANALOG) 40 41 /* ADC01_IN14 */ 42 #define ADC01_IN14_PC4 \ 43 GD32_PINMUX_AF('C', 4, ANALOG) 44 45 /* ADC01_IN15 */ 46 #define ADC01_IN15_PC5 \ 47 GD32_PINMUX_AF('C', 5, ANALOG) 48 49 /* ADC01_IN4 */ 50 #define ADC01_IN4_PA4 \ 51 GD32_PINMUX_AF('A', 4, ANALOG) 52 53 /* ADC01_IN5 */ 54 #define ADC01_IN5_PA5 \ 55 GD32_PINMUX_AF('A', 5, ANALOG) 56 57 /* ADC01_IN6 */ 58 #define ADC01_IN6_PA6 \ 59 GD32_PINMUX_AF('A', 6, ANALOG) 60 61 /* ADC01_IN7 */ 62 #define ADC01_IN7_PA7 \ 63 GD32_PINMUX_AF('A', 7, ANALOG) 64 65 /* ADC01_IN8 */ 66 #define ADC01_IN8_PB0 \ 67 GD32_PINMUX_AF('B', 0, ANALOG) 68 69 /* ADC01_IN9 */ 70 #define ADC01_IN9_PB1 \ 71 GD32_PINMUX_AF('B', 1, ANALOG) 72 73 /* ADC2_IN14 */ 74 #define ADC2_IN14_PF4 \ 75 GD32_PINMUX_AF('F', 4, ANALOG) 76 77 /* ADC2_IN15 */ 78 #define ADC2_IN15_PF5 \ 79 GD32_PINMUX_AF('F', 5, ANALOG) 80 81 /* ADC2_IN4 */ 82 #define ADC2_IN4_PF6 \ 83 GD32_PINMUX_AF('F', 6, ANALOG) 84 85 /* ADC2_IN5 */ 86 #define ADC2_IN5_PF7 \ 87 GD32_PINMUX_AF('F', 7, ANALOG) 88 89 /* ADC2_IN6 */ 90 #define ADC2_IN6_PF8 \ 91 GD32_PINMUX_AF('F', 8, ANALOG) 92 93 /* ADC2_IN7 */ 94 #define ADC2_IN7_PF9 \ 95 GD32_PINMUX_AF('F', 9, ANALOG) 96 97 /* ADC2_IN8 */ 98 #define ADC2_IN8_PF10 \ 99 GD32_PINMUX_AF('F', 10, ANALOG) 100 101 /* ADC2_IN9 */ 102 #define ADC2_IN9_PF3 \ 103 GD32_PINMUX_AF('F', 3, ANALOG) 104 105 /* ANALOG */ 106 #define ANALOG_PA0 \ 107 GD32_PINMUX_AF('A', 0, ANALOG) 108 #define ANALOG_PA1 \ 109 GD32_PINMUX_AF('A', 1, ANALOG) 110 #define ANALOG_PA2 \ 111 GD32_PINMUX_AF('A', 2, ANALOG) 112 #define ANALOG_PA3 \ 113 GD32_PINMUX_AF('A', 3, ANALOG) 114 #define ANALOG_PA4 \ 115 GD32_PINMUX_AF('A', 4, ANALOG) 116 #define ANALOG_PA5 \ 117 GD32_PINMUX_AF('A', 5, ANALOG) 118 #define ANALOG_PA6 \ 119 GD32_PINMUX_AF('A', 6, ANALOG) 120 #define ANALOG_PA7 \ 121 GD32_PINMUX_AF('A', 7, ANALOG) 122 #define ANALOG_PA8 \ 123 GD32_PINMUX_AF('A', 8, ANALOG) 124 #define ANALOG_PA9 \ 125 GD32_PINMUX_AF('A', 9, ANALOG) 126 #define ANALOG_PA10 \ 127 GD32_PINMUX_AF('A', 10, ANALOG) 128 #define ANALOG_PA11 \ 129 GD32_PINMUX_AF('A', 11, ANALOG) 130 #define ANALOG_PA12 \ 131 GD32_PINMUX_AF('A', 12, ANALOG) 132 #define ANALOG_PA13 \ 133 GD32_PINMUX_AF('A', 13, ANALOG) 134 #define ANALOG_PA14 \ 135 GD32_PINMUX_AF('A', 14, ANALOG) 136 #define ANALOG_PA15 \ 137 GD32_PINMUX_AF('A', 15, ANALOG) 138 #define ANALOG_PB0 \ 139 GD32_PINMUX_AF('B', 0, ANALOG) 140 #define ANALOG_PB1 \ 141 GD32_PINMUX_AF('B', 1, ANALOG) 142 #define ANALOG_PB2 \ 143 GD32_PINMUX_AF('B', 2, ANALOG) 144 #define ANALOG_PB3 \ 145 GD32_PINMUX_AF('B', 3, ANALOG) 146 #define ANALOG_PB4 \ 147 GD32_PINMUX_AF('B', 4, ANALOG) 148 #define ANALOG_PB5 \ 149 GD32_PINMUX_AF('B', 5, ANALOG) 150 #define ANALOG_PB6 \ 151 GD32_PINMUX_AF('B', 6, ANALOG) 152 #define ANALOG_PB7 \ 153 GD32_PINMUX_AF('B', 7, ANALOG) 154 #define ANALOG_PB8 \ 155 GD32_PINMUX_AF('B', 8, ANALOG) 156 #define ANALOG_PB9 \ 157 GD32_PINMUX_AF('B', 9, ANALOG) 158 #define ANALOG_PB10 \ 159 GD32_PINMUX_AF('B', 10, ANALOG) 160 #define ANALOG_PB11 \ 161 GD32_PINMUX_AF('B', 11, ANALOG) 162 #define ANALOG_PB12 \ 163 GD32_PINMUX_AF('B', 12, ANALOG) 164 #define ANALOG_PB13 \ 165 GD32_PINMUX_AF('B', 13, ANALOG) 166 #define ANALOG_PB14 \ 167 GD32_PINMUX_AF('B', 14, ANALOG) 168 #define ANALOG_PB15 \ 169 GD32_PINMUX_AF('B', 15, ANALOG) 170 #define ANALOG_PC0 \ 171 GD32_PINMUX_AF('C', 0, ANALOG) 172 #define ANALOG_PC1 \ 173 GD32_PINMUX_AF('C', 1, ANALOG) 174 #define ANALOG_PC2 \ 175 GD32_PINMUX_AF('C', 2, ANALOG) 176 #define ANALOG_PC3 \ 177 GD32_PINMUX_AF('C', 3, ANALOG) 178 #define ANALOG_PC4 \ 179 GD32_PINMUX_AF('C', 4, ANALOG) 180 #define ANALOG_PC5 \ 181 GD32_PINMUX_AF('C', 5, ANALOG) 182 #define ANALOG_PC6 \ 183 GD32_PINMUX_AF('C', 6, ANALOG) 184 #define ANALOG_PC7 \ 185 GD32_PINMUX_AF('C', 7, ANALOG) 186 #define ANALOG_PC8 \ 187 GD32_PINMUX_AF('C', 8, ANALOG) 188 #define ANALOG_PC9 \ 189 GD32_PINMUX_AF('C', 9, ANALOG) 190 #define ANALOG_PC10 \ 191 GD32_PINMUX_AF('C', 10, ANALOG) 192 #define ANALOG_PC11 \ 193 GD32_PINMUX_AF('C', 11, ANALOG) 194 #define ANALOG_PC12 \ 195 GD32_PINMUX_AF('C', 12, ANALOG) 196 #define ANALOG_PC13 \ 197 GD32_PINMUX_AF('C', 13, ANALOG) 198 #define ANALOG_PC14 \ 199 GD32_PINMUX_AF('C', 14, ANALOG) 200 #define ANALOG_PC15 \ 201 GD32_PINMUX_AF('C', 15, ANALOG) 202 #define ANALOG_PD0 \ 203 GD32_PINMUX_AF('D', 0, ANALOG) 204 #define ANALOG_PD1 \ 205 GD32_PINMUX_AF('D', 1, ANALOG) 206 #define ANALOG_PD2 \ 207 GD32_PINMUX_AF('D', 2, ANALOG) 208 #define ANALOG_PD3 \ 209 GD32_PINMUX_AF('D', 3, ANALOG) 210 #define ANALOG_PD4 \ 211 GD32_PINMUX_AF('D', 4, ANALOG) 212 #define ANALOG_PD5 \ 213 GD32_PINMUX_AF('D', 5, ANALOG) 214 #define ANALOG_PD6 \ 215 GD32_PINMUX_AF('D', 6, ANALOG) 216 #define ANALOG_PD7 \ 217 GD32_PINMUX_AF('D', 7, ANALOG) 218 #define ANALOG_PD8 \ 219 GD32_PINMUX_AF('D', 8, ANALOG) 220 #define ANALOG_PD9 \ 221 GD32_PINMUX_AF('D', 9, ANALOG) 222 #define ANALOG_PD10 \ 223 GD32_PINMUX_AF('D', 10, ANALOG) 224 #define ANALOG_PD11 \ 225 GD32_PINMUX_AF('D', 11, ANALOG) 226 #define ANALOG_PD12 \ 227 GD32_PINMUX_AF('D', 12, ANALOG) 228 #define ANALOG_PD13 \ 229 GD32_PINMUX_AF('D', 13, ANALOG) 230 #define ANALOG_PD14 \ 231 GD32_PINMUX_AF('D', 14, ANALOG) 232 #define ANALOG_PD15 \ 233 GD32_PINMUX_AF('D', 15, ANALOG) 234 #define ANALOG_PE0 \ 235 GD32_PINMUX_AF('E', 0, ANALOG) 236 #define ANALOG_PE1 \ 237 GD32_PINMUX_AF('E', 1, ANALOG) 238 #define ANALOG_PE2 \ 239 GD32_PINMUX_AF('E', 2, ANALOG) 240 #define ANALOG_PE3 \ 241 GD32_PINMUX_AF('E', 3, ANALOG) 242 #define ANALOG_PE4 \ 243 GD32_PINMUX_AF('E', 4, ANALOG) 244 #define ANALOG_PE5 \ 245 GD32_PINMUX_AF('E', 5, ANALOG) 246 #define ANALOG_PE6 \ 247 GD32_PINMUX_AF('E', 6, ANALOG) 248 #define ANALOG_PE7 \ 249 GD32_PINMUX_AF('E', 7, ANALOG) 250 #define ANALOG_PE8 \ 251 GD32_PINMUX_AF('E', 8, ANALOG) 252 #define ANALOG_PE9 \ 253 GD32_PINMUX_AF('E', 9, ANALOG) 254 #define ANALOG_PE10 \ 255 GD32_PINMUX_AF('E', 10, ANALOG) 256 #define ANALOG_PE11 \ 257 GD32_PINMUX_AF('E', 11, ANALOG) 258 #define ANALOG_PE12 \ 259 GD32_PINMUX_AF('E', 12, ANALOG) 260 #define ANALOG_PE13 \ 261 GD32_PINMUX_AF('E', 13, ANALOG) 262 #define ANALOG_PE14 \ 263 GD32_PINMUX_AF('E', 14, ANALOG) 264 #define ANALOG_PE15 \ 265 GD32_PINMUX_AF('E', 15, ANALOG) 266 #define ANALOG_PF0 \ 267 GD32_PINMUX_AF('F', 0, ANALOG) 268 #define ANALOG_PF1 \ 269 GD32_PINMUX_AF('F', 1, ANALOG) 270 #define ANALOG_PF2 \ 271 GD32_PINMUX_AF('F', 2, ANALOG) 272 #define ANALOG_PF3 \ 273 GD32_PINMUX_AF('F', 3, ANALOG) 274 #define ANALOG_PF4 \ 275 GD32_PINMUX_AF('F', 4, ANALOG) 276 #define ANALOG_PF5 \ 277 GD32_PINMUX_AF('F', 5, ANALOG) 278 #define ANALOG_PF6 \ 279 GD32_PINMUX_AF('F', 6, ANALOG) 280 #define ANALOG_PF7 \ 281 GD32_PINMUX_AF('F', 7, ANALOG) 282 #define ANALOG_PF8 \ 283 GD32_PINMUX_AF('F', 8, ANALOG) 284 #define ANALOG_PF9 \ 285 GD32_PINMUX_AF('F', 9, ANALOG) 286 #define ANALOG_PF10 \ 287 GD32_PINMUX_AF('F', 10, ANALOG) 288 #define ANALOG_PF11 \ 289 GD32_PINMUX_AF('F', 11, ANALOG) 290 #define ANALOG_PF12 \ 291 GD32_PINMUX_AF('F', 12, ANALOG) 292 #define ANALOG_PF13 \ 293 GD32_PINMUX_AF('F', 13, ANALOG) 294 #define ANALOG_PF14 \ 295 GD32_PINMUX_AF('F', 14, ANALOG) 296 #define ANALOG_PF15 \ 297 GD32_PINMUX_AF('F', 15, ANALOG) 298 #define ANALOG_PG0 \ 299 GD32_PINMUX_AF('G', 0, ANALOG) 300 #define ANALOG_PG1 \ 301 GD32_PINMUX_AF('G', 1, ANALOG) 302 #define ANALOG_PG2 \ 303 GD32_PINMUX_AF('G', 2, ANALOG) 304 #define ANALOG_PG3 \ 305 GD32_PINMUX_AF('G', 3, ANALOG) 306 #define ANALOG_PG4 \ 307 GD32_PINMUX_AF('G', 4, ANALOG) 308 #define ANALOG_PG5 \ 309 GD32_PINMUX_AF('G', 5, ANALOG) 310 #define ANALOG_PG6 \ 311 GD32_PINMUX_AF('G', 6, ANALOG) 312 #define ANALOG_PG7 \ 313 GD32_PINMUX_AF('G', 7, ANALOG) 314 #define ANALOG_PG8 \ 315 GD32_PINMUX_AF('G', 8, ANALOG) 316 #define ANALOG_PG9 \ 317 GD32_PINMUX_AF('G', 9, ANALOG) 318 #define ANALOG_PG10 \ 319 GD32_PINMUX_AF('G', 10, ANALOG) 320 #define ANALOG_PG11 \ 321 GD32_PINMUX_AF('G', 11, ANALOG) 322 #define ANALOG_PG12 \ 323 GD32_PINMUX_AF('G', 12, ANALOG) 324 #define ANALOG_PG13 \ 325 GD32_PINMUX_AF('G', 13, ANALOG) 326 #define ANALOG_PG14 \ 327 GD32_PINMUX_AF('G', 14, ANALOG) 328 #define ANALOG_PG15 \ 329 GD32_PINMUX_AF('G', 15, ANALOG) 330 #define ANALOG_PH0 \ 331 GD32_PINMUX_AF('H', 0, ANALOG) 332 #define ANALOG_PH1 \ 333 GD32_PINMUX_AF('H', 1, ANALOG) 334 #define ANALOG_PH2 \ 335 GD32_PINMUX_AF('H', 2, ANALOG) 336 #define ANALOG_PH3 \ 337 GD32_PINMUX_AF('H', 3, ANALOG) 338 #define ANALOG_PH4 \ 339 GD32_PINMUX_AF('H', 4, ANALOG) 340 #define ANALOG_PH5 \ 341 GD32_PINMUX_AF('H', 5, ANALOG) 342 #define ANALOG_PH6 \ 343 GD32_PINMUX_AF('H', 6, ANALOG) 344 #define ANALOG_PH7 \ 345 GD32_PINMUX_AF('H', 7, ANALOG) 346 #define ANALOG_PH8 \ 347 GD32_PINMUX_AF('H', 8, ANALOG) 348 #define ANALOG_PH9 \ 349 GD32_PINMUX_AF('H', 9, ANALOG) 350 #define ANALOG_PH10 \ 351 GD32_PINMUX_AF('H', 10, ANALOG) 352 #define ANALOG_PH11 \ 353 GD32_PINMUX_AF('H', 11, ANALOG) 354 #define ANALOG_PH12 \ 355 GD32_PINMUX_AF('H', 12, ANALOG) 356 #define ANALOG_PH13 \ 357 GD32_PINMUX_AF('H', 13, ANALOG) 358 #define ANALOG_PH14 \ 359 GD32_PINMUX_AF('H', 14, ANALOG) 360 #define ANALOG_PH15 \ 361 GD32_PINMUX_AF('H', 15, ANALOG) 362 #define ANALOG_PI0 \ 363 GD32_PINMUX_AF('I', 0, ANALOG) 364 #define ANALOG_PI1 \ 365 GD32_PINMUX_AF('I', 1, ANALOG) 366 #define ANALOG_PI2 \ 367 GD32_PINMUX_AF('I', 2, ANALOG) 368 #define ANALOG_PI3 \ 369 GD32_PINMUX_AF('I', 3, ANALOG) 370 #define ANALOG_PI4 \ 371 GD32_PINMUX_AF('I', 4, ANALOG) 372 #define ANALOG_PI5 \ 373 GD32_PINMUX_AF('I', 5, ANALOG) 374 #define ANALOG_PI6 \ 375 GD32_PINMUX_AF('I', 6, ANALOG) 376 #define ANALOG_PI7 \ 377 GD32_PINMUX_AF('I', 7, ANALOG) 378 #define ANALOG_PI8 \ 379 GD32_PINMUX_AF('I', 8, ANALOG) 380 #define ANALOG_PI9 \ 381 GD32_PINMUX_AF('I', 9, ANALOG) 382 #define ANALOG_PI10 \ 383 GD32_PINMUX_AF('I', 10, ANALOG) 384 #define ANALOG_PI11 \ 385 GD32_PINMUX_AF('I', 11, ANALOG) 386 387 /* CAN0_RX */ 388 #define CAN0_RX_PA11 \ 389 GD32_PINMUX_AF('A', 11, AF9) 390 #define CAN0_RX_PB8 \ 391 GD32_PINMUX_AF('B', 8, AF9) 392 #define CAN0_RX_PD0 \ 393 GD32_PINMUX_AF('D', 0, AF9) 394 #define CAN0_RX_PI9 \ 395 GD32_PINMUX_AF('I', 9, AF9) 396 397 /* CAN0_TX */ 398 #define CAN0_TX_PA12 \ 399 GD32_PINMUX_AF('A', 12, AF9) 400 #define CAN0_TX_PB9 \ 401 GD32_PINMUX_AF('B', 9, AF9) 402 #define CAN0_TX_PD1 \ 403 GD32_PINMUX_AF('D', 1, AF9) 404 #define CAN0_TX_PH13 \ 405 GD32_PINMUX_AF('H', 13, AF9) 406 407 /* CAN1_RX */ 408 #define CAN1_RX_PB5 \ 409 GD32_PINMUX_AF('B', 5, AF9) 410 #define CAN1_RX_PB12 \ 411 GD32_PINMUX_AF('B', 12, AF9) 412 413 /* CAN1_TX */ 414 #define CAN1_TX_PB6 \ 415 GD32_PINMUX_AF('B', 6, AF9) 416 #define CAN1_TX_PB13 \ 417 GD32_PINMUX_AF('B', 13, AF9) 418 419 /* CK_OUT0 */ 420 #define CK_OUT0_PA8 \ 421 GD32_PINMUX_AF('A', 8, AF0) 422 423 /* CK_OUT1 */ 424 #define CK_OUT1_PC9 \ 425 GD32_PINMUX_AF('C', 9, AF0) 426 427 /* CTC_SYNC */ 428 #define CTC_SYNC_PA8 \ 429 GD32_PINMUX_AF('A', 8, AF9) 430 #define CTC_SYNC_PD15 \ 431 GD32_PINMUX_AF('D', 15, AF0) 432 #define CTC_SYNC_PF0 \ 433 GD32_PINMUX_AF('F', 0, AF0) 434 435 /* DAC_OUT0 */ 436 #define DAC_OUT0_PA4 \ 437 GD32_PINMUX_AF('A', 4, ANALOG) 438 439 /* DAC_OUT1 */ 440 #define DAC_OUT1_PA5 \ 441 GD32_PINMUX_AF('A', 5, ANALOG) 442 443 /* DCI_D0 */ 444 #define DCI_D0_PA9 \ 445 GD32_PINMUX_AF('A', 9, AF13) 446 #define DCI_D0_PC6 \ 447 GD32_PINMUX_AF('C', 6, AF13) 448 #define DCI_D0_PH9 \ 449 GD32_PINMUX_AF('H', 9, AF13) 450 451 /* DCI_D1 */ 452 #define DCI_D1_PA10 \ 453 GD32_PINMUX_AF('A', 10, AF13) 454 #define DCI_D1_PC7 \ 455 GD32_PINMUX_AF('C', 7, AF13) 456 #define DCI_D1_PH10 \ 457 GD32_PINMUX_AF('H', 10, AF13) 458 459 /* DCI_D10 */ 460 #define DCI_D10_PB5 \ 461 GD32_PINMUX_AF('B', 5, AF13) 462 #define DCI_D10_PD6 \ 463 GD32_PINMUX_AF('D', 6, AF13) 464 #define DCI_D10_PI3 \ 465 GD32_PINMUX_AF('I', 3, AF13) 466 467 /* DCI_D11 */ 468 #define DCI_D11_PD2 \ 469 GD32_PINMUX_AF('D', 2, AF13) 470 #define DCI_D11_PF10 \ 471 GD32_PINMUX_AF('F', 10, AF13) 472 #define DCI_D11_PH15 \ 473 GD32_PINMUX_AF('H', 15, AF13) 474 475 /* DCI_D12 */ 476 #define DCI_D12_PF11 \ 477 GD32_PINMUX_AF('F', 11, AF13) 478 #define DCI_D12_PG6 \ 479 GD32_PINMUX_AF('G', 6, AF13) 480 481 /* DCI_D13 */ 482 #define DCI_D13_PG7 \ 483 GD32_PINMUX_AF('G', 7, AF13) 484 #define DCI_D13_PG15 \ 485 GD32_PINMUX_AF('G', 15, AF13) 486 #define DCI_D13_PI0 \ 487 GD32_PINMUX_AF('I', 0, AF13) 488 489 /* DCI_D2 */ 490 #define DCI_D2_PC8 \ 491 GD32_PINMUX_AF('C', 8, AF13) 492 #define DCI_D2_PE0 \ 493 GD32_PINMUX_AF('E', 0, AF13) 494 #define DCI_D2_PG10 \ 495 GD32_PINMUX_AF('G', 10, AF13) 496 #define DCI_D2_PH11 \ 497 GD32_PINMUX_AF('H', 11, AF13) 498 499 /* DCI_D3 */ 500 #define DCI_D3_PC9 \ 501 GD32_PINMUX_AF('C', 9, AF13) 502 #define DCI_D3_PE1 \ 503 GD32_PINMUX_AF('E', 1, AF13) 504 #define DCI_D3_PG11 \ 505 GD32_PINMUX_AF('G', 11, AF13) 506 #define DCI_D3_PH12 \ 507 GD32_PINMUX_AF('H', 12, AF13) 508 509 /* DCI_D4 */ 510 #define DCI_D4_PC11 \ 511 GD32_PINMUX_AF('C', 11, AF13) 512 #define DCI_D4_PE4 \ 513 GD32_PINMUX_AF('E', 4, AF13) 514 #define DCI_D4_PH14 \ 515 GD32_PINMUX_AF('H', 14, AF13) 516 517 /* DCI_D5 */ 518 #define DCI_D5_PB6 \ 519 GD32_PINMUX_AF('B', 6, AF13) 520 #define DCI_D5_PD3 \ 521 GD32_PINMUX_AF('D', 3, AF13) 522 #define DCI_D5_PI4 \ 523 GD32_PINMUX_AF('I', 4, AF13) 524 525 /* DCI_D6 */ 526 #define DCI_D6_PB8 \ 527 GD32_PINMUX_AF('B', 8, AF13) 528 #define DCI_D6_PE5 \ 529 GD32_PINMUX_AF('E', 5, AF13) 530 #define DCI_D6_PI6 \ 531 GD32_PINMUX_AF('I', 6, AF13) 532 533 /* DCI_D7 */ 534 #define DCI_D7_PB9 \ 535 GD32_PINMUX_AF('B', 9, AF13) 536 #define DCI_D7_PE6 \ 537 GD32_PINMUX_AF('E', 6, AF13) 538 #define DCI_D7_PI7 \ 539 GD32_PINMUX_AF('I', 7, AF13) 540 541 /* DCI_D8 */ 542 #define DCI_D8_PC10 \ 543 GD32_PINMUX_AF('C', 10, AF13) 544 #define DCI_D8_PH6 \ 545 GD32_PINMUX_AF('H', 6, AF13) 546 #define DCI_D8_PI1 \ 547 GD32_PINMUX_AF('I', 1, AF13) 548 549 /* DCI_D9 */ 550 #define DCI_D9_PC12 \ 551 GD32_PINMUX_AF('C', 12, AF13) 552 #define DCI_D9_PH7 \ 553 GD32_PINMUX_AF('H', 7, AF13) 554 #define DCI_D9_PI2 \ 555 GD32_PINMUX_AF('I', 2, AF13) 556 557 /* DCI_HSYNC */ 558 #define DCI_HSYNC_PA4 \ 559 GD32_PINMUX_AF('A', 4, AF13) 560 #define DCI_HSYNC_PH8 \ 561 GD32_PINMUX_AF('H', 8, AF13) 562 563 /* DCI_PIXCLK */ 564 #define DCI_PIXCLK_PA6 \ 565 GD32_PINMUX_AF('A', 6, AF13) 566 567 /* DCI_VSYNC */ 568 #define DCI_VSYNC_PB7 \ 569 GD32_PINMUX_AF('B', 7, AF13) 570 #define DCI_VSYNC_PG9 \ 571 GD32_PINMUX_AF('G', 9, AF13) 572 #define DCI_VSYNC_PI5 \ 573 GD32_PINMUX_AF('I', 5, AF13) 574 575 /* ETH_MDC */ 576 #define ETH_MDC_PC1 \ 577 GD32_PINMUX_AF('C', 1, AF11) 578 579 /* ETH_MDIO */ 580 #define ETH_MDIO_PA2 \ 581 GD32_PINMUX_AF('A', 2, AF11) 582 583 /* ETH_MII_COL */ 584 #define ETH_MII_COL_PA3 \ 585 GD32_PINMUX_AF('A', 3, AF11) 586 #define ETH_MII_COL_PH3 \ 587 GD32_PINMUX_AF('H', 3, AF11) 588 589 /* ETH_MII_CRS */ 590 #define ETH_MII_CRS_PA0 \ 591 GD32_PINMUX_AF('A', 0, AF11) 592 #define ETH_MII_CRS_PH2 \ 593 GD32_PINMUX_AF('H', 2, AF11) 594 595 /* ETH_MII_RXD0 */ 596 #define ETH_MII_RXD0_PC4 \ 597 GD32_PINMUX_AF('C', 4, AF11) 598 599 /* ETH_MII_RXD1 */ 600 #define ETH_MII_RXD1_PC5 \ 601 GD32_PINMUX_AF('C', 5, AF11) 602 603 /* ETH_MII_RXD2 */ 604 #define ETH_MII_RXD2_PB0 \ 605 GD32_PINMUX_AF('B', 0, AF11) 606 #define ETH_MII_RXD2_PH6 \ 607 GD32_PINMUX_AF('H', 6, AF11) 608 609 /* ETH_MII_RXD3 */ 610 #define ETH_MII_RXD3_PB1 \ 611 GD32_PINMUX_AF('B', 1, AF11) 612 #define ETH_MII_RXD3_PH7 \ 613 GD32_PINMUX_AF('H', 7, AF11) 614 615 /* ETH_MII_RX_CLK */ 616 #define ETH_MII_RX_CLK_PA1 \ 617 GD32_PINMUX_AF('A', 1, AF11) 618 619 /* ETH_MII_RX_DV */ 620 #define ETH_MII_RX_DV_PA7 \ 621 GD32_PINMUX_AF('A', 7, AF11) 622 623 /* ETH_MII_RX_ER */ 624 #define ETH_MII_RX_ER_PB10 \ 625 GD32_PINMUX_AF('B', 10, AF11) 626 #define ETH_MII_RX_ER_PI10 \ 627 GD32_PINMUX_AF('I', 10, AF11) 628 629 /* ETH_MII_TXD0 */ 630 #define ETH_MII_TXD0_PB12 \ 631 GD32_PINMUX_AF('B', 12, AF11) 632 #define ETH_MII_TXD0_PG13 \ 633 GD32_PINMUX_AF('G', 13, AF11) 634 635 /* ETH_MII_TXD1 */ 636 #define ETH_MII_TXD1_PB13 \ 637 GD32_PINMUX_AF('B', 13, AF11) 638 #define ETH_MII_TXD1_PG14 \ 639 GD32_PINMUX_AF('G', 14, AF11) 640 641 /* ETH_MII_TXD2 */ 642 #define ETH_MII_TXD2_PC2 \ 643 GD32_PINMUX_AF('C', 2, AF11) 644 645 /* ETH_MII_TXD3 */ 646 #define ETH_MII_TXD3_PB8 \ 647 GD32_PINMUX_AF('B', 8, AF11) 648 #define ETH_MII_TXD3_PE2 \ 649 GD32_PINMUX_AF('E', 2, AF11) 650 651 /* ETH_MII_TX_CLK */ 652 #define ETH_MII_TX_CLK_PC3 \ 653 GD32_PINMUX_AF('C', 3, AF11) 654 655 /* ETH_MII_TX_EN */ 656 #define ETH_MII_TX_EN_PB11 \ 657 GD32_PINMUX_AF('B', 11, AF11) 658 #define ETH_MII_TX_EN_PG11 \ 659 GD32_PINMUX_AF('G', 11, AF11) 660 661 /* ETH_PPS_OUT */ 662 #define ETH_PPS_OUT_PB5 \ 663 GD32_PINMUX_AF('B', 5, AF11) 664 #define ETH_PPS_OUT_PG8 \ 665 GD32_PINMUX_AF('G', 8, AF11) 666 667 /* ETH_RMII_CRS_DV */ 668 #define ETH_RMII_CRS_DV_PA7 \ 669 GD32_PINMUX_AF('A', 7, AF11) 670 671 /* ETH_RMII_REF_CLK */ 672 #define ETH_RMII_REF_CLK_PA1 \ 673 GD32_PINMUX_AF('A', 1, AF11) 674 675 /* ETH_RMII_RXD0 */ 676 #define ETH_RMII_RXD0_PC4 \ 677 GD32_PINMUX_AF('C', 4, AF11) 678 679 /* ETH_RMII_RXD1 */ 680 #define ETH_RMII_RXD1_PC5 \ 681 GD32_PINMUX_AF('C', 5, AF11) 682 683 /* ETH_RMII_TXD0 */ 684 #define ETH_RMII_TXD0_PB12 \ 685 GD32_PINMUX_AF('B', 12, AF11) 686 #define ETH_RMII_TXD0_PG13 \ 687 GD32_PINMUX_AF('G', 13, AF11) 688 689 /* ETH_RMII_TXD1 */ 690 #define ETH_RMII_TXD1_PB13 \ 691 GD32_PINMUX_AF('B', 13, AF11) 692 #define ETH_RMII_TXD1_PG14 \ 693 GD32_PINMUX_AF('G', 14, AF11) 694 695 /* ETH_RMII_TX_EN */ 696 #define ETH_RMII_TX_EN_PB11 \ 697 GD32_PINMUX_AF('B', 11, AF11) 698 #define ETH_RMII_TX_EN_PG11 \ 699 GD32_PINMUX_AF('G', 11, AF11) 700 701 /* EVENTOUT */ 702 #define EVENTOUT_PA0 \ 703 GD32_PINMUX_AF('A', 0, AF15) 704 #define EVENTOUT_PA1 \ 705 GD32_PINMUX_AF('A', 1, AF15) 706 #define EVENTOUT_PA2 \ 707 GD32_PINMUX_AF('A', 2, AF15) 708 #define EVENTOUT_PA3 \ 709 GD32_PINMUX_AF('A', 3, AF15) 710 #define EVENTOUT_PA4 \ 711 GD32_PINMUX_AF('A', 4, AF15) 712 #define EVENTOUT_PA5 \ 713 GD32_PINMUX_AF('A', 5, AF15) 714 #define EVENTOUT_PA6 \ 715 GD32_PINMUX_AF('A', 6, AF15) 716 #define EVENTOUT_PA7 \ 717 GD32_PINMUX_AF('A', 7, AF15) 718 #define EVENTOUT_PA8 \ 719 GD32_PINMUX_AF('A', 8, AF15) 720 #define EVENTOUT_PA9 \ 721 GD32_PINMUX_AF('A', 9, AF15) 722 #define EVENTOUT_PA10 \ 723 GD32_PINMUX_AF('A', 10, AF15) 724 #define EVENTOUT_PA11 \ 725 GD32_PINMUX_AF('A', 11, AF15) 726 #define EVENTOUT_PA12 \ 727 GD32_PINMUX_AF('A', 12, AF15) 728 #define EVENTOUT_PA13 \ 729 GD32_PINMUX_AF('A', 13, AF15) 730 #define EVENTOUT_PA14 \ 731 GD32_PINMUX_AF('A', 14, AF15) 732 #define EVENTOUT_PA15 \ 733 GD32_PINMUX_AF('A', 15, AF15) 734 #define EVENTOUT_PB0 \ 735 GD32_PINMUX_AF('B', 0, AF15) 736 #define EVENTOUT_PB1 \ 737 GD32_PINMUX_AF('B', 1, AF15) 738 #define EVENTOUT_PB2 \ 739 GD32_PINMUX_AF('B', 2, AF15) 740 #define EVENTOUT_PB3 \ 741 GD32_PINMUX_AF('B', 3, AF15) 742 #define EVENTOUT_PB4 \ 743 GD32_PINMUX_AF('B', 4, AF15) 744 #define EVENTOUT_PB5 \ 745 GD32_PINMUX_AF('B', 5, AF15) 746 #define EVENTOUT_PB6 \ 747 GD32_PINMUX_AF('B', 6, AF15) 748 #define EVENTOUT_PB7 \ 749 GD32_PINMUX_AF('B', 7, AF15) 750 #define EVENTOUT_PB8 \ 751 GD32_PINMUX_AF('B', 8, AF15) 752 #define EVENTOUT_PB9 \ 753 GD32_PINMUX_AF('B', 9, AF15) 754 #define EVENTOUT_PB10 \ 755 GD32_PINMUX_AF('B', 10, AF15) 756 #define EVENTOUT_PB11 \ 757 GD32_PINMUX_AF('B', 11, AF15) 758 #define EVENTOUT_PB12 \ 759 GD32_PINMUX_AF('B', 12, AF15) 760 #define EVENTOUT_PB13 \ 761 GD32_PINMUX_AF('B', 13, AF15) 762 #define EVENTOUT_PB14 \ 763 GD32_PINMUX_AF('B', 14, AF15) 764 #define EVENTOUT_PB15 \ 765 GD32_PINMUX_AF('B', 15, AF15) 766 #define EVENTOUT_PC0 \ 767 GD32_PINMUX_AF('C', 0, AF15) 768 #define EVENTOUT_PC1 \ 769 GD32_PINMUX_AF('C', 1, AF15) 770 #define EVENTOUT_PC2 \ 771 GD32_PINMUX_AF('C', 2, AF15) 772 #define EVENTOUT_PC3 \ 773 GD32_PINMUX_AF('C', 3, AF15) 774 #define EVENTOUT_PC4 \ 775 GD32_PINMUX_AF('C', 4, AF15) 776 #define EVENTOUT_PC5 \ 777 GD32_PINMUX_AF('C', 5, AF15) 778 #define EVENTOUT_PC6 \ 779 GD32_PINMUX_AF('C', 6, AF15) 780 #define EVENTOUT_PC7 \ 781 GD32_PINMUX_AF('C', 7, AF15) 782 #define EVENTOUT_PC8 \ 783 GD32_PINMUX_AF('C', 8, AF15) 784 #define EVENTOUT_PC9 \ 785 GD32_PINMUX_AF('C', 9, AF15) 786 #define EVENTOUT_PC10 \ 787 GD32_PINMUX_AF('C', 10, AF15) 788 #define EVENTOUT_PC11 \ 789 GD32_PINMUX_AF('C', 11, AF15) 790 #define EVENTOUT_PC12 \ 791 GD32_PINMUX_AF('C', 12, AF15) 792 #define EVENTOUT_PC13 \ 793 GD32_PINMUX_AF('C', 13, AF15) 794 #define EVENTOUT_PC14 \ 795 GD32_PINMUX_AF('C', 14, AF15) 796 #define EVENTOUT_PC15 \ 797 GD32_PINMUX_AF('C', 15, AF15) 798 #define EVENTOUT_PD0 \ 799 GD32_PINMUX_AF('D', 0, AF15) 800 #define EVENTOUT_PD1 \ 801 GD32_PINMUX_AF('D', 1, AF15) 802 #define EVENTOUT_PD2 \ 803 GD32_PINMUX_AF('D', 2, AF15) 804 #define EVENTOUT_PD3 \ 805 GD32_PINMUX_AF('D', 3, AF15) 806 #define EVENTOUT_PD4 \ 807 GD32_PINMUX_AF('D', 4, AF15) 808 #define EVENTOUT_PD5 \ 809 GD32_PINMUX_AF('D', 5, AF15) 810 #define EVENTOUT_PD6 \ 811 GD32_PINMUX_AF('D', 6, AF15) 812 #define EVENTOUT_PD7 \ 813 GD32_PINMUX_AF('D', 7, AF15) 814 #define EVENTOUT_PD8 \ 815 GD32_PINMUX_AF('D', 8, AF15) 816 #define EVENTOUT_PD9 \ 817 GD32_PINMUX_AF('D', 9, AF15) 818 #define EVENTOUT_PD10 \ 819 GD32_PINMUX_AF('D', 10, AF15) 820 #define EVENTOUT_PD11 \ 821 GD32_PINMUX_AF('D', 11, AF15) 822 #define EVENTOUT_PD12 \ 823 GD32_PINMUX_AF('D', 12, AF15) 824 #define EVENTOUT_PD13 \ 825 GD32_PINMUX_AF('D', 13, AF15) 826 #define EVENTOUT_PD14 \ 827 GD32_PINMUX_AF('D', 14, AF15) 828 #define EVENTOUT_PD15 \ 829 GD32_PINMUX_AF('D', 15, AF15) 830 #define EVENTOUT_PE0 \ 831 GD32_PINMUX_AF('E', 0, AF15) 832 #define EVENTOUT_PE1 \ 833 GD32_PINMUX_AF('E', 1, AF15) 834 #define EVENTOUT_PE2 \ 835 GD32_PINMUX_AF('E', 2, AF15) 836 #define EVENTOUT_PE3 \ 837 GD32_PINMUX_AF('E', 3, AF15) 838 #define EVENTOUT_PE4 \ 839 GD32_PINMUX_AF('E', 4, AF15) 840 #define EVENTOUT_PE5 \ 841 GD32_PINMUX_AF('E', 5, AF15) 842 #define EVENTOUT_PE6 \ 843 GD32_PINMUX_AF('E', 6, AF15) 844 #define EVENTOUT_PE7 \ 845 GD32_PINMUX_AF('E', 7, AF15) 846 #define EVENTOUT_PE8 \ 847 GD32_PINMUX_AF('E', 8, AF15) 848 #define EVENTOUT_PE9 \ 849 GD32_PINMUX_AF('E', 9, AF15) 850 #define EVENTOUT_PE10 \ 851 GD32_PINMUX_AF('E', 10, AF15) 852 #define EVENTOUT_PE11 \ 853 GD32_PINMUX_AF('E', 11, AF15) 854 #define EVENTOUT_PE12 \ 855 GD32_PINMUX_AF('E', 12, AF15) 856 #define EVENTOUT_PE13 \ 857 GD32_PINMUX_AF('E', 13, AF15) 858 #define EVENTOUT_PE14 \ 859 GD32_PINMUX_AF('E', 14, AF15) 860 #define EVENTOUT_PE15 \ 861 GD32_PINMUX_AF('E', 15, AF15) 862 #define EVENTOUT_PF0 \ 863 GD32_PINMUX_AF('F', 0, AF15) 864 #define EVENTOUT_PF1 \ 865 GD32_PINMUX_AF('F', 1, AF15) 866 #define EVENTOUT_PF2 \ 867 GD32_PINMUX_AF('F', 2, AF15) 868 #define EVENTOUT_PF3 \ 869 GD32_PINMUX_AF('F', 3, AF15) 870 #define EVENTOUT_PF4 \ 871 GD32_PINMUX_AF('F', 4, AF15) 872 #define EVENTOUT_PF5 \ 873 GD32_PINMUX_AF('F', 5, AF15) 874 #define EVENTOUT_PF6 \ 875 GD32_PINMUX_AF('F', 6, AF15) 876 #define EVENTOUT_PF7 \ 877 GD32_PINMUX_AF('F', 7, AF15) 878 #define EVENTOUT_PF8 \ 879 GD32_PINMUX_AF('F', 8, AF15) 880 #define EVENTOUT_PF9 \ 881 GD32_PINMUX_AF('F', 9, AF15) 882 #define EVENTOUT_PF10 \ 883 GD32_PINMUX_AF('F', 10, AF15) 884 #define EVENTOUT_PF11 \ 885 GD32_PINMUX_AF('F', 11, AF15) 886 #define EVENTOUT_PF12 \ 887 GD32_PINMUX_AF('F', 12, AF15) 888 #define EVENTOUT_PF13 \ 889 GD32_PINMUX_AF('F', 13, AF15) 890 #define EVENTOUT_PF14 \ 891 GD32_PINMUX_AF('F', 14, AF15) 892 #define EVENTOUT_PF15 \ 893 GD32_PINMUX_AF('F', 15, AF15) 894 #define EVENTOUT_PG0 \ 895 GD32_PINMUX_AF('G', 0, AF15) 896 #define EVENTOUT_PG1 \ 897 GD32_PINMUX_AF('G', 1, AF15) 898 #define EVENTOUT_PG2 \ 899 GD32_PINMUX_AF('G', 2, AF15) 900 #define EVENTOUT_PG3 \ 901 GD32_PINMUX_AF('G', 3, AF15) 902 #define EVENTOUT_PG4 \ 903 GD32_PINMUX_AF('G', 4, AF15) 904 #define EVENTOUT_PG5 \ 905 GD32_PINMUX_AF('G', 5, AF15) 906 #define EVENTOUT_PG6 \ 907 GD32_PINMUX_AF('G', 6, AF15) 908 #define EVENTOUT_PG7 \ 909 GD32_PINMUX_AF('G', 7, AF15) 910 #define EVENTOUT_PG8 \ 911 GD32_PINMUX_AF('G', 8, AF15) 912 #define EVENTOUT_PG9 \ 913 GD32_PINMUX_AF('G', 9, AF15) 914 #define EVENTOUT_PG10 \ 915 GD32_PINMUX_AF('G', 10, AF15) 916 #define EVENTOUT_PG11 \ 917 GD32_PINMUX_AF('G', 11, AF15) 918 #define EVENTOUT_PG12 \ 919 GD32_PINMUX_AF('G', 12, AF15) 920 #define EVENTOUT_PG13 \ 921 GD32_PINMUX_AF('G', 13, AF15) 922 #define EVENTOUT_PG14 \ 923 GD32_PINMUX_AF('G', 14, AF15) 924 #define EVENTOUT_PG15 \ 925 GD32_PINMUX_AF('G', 15, AF15) 926 #define EVENTOUT_PH0 \ 927 GD32_PINMUX_AF('H', 0, AF15) 928 #define EVENTOUT_PH1 \ 929 GD32_PINMUX_AF('H', 1, AF15) 930 #define EVENTOUT_PH2 \ 931 GD32_PINMUX_AF('H', 2, AF15) 932 #define EVENTOUT_PH3 \ 933 GD32_PINMUX_AF('H', 3, AF15) 934 #define EVENTOUT_PH4 \ 935 GD32_PINMUX_AF('H', 4, AF15) 936 #define EVENTOUT_PH5 \ 937 GD32_PINMUX_AF('H', 5, AF15) 938 #define EVENTOUT_PH6 \ 939 GD32_PINMUX_AF('H', 6, AF15) 940 #define EVENTOUT_PH7 \ 941 GD32_PINMUX_AF('H', 7, AF15) 942 #define EVENTOUT_PH8 \ 943 GD32_PINMUX_AF('H', 8, AF15) 944 #define EVENTOUT_PH9 \ 945 GD32_PINMUX_AF('H', 9, AF15) 946 #define EVENTOUT_PH10 \ 947 GD32_PINMUX_AF('H', 10, AF15) 948 #define EVENTOUT_PH11 \ 949 GD32_PINMUX_AF('H', 11, AF15) 950 #define EVENTOUT_PH12 \ 951 GD32_PINMUX_AF('H', 12, AF15) 952 #define EVENTOUT_PH13 \ 953 GD32_PINMUX_AF('H', 13, AF15) 954 #define EVENTOUT_PH14 \ 955 GD32_PINMUX_AF('H', 14, AF15) 956 #define EVENTOUT_PH15 \ 957 GD32_PINMUX_AF('H', 15, AF15) 958 #define EVENTOUT_PI0 \ 959 GD32_PINMUX_AF('I', 0, AF15) 960 #define EVENTOUT_PI1 \ 961 GD32_PINMUX_AF('I', 1, AF15) 962 #define EVENTOUT_PI2 \ 963 GD32_PINMUX_AF('I', 2, AF15) 964 #define EVENTOUT_PI3 \ 965 GD32_PINMUX_AF('I', 3, AF15) 966 #define EVENTOUT_PI4 \ 967 GD32_PINMUX_AF('I', 4, AF15) 968 #define EVENTOUT_PI5 \ 969 GD32_PINMUX_AF('I', 5, AF15) 970 #define EVENTOUT_PI6 \ 971 GD32_PINMUX_AF('I', 6, AF15) 972 #define EVENTOUT_PI7 \ 973 GD32_PINMUX_AF('I', 7, AF15) 974 #define EVENTOUT_PI8 \ 975 GD32_PINMUX_AF('I', 8, AF15) 976 #define EVENTOUT_PI9 \ 977 GD32_PINMUX_AF('I', 9, AF15) 978 #define EVENTOUT_PI10 \ 979 GD32_PINMUX_AF('I', 10, AF15) 980 #define EVENTOUT_PI11 \ 981 GD32_PINMUX_AF('I', 11, AF15) 982 983 /* EXMC_A0 */ 984 #define EXMC_A0_PF0 \ 985 GD32_PINMUX_AF('F', 0, AF12) 986 987 /* EXMC_A1 */ 988 #define EXMC_A1_PF1 \ 989 GD32_PINMUX_AF('F', 1, AF12) 990 991 /* EXMC_A10 */ 992 #define EXMC_A10_PG0 \ 993 GD32_PINMUX_AF('G', 0, AF12) 994 995 /* EXMC_A11 */ 996 #define EXMC_A11_PG1 \ 997 GD32_PINMUX_AF('G', 1, AF12) 998 999 /* EXMC_A12 */ 1000 #define EXMC_A12_PG2 \ 1001 GD32_PINMUX_AF('G', 2, AF12) 1002 1003 /* EXMC_A13 */ 1004 #define EXMC_A13_PG3 \ 1005 GD32_PINMUX_AF('G', 3, AF12) 1006 1007 /* EXMC_A14 */ 1008 #define EXMC_A14_PG4 \ 1009 GD32_PINMUX_AF('G', 4, AF12) 1010 1011 /* EXMC_A15 */ 1012 #define EXMC_A15_PG5 \ 1013 GD32_PINMUX_AF('G', 5, AF12) 1014 1015 /* EXMC_A16 */ 1016 #define EXMC_A16_PD11 \ 1017 GD32_PINMUX_AF('D', 11, AF12) 1018 1019 /* EXMC_A17 */ 1020 #define EXMC_A17_PD12 \ 1021 GD32_PINMUX_AF('D', 12, AF12) 1022 1023 /* EXMC_A18 */ 1024 #define EXMC_A18_PD13 \ 1025 GD32_PINMUX_AF('D', 13, AF12) 1026 1027 /* EXMC_A19 */ 1028 #define EXMC_A19_PE3 \ 1029 GD32_PINMUX_AF('E', 3, AF12) 1030 1031 /* EXMC_A2 */ 1032 #define EXMC_A2_PF2 \ 1033 GD32_PINMUX_AF('F', 2, AF12) 1034 1035 /* EXMC_A20 */ 1036 #define EXMC_A20_PE4 \ 1037 GD32_PINMUX_AF('E', 4, AF12) 1038 1039 /* EXMC_A21 */ 1040 #define EXMC_A21_PE5 \ 1041 GD32_PINMUX_AF('E', 5, AF12) 1042 1043 /* EXMC_A22 */ 1044 #define EXMC_A22_PE6 \ 1045 GD32_PINMUX_AF('E', 6, AF12) 1046 1047 /* EXMC_A23 */ 1048 #define EXMC_A23_PE2 \ 1049 GD32_PINMUX_AF('E', 2, AF12) 1050 1051 /* EXMC_A24 */ 1052 #define EXMC_A24_PG13 \ 1053 GD32_PINMUX_AF('G', 13, AF12) 1054 1055 /* EXMC_A25 */ 1056 #define EXMC_A25_PG14 \ 1057 GD32_PINMUX_AF('G', 14, AF12) 1058 1059 /* EXMC_A3 */ 1060 #define EXMC_A3_PF3 \ 1061 GD32_PINMUX_AF('F', 3, AF12) 1062 1063 /* EXMC_A4 */ 1064 #define EXMC_A4_PF4 \ 1065 GD32_PINMUX_AF('F', 4, AF12) 1066 1067 /* EXMC_A5 */ 1068 #define EXMC_A5_PF5 \ 1069 GD32_PINMUX_AF('F', 5, AF12) 1070 1071 /* EXMC_A6 */ 1072 #define EXMC_A6_PF12 \ 1073 GD32_PINMUX_AF('F', 12, AF12) 1074 1075 /* EXMC_A7 */ 1076 #define EXMC_A7_PF13 \ 1077 GD32_PINMUX_AF('F', 13, AF12) 1078 1079 /* EXMC_A8 */ 1080 #define EXMC_A8_PF14 \ 1081 GD32_PINMUX_AF('F', 14, AF12) 1082 1083 /* EXMC_A9 */ 1084 #define EXMC_A9_PF15 \ 1085 GD32_PINMUX_AF('F', 15, AF12) 1086 1087 /* EXMC_CD */ 1088 #define EXMC_CD_PF9 \ 1089 GD32_PINMUX_AF('F', 9, AF12) 1090 1091 /* EXMC_CLK */ 1092 #define EXMC_CLK_PD3 \ 1093 GD32_PINMUX_AF('D', 3, AF12) 1094 1095 /* EXMC_D0 */ 1096 #define EXMC_D0_PD14 \ 1097 GD32_PINMUX_AF('D', 14, AF12) 1098 1099 /* EXMC_D1 */ 1100 #define EXMC_D1_PD15 \ 1101 GD32_PINMUX_AF('D', 15, AF12) 1102 1103 /* EXMC_D10 */ 1104 #define EXMC_D10_PE13 \ 1105 GD32_PINMUX_AF('E', 13, AF12) 1106 1107 /* EXMC_D11 */ 1108 #define EXMC_D11_PE14 \ 1109 GD32_PINMUX_AF('E', 14, AF12) 1110 1111 /* EXMC_D12 */ 1112 #define EXMC_D12_PE15 \ 1113 GD32_PINMUX_AF('E', 15, AF12) 1114 1115 /* EXMC_D13 */ 1116 #define EXMC_D13_PD8 \ 1117 GD32_PINMUX_AF('D', 8, AF12) 1118 1119 /* EXMC_D14 */ 1120 #define EXMC_D14_PD9 \ 1121 GD32_PINMUX_AF('D', 9, AF12) 1122 1123 /* EXMC_D15 */ 1124 #define EXMC_D15_PD10 \ 1125 GD32_PINMUX_AF('D', 10, AF12) 1126 1127 /* EXMC_D16 */ 1128 #define EXMC_D16_PH8 \ 1129 GD32_PINMUX_AF('H', 8, AF12) 1130 1131 /* EXMC_D17 */ 1132 #define EXMC_D17_PH9 \ 1133 GD32_PINMUX_AF('H', 9, AF12) 1134 1135 /* EXMC_D18 */ 1136 #define EXMC_D18_PH10 \ 1137 GD32_PINMUX_AF('H', 10, AF12) 1138 1139 /* EXMC_D19 */ 1140 #define EXMC_D19_PH11 \ 1141 GD32_PINMUX_AF('H', 11, AF12) 1142 1143 /* EXMC_D2 */ 1144 #define EXMC_D2_PD0 \ 1145 GD32_PINMUX_AF('D', 0, AF12) 1146 1147 /* EXMC_D20 */ 1148 #define EXMC_D20_PH12 \ 1149 GD32_PINMUX_AF('H', 12, AF12) 1150 1151 /* EXMC_D21 */ 1152 #define EXMC_D21_PH13 \ 1153 GD32_PINMUX_AF('H', 13, AF12) 1154 1155 /* EXMC_D22 */ 1156 #define EXMC_D22_PH14 \ 1157 GD32_PINMUX_AF('H', 14, AF12) 1158 1159 /* EXMC_D23 */ 1160 #define EXMC_D23_PH15 \ 1161 GD32_PINMUX_AF('H', 15, AF12) 1162 1163 /* EXMC_D24 */ 1164 #define EXMC_D24_PI0 \ 1165 GD32_PINMUX_AF('I', 0, AF12) 1166 1167 /* EXMC_D25 */ 1168 #define EXMC_D25_PI1 \ 1169 GD32_PINMUX_AF('I', 1, AF12) 1170 1171 /* EXMC_D26 */ 1172 #define EXMC_D26_PI2 \ 1173 GD32_PINMUX_AF('I', 2, AF12) 1174 1175 /* EXMC_D27 */ 1176 #define EXMC_D27_PI3 \ 1177 GD32_PINMUX_AF('I', 3, AF12) 1178 1179 /* EXMC_D28 */ 1180 #define EXMC_D28_PI6 \ 1181 GD32_PINMUX_AF('I', 6, AF12) 1182 1183 /* EXMC_D29 */ 1184 #define EXMC_D29_PI7 \ 1185 GD32_PINMUX_AF('I', 7, AF12) 1186 1187 /* EXMC_D3 */ 1188 #define EXMC_D3_PD1 \ 1189 GD32_PINMUX_AF('D', 1, AF12) 1190 1191 /* EXMC_D30 */ 1192 #define EXMC_D30_PI9 \ 1193 GD32_PINMUX_AF('I', 9, AF12) 1194 1195 /* EXMC_D31 */ 1196 #define EXMC_D31_PI10 \ 1197 GD32_PINMUX_AF('I', 10, AF12) 1198 1199 /* EXMC_D4 */ 1200 #define EXMC_D4_PE7 \ 1201 GD32_PINMUX_AF('E', 7, AF12) 1202 1203 /* EXMC_D5 */ 1204 #define EXMC_D5_PE8 \ 1205 GD32_PINMUX_AF('E', 8, AF12) 1206 1207 /* EXMC_D6 */ 1208 #define EXMC_D6_PE9 \ 1209 GD32_PINMUX_AF('E', 9, AF12) 1210 1211 /* EXMC_D7 */ 1212 #define EXMC_D7_PE10 \ 1213 GD32_PINMUX_AF('E', 10, AF12) 1214 1215 /* EXMC_D8 */ 1216 #define EXMC_D8_PE11 \ 1217 GD32_PINMUX_AF('E', 11, AF12) 1218 1219 /* EXMC_D9 */ 1220 #define EXMC_D9_PE12 \ 1221 GD32_PINMUX_AF('E', 12, AF12) 1222 1223 /* EXMC_INT1 */ 1224 #define EXMC_INT1_PG6 \ 1225 GD32_PINMUX_AF('G', 6, AF12) 1226 1227 /* EXMC_INT2 */ 1228 #define EXMC_INT2_PG7 \ 1229 GD32_PINMUX_AF('G', 7, AF12) 1230 1231 /* EXMC_INTR */ 1232 #define EXMC_INTR_PF10 \ 1233 GD32_PINMUX_AF('F', 10, AF12) 1234 1235 /* EXMC_NBL0 */ 1236 #define EXMC_NBL0_PE0 \ 1237 GD32_PINMUX_AF('E', 0, AF12) 1238 1239 /* EXMC_NBL1 */ 1240 #define EXMC_NBL1_PE1 \ 1241 GD32_PINMUX_AF('E', 1, AF12) 1242 1243 /* EXMC_NBL2 */ 1244 #define EXMC_NBL2_PI4 \ 1245 GD32_PINMUX_AF('I', 4, AF12) 1246 1247 /* EXMC_NBL3 */ 1248 #define EXMC_NBL3_PI5 \ 1249 GD32_PINMUX_AF('I', 5, AF12) 1250 1251 /* EXMC_NCE1 */ 1252 #define EXMC_NCE1_PD7 \ 1253 GD32_PINMUX_AF('D', 7, AF12) 1254 1255 /* EXMC_NCE2 */ 1256 #define EXMC_NCE2_PG9 \ 1257 GD32_PINMUX_AF('G', 9, AF12) 1258 1259 /* EXMC_NCE3_0 */ 1260 #define EXMC_NCE3_0_PG10 \ 1261 GD32_PINMUX_AF('G', 10, AF12) 1262 1263 /* EXMC_NCE3_1 */ 1264 #define EXMC_NCE3_1_PG11 \ 1265 GD32_PINMUX_AF('G', 11, AF12) 1266 1267 /* EXMC_NE0 */ 1268 #define EXMC_NE0_PD7 \ 1269 GD32_PINMUX_AF('D', 7, AF12) 1270 1271 /* EXMC_NE1 */ 1272 #define EXMC_NE1_PG9 \ 1273 GD32_PINMUX_AF('G', 9, AF12) 1274 1275 /* EXMC_NE2 */ 1276 #define EXMC_NE2_PG10 \ 1277 GD32_PINMUX_AF('G', 10, AF12) 1278 1279 /* EXMC_NE3 */ 1280 #define EXMC_NE3_PG12 \ 1281 GD32_PINMUX_AF('G', 12, AF12) 1282 1283 /* EXMC_NIORD */ 1284 #define EXMC_NIORD_PF6 \ 1285 GD32_PINMUX_AF('F', 6, AF12) 1286 1287 /* EXMC_NIOWR */ 1288 #define EXMC_NIOWR_PF8 \ 1289 GD32_PINMUX_AF('F', 8, AF12) 1290 1291 /* EXMC_NL */ 1292 #define EXMC_NL_PB7 \ 1293 GD32_PINMUX_AF('B', 7, AF12) 1294 1295 /* EXMC_NOE */ 1296 #define EXMC_NOE_PD4 \ 1297 GD32_PINMUX_AF('D', 4, AF12) 1298 1299 /* EXMC_NREG */ 1300 #define EXMC_NREG_PF7 \ 1301 GD32_PINMUX_AF('F', 7, AF12) 1302 1303 /* EXMC_NWAIT */ 1304 #define EXMC_NWAIT_PD6 \ 1305 GD32_PINMUX_AF('D', 6, AF12) 1306 1307 /* EXMC_NWE */ 1308 #define EXMC_NWE_PD5 \ 1309 GD32_PINMUX_AF('D', 5, AF12) 1310 1311 /* EXMC_SDCKE0 */ 1312 #define EXMC_SDCKE0_PC3 \ 1313 GD32_PINMUX_AF('C', 3, AF12) 1314 #define EXMC_SDCKE0_PC5 \ 1315 GD32_PINMUX_AF('C', 5, AF12) 1316 #define EXMC_SDCKE0_PH2 \ 1317 GD32_PINMUX_AF('H', 2, AF12) 1318 1319 /* EXMC_SDCKE1 */ 1320 #define EXMC_SDCKE1_PB5 \ 1321 GD32_PINMUX_AF('B', 5, AF12) 1322 #define EXMC_SDCKE1_PH7 \ 1323 GD32_PINMUX_AF('H', 7, AF12) 1324 1325 /* EXMC_SDCLK */ 1326 #define EXMC_SDCLK_PG8 \ 1327 GD32_PINMUX_AF('G', 8, AF12) 1328 1329 /* EXMC_SDNCAS */ 1330 #define EXMC_SDNCAS_PG15 \ 1331 GD32_PINMUX_AF('G', 15, AF12) 1332 1333 /* EXMC_SDNE0 */ 1334 #define EXMC_SDNE0_PC2 \ 1335 GD32_PINMUX_AF('C', 2, AF12) 1336 #define EXMC_SDNE0_PH3 \ 1337 GD32_PINMUX_AF('H', 3, AF12) 1338 1339 /* EXMC_SDNE1 */ 1340 #define EXMC_SDNE1_PB6 \ 1341 GD32_PINMUX_AF('B', 6, AF12) 1342 #define EXMC_SDNE1_PH6 \ 1343 GD32_PINMUX_AF('H', 6, AF12) 1344 1345 /* EXMC_SDNRAS */ 1346 #define EXMC_SDNRAS_PF11 \ 1347 GD32_PINMUX_AF('F', 11, AF12) 1348 1349 /* EXMC_SDNWE */ 1350 #define EXMC_SDNWE_PA7 \ 1351 GD32_PINMUX_AF('A', 7, AF12) 1352 #define EXMC_SDNWE_PC0 \ 1353 GD32_PINMUX_AF('C', 0, AF12) 1354 #define EXMC_SDNWE_PH5 \ 1355 GD32_PINMUX_AF('H', 5, AF12) 1356 1357 /* I2C0_SCL */ 1358 #define I2C0_SCL_PB6 \ 1359 GD32_PINMUX_AF('B', 6, AF4) 1360 #define I2C0_SCL_PB8 \ 1361 GD32_PINMUX_AF('B', 8, AF4) 1362 1363 /* I2C0_SDA */ 1364 #define I2C0_SDA_PB7 \ 1365 GD32_PINMUX_AF('B', 7, AF4) 1366 #define I2C0_SDA_PB9 \ 1367 GD32_PINMUX_AF('B', 9, AF4) 1368 1369 /* I2C0_SMBA */ 1370 #define I2C0_SMBA_PB5 \ 1371 GD32_PINMUX_AF('B', 5, AF4) 1372 1373 /* I2C0_TXFRAME */ 1374 #define I2C0_TXFRAME_PB4 \ 1375 GD32_PINMUX_AF('B', 4, AF4) 1376 1377 /* I2C1_SCL */ 1378 #define I2C1_SCL_PB10 \ 1379 GD32_PINMUX_AF('B', 10, AF4) 1380 #define I2C1_SCL_PF1 \ 1381 GD32_PINMUX_AF('F', 1, AF4) 1382 #define I2C1_SCL_PH4 \ 1383 GD32_PINMUX_AF('H', 4, AF4) 1384 1385 /* I2C1_SDA */ 1386 #define I2C1_SDA_PB3 \ 1387 GD32_PINMUX_AF('B', 3, AF9) 1388 #define I2C1_SDA_PB11 \ 1389 GD32_PINMUX_AF('B', 11, AF4) 1390 #define I2C1_SDA_PC12 \ 1391 GD32_PINMUX_AF('C', 12, AF4) 1392 #define I2C1_SDA_PF0 \ 1393 GD32_PINMUX_AF('F', 0, AF4) 1394 #define I2C1_SDA_PH5 \ 1395 GD32_PINMUX_AF('H', 5, AF4) 1396 1397 /* I2C1_SMBA */ 1398 #define I2C1_SMBA_PB12 \ 1399 GD32_PINMUX_AF('B', 12, AF4) 1400 #define I2C1_SMBA_PF2 \ 1401 GD32_PINMUX_AF('F', 2, AF4) 1402 #define I2C1_SMBA_PH6 \ 1403 GD32_PINMUX_AF('H', 6, AF4) 1404 1405 /* I2C1_TXFRAME */ 1406 #define I2C1_TXFRAME_PB13 \ 1407 GD32_PINMUX_AF('B', 13, AF4) 1408 #define I2C1_TXFRAME_PF3 \ 1409 GD32_PINMUX_AF('F', 3, AF4) 1410 #define I2C1_TXFRAME_PH3 \ 1411 GD32_PINMUX_AF('H', 3, AF4) 1412 1413 /* I2C2_SCL */ 1414 #define I2C2_SCL_PA8 \ 1415 GD32_PINMUX_AF('A', 8, AF4) 1416 #define I2C2_SCL_PH7 \ 1417 GD32_PINMUX_AF('H', 7, AF4) 1418 1419 /* I2C2_SDA */ 1420 #define I2C2_SDA_PB4 \ 1421 GD32_PINMUX_AF('B', 4, AF9) 1422 #define I2C2_SDA_PC9 \ 1423 GD32_PINMUX_AF('C', 9, AF4) 1424 #define I2C2_SDA_PH8 \ 1425 GD32_PINMUX_AF('H', 8, AF4) 1426 1427 /* I2C2_SMBA */ 1428 #define I2C2_SMBA_PA9 \ 1429 GD32_PINMUX_AF('A', 9, AF4) 1430 #define I2C2_SMBA_PH9 \ 1431 GD32_PINMUX_AF('H', 9, AF4) 1432 1433 /* I2C2_TXFRAME */ 1434 #define I2C2_TXFRAME_PA10 \ 1435 GD32_PINMUX_AF('A', 10, AF4) 1436 #define I2C2_TXFRAME_PH10 \ 1437 GD32_PINMUX_AF('H', 10, AF4) 1438 1439 /* I2S1_ADD_SD */ 1440 #define I2S1_ADD_SD_PB14 \ 1441 GD32_PINMUX_AF('B', 14, AF6) 1442 #define I2S1_ADD_SD_PC2 \ 1443 GD32_PINMUX_AF('C', 2, AF6) 1444 #define I2S1_ADD_SD_PI2 \ 1445 GD32_PINMUX_AF('I', 2, AF6) 1446 1447 /* I2S1_CK */ 1448 #define I2S1_CK_PA9 \ 1449 GD32_PINMUX_AF('A', 9, AF5) 1450 #define I2S1_CK_PB10 \ 1451 GD32_PINMUX_AF('B', 10, AF5) 1452 #define I2S1_CK_PB13 \ 1453 GD32_PINMUX_AF('B', 13, AF5) 1454 #define I2S1_CK_PC7 \ 1455 GD32_PINMUX_AF('C', 7, AF5) 1456 #define I2S1_CK_PD3 \ 1457 GD32_PINMUX_AF('D', 3, AF5) 1458 #define I2S1_CK_PI1 \ 1459 GD32_PINMUX_AF('I', 1, AF5) 1460 1461 /* I2S1_MCK */ 1462 #define I2S1_MCK_PA3 \ 1463 GD32_PINMUX_AF('A', 3, AF5) 1464 #define I2S1_MCK_PA6 \ 1465 GD32_PINMUX_AF('A', 6, AF6) 1466 #define I2S1_MCK_PC6 \ 1467 GD32_PINMUX_AF('C', 6, AF5) 1468 1469 /* I2S1_NSS */ 1470 #define I2S1_NSS_PB9 \ 1471 GD32_PINMUX_AF('B', 9, AF5) 1472 1473 /* I2S1_SD */ 1474 #define I2S1_SD_PB15 \ 1475 GD32_PINMUX_AF('B', 15, AF5) 1476 #define I2S1_SD_PC1 \ 1477 GD32_PINMUX_AF('C', 1, AF7) 1478 #define I2S1_SD_PC3 \ 1479 GD32_PINMUX_AF('C', 3, AF5) 1480 #define I2S1_SD_PI3 \ 1481 GD32_PINMUX_AF('I', 3, AF5) 1482 1483 /* I2S1_WS */ 1484 #define I2S1_WS_PB12 \ 1485 GD32_PINMUX_AF('B', 12, AF5) 1486 #define I2S1_WS_PD1 \ 1487 GD32_PINMUX_AF('D', 1, AF7) 1488 #define I2S1_WS_PI0 \ 1489 GD32_PINMUX_AF('I', 0, AF5) 1490 1491 /* I2S2_ADD_SD */ 1492 #define I2S2_ADD_SD_PB4 \ 1493 GD32_PINMUX_AF('B', 4, AF7) 1494 #define I2S2_ADD_SD_PC11 \ 1495 GD32_PINMUX_AF('C', 11, AF5) 1496 1497 /* I2S2_CK */ 1498 #define I2S2_CK_PB3 \ 1499 GD32_PINMUX_AF('B', 3, AF6) 1500 #define I2S2_CK_PC10 \ 1501 GD32_PINMUX_AF('C', 10, AF6) 1502 1503 /* I2S2_MCK */ 1504 #define I2S2_MCK_PB10 \ 1505 GD32_PINMUX_AF('B', 10, AF6) 1506 #define I2S2_MCK_PC7 \ 1507 GD32_PINMUX_AF('C', 7, AF6) 1508 1509 /* I2S2_SD */ 1510 #define I2S2_SD_PB0 \ 1511 GD32_PINMUX_AF('B', 0, AF7) 1512 #define I2S2_SD_PB2 \ 1513 GD32_PINMUX_AF('B', 2, AF7) 1514 #define I2S2_SD_PB5 \ 1515 GD32_PINMUX_AF('B', 5, AF6) 1516 #define I2S2_SD_PC1 \ 1517 GD32_PINMUX_AF('C', 1, AF5) 1518 #define I2S2_SD_PC12 \ 1519 GD32_PINMUX_AF('C', 12, AF6) 1520 #define I2S2_SD_PD0 \ 1521 GD32_PINMUX_AF('D', 0, AF6) 1522 #define I2S2_SD_PD6 \ 1523 GD32_PINMUX_AF('D', 6, AF5) 1524 1525 /* I2S2_WS */ 1526 #define I2S2_WS_PA4 \ 1527 GD32_PINMUX_AF('A', 4, AF6) 1528 #define I2S2_WS_PA15 \ 1529 GD32_PINMUX_AF('A', 15, AF6) 1530 1531 /* I2S_CKIN */ 1532 #define I2S_CKIN_PA2 \ 1533 GD32_PINMUX_AF('A', 2, AF5) 1534 #define I2S_CKIN_PB11 \ 1535 GD32_PINMUX_AF('B', 11, AF5) 1536 #define I2S_CKIN_PC9 \ 1537 GD32_PINMUX_AF('C', 9, AF5) 1538 1539 /* JNTRST */ 1540 #define JNTRST_PB4 \ 1541 GD32_PINMUX_AF('B', 4, AF0) 1542 1543 /* JTCK */ 1544 #define JTCK_PA14 \ 1545 GD32_PINMUX_AF('A', 14, AF0) 1546 1547 /* JTDI */ 1548 #define JTDI_PA15 \ 1549 GD32_PINMUX_AF('A', 15, AF0) 1550 1551 /* JTDO */ 1552 #define JTDO_PB3 \ 1553 GD32_PINMUX_AF('B', 3, AF0) 1554 1555 /* JTMS */ 1556 #define JTMS_PA13 \ 1557 GD32_PINMUX_AF('A', 13, AF0) 1558 1559 /* RTC_REFIN */ 1560 #define RTC_REFIN_PB15 \ 1561 GD32_PINMUX_AF('B', 15, AF0) 1562 1563 /* SDIO_CK */ 1564 #define SDIO_CK_PB2 \ 1565 GD32_PINMUX_AF('B', 2, AF12) 1566 #define SDIO_CK_PC12 \ 1567 GD32_PINMUX_AF('C', 12, AF12) 1568 1569 /* SDIO_CMD */ 1570 #define SDIO_CMD_PA6 \ 1571 GD32_PINMUX_AF('A', 6, AF12) 1572 #define SDIO_CMD_PD2 \ 1573 GD32_PINMUX_AF('D', 2, AF12) 1574 1575 /* SDIO_D0 */ 1576 #define SDIO_D0_PB4 \ 1577 GD32_PINMUX_AF('B', 4, AF12) 1578 #define SDIO_D0_PC8 \ 1579 GD32_PINMUX_AF('C', 8, AF12) 1580 1581 /* SDIO_D1 */ 1582 #define SDIO_D1_PA8 \ 1583 GD32_PINMUX_AF('A', 8, AF12) 1584 #define SDIO_D1_PB0 \ 1585 GD32_PINMUX_AF('B', 0, AF12) 1586 #define SDIO_D1_PC9 \ 1587 GD32_PINMUX_AF('C', 9, AF12) 1588 1589 /* SDIO_D2 */ 1590 #define SDIO_D2_PA9 \ 1591 GD32_PINMUX_AF('A', 9, AF12) 1592 #define SDIO_D2_PB1 \ 1593 GD32_PINMUX_AF('B', 1, AF12) 1594 #define SDIO_D2_PC10 \ 1595 GD32_PINMUX_AF('C', 10, AF12) 1596 1597 /* SDIO_D3 */ 1598 #define SDIO_D3_PC11 \ 1599 GD32_PINMUX_AF('C', 11, AF12) 1600 1601 /* SDIO_D4 */ 1602 #define SDIO_D4_PB8 \ 1603 GD32_PINMUX_AF('B', 8, AF12) 1604 1605 /* SDIO_D5 */ 1606 #define SDIO_D5_PB9 \ 1607 GD32_PINMUX_AF('B', 9, AF12) 1608 1609 /* SDIO_D6 */ 1610 #define SDIO_D6_PC6 \ 1611 GD32_PINMUX_AF('C', 6, AF12) 1612 1613 /* SDIO_D7 */ 1614 #define SDIO_D7_PB10 \ 1615 GD32_PINMUX_AF('B', 10, AF12) 1616 #define SDIO_D7_PC7 \ 1617 GD32_PINMUX_AF('C', 7, AF12) 1618 1619 /* SPI0_MISO */ 1620 #define SPI0_MISO_PA6 \ 1621 GD32_PINMUX_AF('A', 6, AF5) 1622 #define SPI0_MISO_PB4 \ 1623 GD32_PINMUX_AF('B', 4, AF5) 1624 1625 /* SPI0_MOSI */ 1626 #define SPI0_MOSI_PA7 \ 1627 GD32_PINMUX_AF('A', 7, AF5) 1628 #define SPI0_MOSI_PB5 \ 1629 GD32_PINMUX_AF('B', 5, AF5) 1630 1631 /* SPI0_NSS */ 1632 #define SPI0_NSS_PA4 \ 1633 GD32_PINMUX_AF('A', 4, AF5) 1634 #define SPI0_NSS_PA15 \ 1635 GD32_PINMUX_AF('A', 15, AF5) 1636 1637 /* SPI0_SCK */ 1638 #define SPI0_SCK_PA5 \ 1639 GD32_PINMUX_AF('A', 5, AF5) 1640 #define SPI0_SCK_PB3 \ 1641 GD32_PINMUX_AF('B', 3, AF5) 1642 1643 /* SPI1_MISO */ 1644 #define SPI1_MISO_PB14 \ 1645 GD32_PINMUX_AF('B', 14, AF5) 1646 #define SPI1_MISO_PC2 \ 1647 GD32_PINMUX_AF('C', 2, AF5) 1648 #define SPI1_MISO_PI2 \ 1649 GD32_PINMUX_AF('I', 2, AF5) 1650 1651 /* SPI1_MOSI */ 1652 #define SPI1_MOSI_PB15 \ 1653 GD32_PINMUX_AF('B', 15, AF5) 1654 #define SPI1_MOSI_PC1 \ 1655 GD32_PINMUX_AF('C', 1, AF7) 1656 #define SPI1_MOSI_PC3 \ 1657 GD32_PINMUX_AF('C', 3, AF5) 1658 #define SPI1_MOSI_PI3 \ 1659 GD32_PINMUX_AF('I', 3, AF5) 1660 1661 /* SPI1_NSS */ 1662 #define SPI1_NSS_PB9 \ 1663 GD32_PINMUX_AF('B', 9, AF5) 1664 #define SPI1_NSS_PB12 \ 1665 GD32_PINMUX_AF('B', 12, AF5) 1666 #define SPI1_NSS_PD1 \ 1667 GD32_PINMUX_AF('D', 1, AF7) 1668 #define SPI1_NSS_PI0 \ 1669 GD32_PINMUX_AF('I', 0, AF5) 1670 1671 /* SPI1_SCK */ 1672 #define SPI1_SCK_PA9 \ 1673 GD32_PINMUX_AF('A', 9, AF5) 1674 #define SPI1_SCK_PB10 \ 1675 GD32_PINMUX_AF('B', 10, AF5) 1676 #define SPI1_SCK_PB13 \ 1677 GD32_PINMUX_AF('B', 13, AF5) 1678 #define SPI1_SCK_PC7 \ 1679 GD32_PINMUX_AF('C', 7, AF5) 1680 #define SPI1_SCK_PD3 \ 1681 GD32_PINMUX_AF('D', 3, AF5) 1682 #define SPI1_SCK_PI1 \ 1683 GD32_PINMUX_AF('I', 1, AF5) 1684 1685 /* SPI2_MISO */ 1686 #define SPI2_MISO_PB4 \ 1687 GD32_PINMUX_AF('B', 4, AF6) 1688 #define SPI2_MISO_PC11 \ 1689 GD32_PINMUX_AF('C', 11, AF6) 1690 1691 /* SPI2_MOSI */ 1692 #define SPI2_MOSI_PB0 \ 1693 GD32_PINMUX_AF('B', 0, AF7) 1694 #define SPI2_MOSI_PB2 \ 1695 GD32_PINMUX_AF('B', 2, AF7) 1696 #define SPI2_MOSI_PB5 \ 1697 GD32_PINMUX_AF('B', 5, AF6) 1698 #define SPI2_MOSI_PC1 \ 1699 GD32_PINMUX_AF('C', 1, AF5) 1700 #define SPI2_MOSI_PC12 \ 1701 GD32_PINMUX_AF('C', 12, AF6) 1702 #define SPI2_MOSI_PD0 \ 1703 GD32_PINMUX_AF('D', 0, AF6) 1704 #define SPI2_MOSI_PD6 \ 1705 GD32_PINMUX_AF('D', 6, AF5) 1706 1707 /* SPI2_NSS */ 1708 #define SPI2_NSS_PA4 \ 1709 GD32_PINMUX_AF('A', 4, AF6) 1710 #define SPI2_NSS_PA15 \ 1711 GD32_PINMUX_AF('A', 15, AF6) 1712 1713 /* SPI2_SCK */ 1714 #define SPI2_SCK_PB3 \ 1715 GD32_PINMUX_AF('B', 3, AF6) 1716 #define SPI2_SCK_PC10 \ 1717 GD32_PINMUX_AF('C', 10, AF6) 1718 1719 /* SPI3_MISO */ 1720 #define SPI3_MISO_PA11 \ 1721 GD32_PINMUX_AF('A', 11, AF6) 1722 #define SPI3_MISO_PD0 \ 1723 GD32_PINMUX_AF('D', 0, AF5) 1724 #define SPI3_MISO_PE5 \ 1725 GD32_PINMUX_AF('E', 5, AF5) 1726 #define SPI3_MISO_PE13 \ 1727 GD32_PINMUX_AF('E', 13, AF5) 1728 #define SPI3_MISO_PG12 \ 1729 GD32_PINMUX_AF('G', 12, AF6) 1730 1731 /* SPI3_MOSI */ 1732 #define SPI3_MOSI_PA1 \ 1733 GD32_PINMUX_AF('A', 1, AF5) 1734 #define SPI3_MOSI_PE6 \ 1735 GD32_PINMUX_AF('E', 6, AF5) 1736 #define SPI3_MOSI_PE14 \ 1737 GD32_PINMUX_AF('E', 14, AF5) 1738 #define SPI3_MOSI_PG13 \ 1739 GD32_PINMUX_AF('G', 13, AF6) 1740 1741 /* SPI3_NSS */ 1742 #define SPI3_NSS_PB12 \ 1743 GD32_PINMUX_AF('B', 12, AF6) 1744 #define SPI3_NSS_PE4 \ 1745 GD32_PINMUX_AF('E', 4, AF5) 1746 #define SPI3_NSS_PE11 \ 1747 GD32_PINMUX_AF('E', 11, AF5) 1748 #define SPI3_NSS_PG14 \ 1749 GD32_PINMUX_AF('G', 14, AF6) 1750 1751 /* SPI3_SCK */ 1752 #define SPI3_SCK_PB13 \ 1753 GD32_PINMUX_AF('B', 13, AF6) 1754 #define SPI3_SCK_PE2 \ 1755 GD32_PINMUX_AF('E', 2, AF5) 1756 #define SPI3_SCK_PE12 \ 1757 GD32_PINMUX_AF('E', 12, AF5) 1758 #define SPI3_SCK_PG11 \ 1759 GD32_PINMUX_AF('G', 11, AF6) 1760 1761 /* SPI4_MISO */ 1762 #define SPI4_MISO_PA12 \ 1763 GD32_PINMUX_AF('A', 12, AF6) 1764 #define SPI4_MISO_PE13 \ 1765 GD32_PINMUX_AF('E', 13, AF6) 1766 #define SPI4_MISO_PF8 \ 1767 GD32_PINMUX_AF('F', 8, AF5) 1768 #define SPI4_MISO_PH7 \ 1769 GD32_PINMUX_AF('H', 7, AF5) 1770 1771 /* SPI4_MOSI */ 1772 #define SPI4_MOSI_PA10 \ 1773 GD32_PINMUX_AF('A', 10, AF6) 1774 #define SPI4_MOSI_PB8 \ 1775 GD32_PINMUX_AF('B', 8, AF6) 1776 #define SPI4_MOSI_PE14 \ 1777 GD32_PINMUX_AF('E', 14, AF6) 1778 #define SPI4_MOSI_PF9 \ 1779 GD32_PINMUX_AF('F', 9, AF5) 1780 #define SPI4_MOSI_PF11 \ 1781 GD32_PINMUX_AF('F', 11, AF5) 1782 1783 /* SPI4_NSS */ 1784 #define SPI4_NSS_PB1 \ 1785 GD32_PINMUX_AF('B', 1, AF6) 1786 #define SPI4_NSS_PE11 \ 1787 GD32_PINMUX_AF('E', 11, AF6) 1788 #define SPI4_NSS_PF6 \ 1789 GD32_PINMUX_AF('F', 6, AF5) 1790 #define SPI4_NSS_PH5 \ 1791 GD32_PINMUX_AF('H', 5, AF5) 1792 1793 /* SPI4_SCK */ 1794 #define SPI4_SCK_PB0 \ 1795 GD32_PINMUX_AF('B', 0, AF6) 1796 #define SPI4_SCK_PE12 \ 1797 GD32_PINMUX_AF('E', 12, AF6) 1798 #define SPI4_SCK_PF7 \ 1799 GD32_PINMUX_AF('F', 7, AF5) 1800 #define SPI4_SCK_PH6 \ 1801 GD32_PINMUX_AF('H', 6, AF5) 1802 1803 /* SPI5_IO2 */ 1804 #define SPI5_IO2_PG10 \ 1805 GD32_PINMUX_AF('G', 10, AF5) 1806 1807 /* SPI5_IO3 */ 1808 #define SPI5_IO3_PG11 \ 1809 GD32_PINMUX_AF('G', 11, AF5) 1810 1811 /* SPI5_MISO */ 1812 #define SPI5_MISO_PG12 \ 1813 GD32_PINMUX_AF('G', 12, AF5) 1814 1815 /* SPI5_MOSI */ 1816 #define SPI5_MOSI_PG14 \ 1817 GD32_PINMUX_AF('G', 14, AF5) 1818 1819 /* SPI5_NSS */ 1820 #define SPI5_NSS_PG8 \ 1821 GD32_PINMUX_AF('G', 8, AF5) 1822 1823 /* SPI5_SCK */ 1824 #define SPI5_SCK_PG13 \ 1825 GD32_PINMUX_AF('G', 13, AF5) 1826 1827 /* SWCLK */ 1828 #define SWCLK_PA14 \ 1829 GD32_PINMUX_AF('A', 14, AF0) 1830 1831 /* SWDIO */ 1832 #define SWDIO_PA13 \ 1833 GD32_PINMUX_AF('A', 13, AF0) 1834 1835 /* TIMER0_BRKIN */ 1836 #define TIMER0_BRKIN_PA6 \ 1837 GD32_PINMUX_AF('A', 6, AF1) 1838 #define TIMER0_BRKIN_PB12 \ 1839 GD32_PINMUX_AF('B', 12, AF1) 1840 #define TIMER0_BRKIN_PE15 \ 1841 GD32_PINMUX_AF('E', 15, AF1) 1842 1843 /* TIMER0_CH0 */ 1844 #define TIMER0_CH0_PA8 \ 1845 GD32_PINMUX_AF('A', 8, AF1) 1846 #define TIMER0_CH0_PE9 \ 1847 GD32_PINMUX_AF('E', 9, AF1) 1848 1849 /* TIMER0_CH0_ON */ 1850 #define TIMER0_CH0_ON_PA7 \ 1851 GD32_PINMUX_AF('A', 7, AF1) 1852 #define TIMER0_CH0_ON_PB13 \ 1853 GD32_PINMUX_AF('B', 13, AF1) 1854 #define TIMER0_CH0_ON_PE8 \ 1855 GD32_PINMUX_AF('E', 8, AF1) 1856 1857 /* TIMER0_CH1 */ 1858 #define TIMER0_CH1_PA9 \ 1859 GD32_PINMUX_AF('A', 9, AF1) 1860 #define TIMER0_CH1_PE11 \ 1861 GD32_PINMUX_AF('E', 11, AF1) 1862 1863 /* TIMER0_CH1_ON */ 1864 #define TIMER0_CH1_ON_PB0 \ 1865 GD32_PINMUX_AF('B', 0, AF1) 1866 #define TIMER0_CH1_ON_PB1 \ 1867 GD32_PINMUX_AF('B', 1, AF1) 1868 #define TIMER0_CH1_ON_PB14 \ 1869 GD32_PINMUX_AF('B', 14, AF1) 1870 #define TIMER0_CH1_ON_PE1 \ 1871 GD32_PINMUX_AF('E', 1, AF1) 1872 #define TIMER0_CH1_ON_PE10 \ 1873 GD32_PINMUX_AF('E', 10, AF1) 1874 1875 /* TIMER0_CH2 */ 1876 #define TIMER0_CH2_PA10 \ 1877 GD32_PINMUX_AF('A', 10, AF1) 1878 #define TIMER0_CH2_PE13 \ 1879 GD32_PINMUX_AF('E', 13, AF1) 1880 1881 /* TIMER0_CH2_ON */ 1882 #define TIMER0_CH2_ON_PB15 \ 1883 GD32_PINMUX_AF('B', 15, AF1) 1884 #define TIMER0_CH2_ON_PE12 \ 1885 GD32_PINMUX_AF('E', 12, AF1) 1886 1887 /* TIMER0_CH3 */ 1888 #define TIMER0_CH3_PA11 \ 1889 GD32_PINMUX_AF('A', 11, AF1) 1890 #define TIMER0_CH3_PE14 \ 1891 GD32_PINMUX_AF('E', 14, AF1) 1892 1893 /* TIMER0_ETI */ 1894 #define TIMER0_ETI_PA12 \ 1895 GD32_PINMUX_AF('A', 12, AF1) 1896 #define TIMER0_ETI_PE7 \ 1897 GD32_PINMUX_AF('E', 7, AF1) 1898 1899 /* TIMER10_CH0 */ 1900 #define TIMER10_CH0_PB9 \ 1901 GD32_PINMUX_AF('B', 9, AF3) 1902 #define TIMER10_CH0_PF7 \ 1903 GD32_PINMUX_AF('F', 7, AF3) 1904 1905 /* TIMER11_CH0 */ 1906 #define TIMER11_CH0_PB14 \ 1907 GD32_PINMUX_AF('B', 14, AF9) 1908 #define TIMER11_CH0_PH6 \ 1909 GD32_PINMUX_AF('H', 6, AF9) 1910 1911 /* TIMER11_CH1 */ 1912 #define TIMER11_CH1_PB15 \ 1913 GD32_PINMUX_AF('B', 15, AF9) 1914 #define TIMER11_CH1_PH9 \ 1915 GD32_PINMUX_AF('H', 9, AF9) 1916 1917 /* TIMER12_CH0 */ 1918 #define TIMER12_CH0_PA6 \ 1919 GD32_PINMUX_AF('A', 6, AF9) 1920 #define TIMER12_CH0_PF8 \ 1921 GD32_PINMUX_AF('F', 8, AF9) 1922 1923 /* TIMER13_CH0 */ 1924 #define TIMER13_CH0_PA7 \ 1925 GD32_PINMUX_AF('A', 7, AF9) 1926 #define TIMER13_CH0_PF9 \ 1927 GD32_PINMUX_AF('F', 9, AF9) 1928 1929 /* TIMER1_CH0 */ 1930 #define TIMER1_CH0_PA0 \ 1931 GD32_PINMUX_AF('A', 0, AF1) 1932 #define TIMER1_CH0_PA5 \ 1933 GD32_PINMUX_AF('A', 5, AF1) 1934 #define TIMER1_CH0_PA15 \ 1935 GD32_PINMUX_AF('A', 15, AF1) 1936 #define TIMER1_CH0_PB8 \ 1937 GD32_PINMUX_AF('B', 8, AF1) 1938 1939 /* TIMER1_CH1 */ 1940 #define TIMER1_CH1_PA1 \ 1941 GD32_PINMUX_AF('A', 1, AF1) 1942 #define TIMER1_CH1_PB3 \ 1943 GD32_PINMUX_AF('B', 3, AF1) 1944 #define TIMER1_CH1_PB9 \ 1945 GD32_PINMUX_AF('B', 9, AF1) 1946 1947 /* TIMER1_CH2 */ 1948 #define TIMER1_CH2_PA2 \ 1949 GD32_PINMUX_AF('A', 2, AF1) 1950 #define TIMER1_CH2_PB10 \ 1951 GD32_PINMUX_AF('B', 10, AF1) 1952 1953 /* TIMER1_CH3 */ 1954 #define TIMER1_CH3_PA3 \ 1955 GD32_PINMUX_AF('A', 3, AF1) 1956 #define TIMER1_CH3_PB2 \ 1957 GD32_PINMUX_AF('B', 2, AF1) 1958 #define TIMER1_CH3_PB11 \ 1959 GD32_PINMUX_AF('B', 11, AF1) 1960 1961 /* TIMER1_ETI */ 1962 #define TIMER1_ETI_PA0 \ 1963 GD32_PINMUX_AF('A', 0, AF1) 1964 #define TIMER1_ETI_PA5 \ 1965 GD32_PINMUX_AF('A', 5, AF1) 1966 #define TIMER1_ETI_PA15 \ 1967 GD32_PINMUX_AF('A', 15, AF1) 1968 #define TIMER1_ETI_PB8 \ 1969 GD32_PINMUX_AF('B', 8, AF1) 1970 1971 /* TIMER2_CH0 */ 1972 #define TIMER2_CH0_PA6 \ 1973 GD32_PINMUX_AF('A', 6, AF2) 1974 #define TIMER2_CH0_PB4 \ 1975 GD32_PINMUX_AF('B', 4, AF2) 1976 #define TIMER2_CH0_PC6 \ 1977 GD32_PINMUX_AF('C', 6, AF2) 1978 1979 /* TIMER2_CH1 */ 1980 #define TIMER2_CH1_PA7 \ 1981 GD32_PINMUX_AF('A', 7, AF2) 1982 #define TIMER2_CH1_PB5 \ 1983 GD32_PINMUX_AF('B', 5, AF2) 1984 #define TIMER2_CH1_PC7 \ 1985 GD32_PINMUX_AF('C', 7, AF2) 1986 1987 /* TIMER2_CH2 */ 1988 #define TIMER2_CH2_PB0 \ 1989 GD32_PINMUX_AF('B', 0, AF2) 1990 #define TIMER2_CH2_PC8 \ 1991 GD32_PINMUX_AF('C', 8, AF2) 1992 1993 /* TIMER2_CH3 */ 1994 #define TIMER2_CH3_PB1 \ 1995 GD32_PINMUX_AF('B', 1, AF2) 1996 #define TIMER2_CH3_PC9 \ 1997 GD32_PINMUX_AF('C', 9, AF2) 1998 1999 /* TIMER2_ETI */ 2000 #define TIMER2_ETI_PD2 \ 2001 GD32_PINMUX_AF('D', 2, AF2) 2002 2003 /* TIMER3_CH0 */ 2004 #define TIMER3_CH0_PB6 \ 2005 GD32_PINMUX_AF('B', 6, AF2) 2006 #define TIMER3_CH0_PD12 \ 2007 GD32_PINMUX_AF('D', 12, AF2) 2008 2009 /* TIMER3_CH1 */ 2010 #define TIMER3_CH1_PB7 \ 2011 GD32_PINMUX_AF('B', 7, AF2) 2012 #define TIMER3_CH1_PD13 \ 2013 GD32_PINMUX_AF('D', 13, AF2) 2014 2015 /* TIMER3_CH2 */ 2016 #define TIMER3_CH2_PB8 \ 2017 GD32_PINMUX_AF('B', 8, AF2) 2018 #define TIMER3_CH2_PD14 \ 2019 GD32_PINMUX_AF('D', 14, AF2) 2020 2021 /* TIMER3_CH3 */ 2022 #define TIMER3_CH3_PB9 \ 2023 GD32_PINMUX_AF('B', 9, AF2) 2024 #define TIMER3_CH3_PD15 \ 2025 GD32_PINMUX_AF('D', 15, AF2) 2026 2027 /* TIMER3_ETI */ 2028 #define TIMER3_ETI_PE0 \ 2029 GD32_PINMUX_AF('E', 0, AF2) 2030 2031 /* TIMER4_CH0 */ 2032 #define TIMER4_CH0_PA0 \ 2033 GD32_PINMUX_AF('A', 0, AF2) 2034 #define TIMER4_CH0_PH10 \ 2035 GD32_PINMUX_AF('H', 10, AF2) 2036 2037 /* TIMER4_CH1 */ 2038 #define TIMER4_CH1_PA1 \ 2039 GD32_PINMUX_AF('A', 1, AF2) 2040 #define TIMER4_CH1_PH11 \ 2041 GD32_PINMUX_AF('H', 11, AF2) 2042 2043 /* TIMER4_CH2 */ 2044 #define TIMER4_CH2_PA2 \ 2045 GD32_PINMUX_AF('A', 2, AF2) 2046 #define TIMER4_CH2_PH12 \ 2047 GD32_PINMUX_AF('H', 12, AF2) 2048 2049 /* TIMER4_CH3 */ 2050 #define TIMER4_CH3_PA3 \ 2051 GD32_PINMUX_AF('A', 3, AF2) 2052 #define TIMER4_CH3_PI0 \ 2053 GD32_PINMUX_AF('I', 0, AF2) 2054 2055 /* TIMER7_BRKIN */ 2056 #define TIMER7_BRKIN_PA6 \ 2057 GD32_PINMUX_AF('A', 6, AF3) 2058 #define TIMER7_BRKIN_PI4 \ 2059 GD32_PINMUX_AF('I', 4, AF3) 2060 2061 /* TIMER7_CH0 */ 2062 #define TIMER7_CH0_PC6 \ 2063 GD32_PINMUX_AF('C', 6, AF3) 2064 #define TIMER7_CH0_PI5 \ 2065 GD32_PINMUX_AF('I', 5, AF3) 2066 2067 /* TIMER7_CH0_ON */ 2068 #define TIMER7_CH0_ON_PA5 \ 2069 GD32_PINMUX_AF('A', 5, AF3) 2070 #define TIMER7_CH0_ON_PA7 \ 2071 GD32_PINMUX_AF('A', 7, AF3) 2072 #define TIMER7_CH0_ON_PH13 \ 2073 GD32_PINMUX_AF('H', 13, AF3) 2074 2075 /* TIMER7_CH1 */ 2076 #define TIMER7_CH1_PC7 \ 2077 GD32_PINMUX_AF('C', 7, AF3) 2078 #define TIMER7_CH1_PI6 \ 2079 GD32_PINMUX_AF('I', 6, AF3) 2080 2081 /* TIMER7_CH1_ON */ 2082 #define TIMER7_CH1_ON_PB0 \ 2083 GD32_PINMUX_AF('B', 0, AF3) 2084 #define TIMER7_CH1_ON_PB14 \ 2085 GD32_PINMUX_AF('B', 14, AF3) 2086 #define TIMER7_CH1_ON_PH14 \ 2087 GD32_PINMUX_AF('H', 14, AF3) 2088 2089 /* TIMER7_CH2 */ 2090 #define TIMER7_CH2_PC8 \ 2091 GD32_PINMUX_AF('C', 8, AF3) 2092 #define TIMER7_CH2_PI7 \ 2093 GD32_PINMUX_AF('I', 7, AF3) 2094 2095 /* TIMER7_CH2_ON */ 2096 #define TIMER7_CH2_ON_PB1 \ 2097 GD32_PINMUX_AF('B', 1, AF3) 2098 #define TIMER7_CH2_ON_PB15 \ 2099 GD32_PINMUX_AF('B', 15, AF3) 2100 #define TIMER7_CH2_ON_PH15 \ 2101 GD32_PINMUX_AF('H', 15, AF3) 2102 2103 /* TIMER7_CH3 */ 2104 #define TIMER7_CH3_PC9 \ 2105 GD32_PINMUX_AF('C', 9, AF3) 2106 #define TIMER7_CH3_PI2 \ 2107 GD32_PINMUX_AF('I', 2, AF3) 2108 2109 /* TIMER7_ETI */ 2110 #define TIMER7_ETI_PA0 \ 2111 GD32_PINMUX_AF('A', 0, AF3) 2112 #define TIMER7_ETI_PI3 \ 2113 GD32_PINMUX_AF('I', 3, AF3) 2114 2115 /* TIMER8_CH0 */ 2116 #define TIMER8_CH0_PA2 \ 2117 GD32_PINMUX_AF('A', 2, AF3) 2118 #define TIMER8_CH0_PE5 \ 2119 GD32_PINMUX_AF('E', 5, AF3) 2120 2121 /* TIMER8_CH1 */ 2122 #define TIMER8_CH1_PA3 \ 2123 GD32_PINMUX_AF('A', 3, AF3) 2124 #define TIMER8_CH1_PE6 \ 2125 GD32_PINMUX_AF('E', 6, AF3) 2126 2127 /* TIMER9_CH0 */ 2128 #define TIMER9_CH0_PB8 \ 2129 GD32_PINMUX_AF('B', 8, AF3) 2130 #define TIMER9_CH0_PF6 \ 2131 GD32_PINMUX_AF('F', 6, AF3) 2132 2133 /* TLI_B0 */ 2134 #define TLI_B0_PE4 \ 2135 GD32_PINMUX_AF('E', 4, AF14) 2136 2137 /* TLI_B1 */ 2138 #define TLI_B1_PG12 \ 2139 GD32_PINMUX_AF('G', 12, AF14) 2140 2141 /* TLI_B2 */ 2142 #define TLI_B2_PD6 \ 2143 GD32_PINMUX_AF('D', 6, AF14) 2144 2145 /* TLI_B3 */ 2146 #define TLI_B3_PD10 \ 2147 GD32_PINMUX_AF('D', 10, AF14) 2148 #define TLI_B3_PG11 \ 2149 GD32_PINMUX_AF('G', 11, AF14) 2150 2151 /* TLI_B4 */ 2152 #define TLI_B4_PE12 \ 2153 GD32_PINMUX_AF('E', 12, AF14) 2154 #define TLI_B4_PG12 \ 2155 GD32_PINMUX_AF('G', 12, AF9) 2156 #define TLI_B4_PI4 \ 2157 GD32_PINMUX_AF('I', 4, AF14) 2158 2159 /* TLI_B5 */ 2160 #define TLI_B5_PA3 \ 2161 GD32_PINMUX_AF('A', 3, AF14) 2162 #define TLI_B5_PI5 \ 2163 GD32_PINMUX_AF('I', 5, AF14) 2164 2165 /* TLI_B6 */ 2166 #define TLI_B6_PB8 \ 2167 GD32_PINMUX_AF('B', 8, AF14) 2168 #define TLI_B6_PI6 \ 2169 GD32_PINMUX_AF('I', 6, AF14) 2170 2171 /* TLI_B7 */ 2172 #define TLI_B7_PB9 \ 2173 GD32_PINMUX_AF('B', 9, AF14) 2174 #define TLI_B7_PI7 \ 2175 GD32_PINMUX_AF('I', 7, AF14) 2176 2177 /* TLI_DE */ 2178 #define TLI_DE_PE13 \ 2179 GD32_PINMUX_AF('E', 13, AF14) 2180 #define TLI_DE_PF10 \ 2181 GD32_PINMUX_AF('F', 10, AF14) 2182 2183 /* TLI_G0 */ 2184 #define TLI_G0_PE5 \ 2185 GD32_PINMUX_AF('E', 5, AF14) 2186 2187 /* TLI_G1 */ 2188 #define TLI_G1_PE6 \ 2189 GD32_PINMUX_AF('E', 6, AF14) 2190 2191 /* TLI_G2 */ 2192 #define TLI_G2_PA6 \ 2193 GD32_PINMUX_AF('A', 6, AF14) 2194 #define TLI_G2_PH13 \ 2195 GD32_PINMUX_AF('H', 13, AF14) 2196 2197 /* TLI_G3 */ 2198 #define TLI_G3_PE11 \ 2199 GD32_PINMUX_AF('E', 11, AF14) 2200 #define TLI_G3_PG10 \ 2201 GD32_PINMUX_AF('G', 10, AF9) 2202 #define TLI_G3_PH14 \ 2203 GD32_PINMUX_AF('H', 14, AF14) 2204 2205 /* TLI_G4 */ 2206 #define TLI_G4_PB10 \ 2207 GD32_PINMUX_AF('B', 10, AF14) 2208 #define TLI_G4_PH15 \ 2209 GD32_PINMUX_AF('H', 15, AF14) 2210 2211 /* TLI_G5 */ 2212 #define TLI_G5_PB11 \ 2213 GD32_PINMUX_AF('B', 11, AF14) 2214 #define TLI_G5_PI0 \ 2215 GD32_PINMUX_AF('I', 0, AF14) 2216 2217 /* TLI_G6 */ 2218 #define TLI_G6_PC7 \ 2219 GD32_PINMUX_AF('C', 7, AF14) 2220 #define TLI_G6_PI1 \ 2221 GD32_PINMUX_AF('I', 1, AF14) 2222 2223 /* TLI_G7 */ 2224 #define TLI_G7_PD3 \ 2225 GD32_PINMUX_AF('D', 3, AF14) 2226 #define TLI_G7_PI2 \ 2227 GD32_PINMUX_AF('I', 2, AF14) 2228 2229 /* TLI_HSYNC */ 2230 #define TLI_HSYNC_PC6 \ 2231 GD32_PINMUX_AF('C', 6, AF14) 2232 #define TLI_HSYNC_PI10 \ 2233 GD32_PINMUX_AF('I', 10, AF14) 2234 2235 /* TLI_PIXCLK */ 2236 #define TLI_PIXCLK_PE14 \ 2237 GD32_PINMUX_AF('E', 14, AF14) 2238 #define TLI_PIXCLK_PG7 \ 2239 GD32_PINMUX_AF('G', 7, AF14) 2240 2241 /* TLI_R0 */ 2242 #define TLI_R0_PH2 \ 2243 GD32_PINMUX_AF('H', 2, AF14) 2244 2245 /* TLI_R1 */ 2246 #define TLI_R1_PH3 \ 2247 GD32_PINMUX_AF('H', 3, AF14) 2248 2249 /* TLI_R2 */ 2250 #define TLI_R2_PC10 \ 2251 GD32_PINMUX_AF('C', 10, AF14) 2252 #define TLI_R2_PH8 \ 2253 GD32_PINMUX_AF('H', 8, AF14) 2254 2255 /* TLI_R3 */ 2256 #define TLI_R3_PB0 \ 2257 GD32_PINMUX_AF('B', 0, AF9) 2258 #define TLI_R3_PH9 \ 2259 GD32_PINMUX_AF('H', 9, AF14) 2260 2261 /* TLI_R4 */ 2262 #define TLI_R4_PA11 \ 2263 GD32_PINMUX_AF('A', 11, AF14) 2264 #define TLI_R4_PH10 \ 2265 GD32_PINMUX_AF('H', 10, AF14) 2266 2267 /* TLI_R5 */ 2268 #define TLI_R5_PA12 \ 2269 GD32_PINMUX_AF('A', 12, AF14) 2270 #define TLI_R5_PH11 \ 2271 GD32_PINMUX_AF('H', 11, AF14) 2272 2273 /* TLI_R6 */ 2274 #define TLI_R6_PA8 \ 2275 GD32_PINMUX_AF('A', 8, AF14) 2276 #define TLI_R6_PB1 \ 2277 GD32_PINMUX_AF('B', 1, AF9) 2278 #define TLI_R6_PH12 \ 2279 GD32_PINMUX_AF('H', 12, AF14) 2280 2281 /* TLI_R7 */ 2282 #define TLI_R7_PE15 \ 2283 GD32_PINMUX_AF('E', 15, AF14) 2284 #define TLI_R7_PG6 \ 2285 GD32_PINMUX_AF('G', 6, AF14) 2286 2287 /* TLI_VSYNC */ 2288 #define TLI_VSYNC_PA4 \ 2289 GD32_PINMUX_AF('A', 4, AF14) 2290 #define TLI_VSYNC_PI9 \ 2291 GD32_PINMUX_AF('I', 9, AF14) 2292 2293 /* TRACECLK */ 2294 #define TRACECLK_PE2 \ 2295 GD32_PINMUX_AF('E', 2, AF0) 2296 2297 /* TRACED0 */ 2298 #define TRACED0_PC8 \ 2299 GD32_PINMUX_AF('C', 8, AF0) 2300 #define TRACED0_PE3 \ 2301 GD32_PINMUX_AF('E', 3, AF0) 2302 2303 /* TRACED1 */ 2304 #define TRACED1_PD3 \ 2305 GD32_PINMUX_AF('D', 3, AF0) 2306 #define TRACED1_PE4 \ 2307 GD32_PINMUX_AF('E', 4, AF0) 2308 2309 /* TRACED2 */ 2310 #define TRACED2_PE5 \ 2311 GD32_PINMUX_AF('E', 5, AF0) 2312 #define TRACED2_PG13 \ 2313 GD32_PINMUX_AF('G', 13, AF0) 2314 2315 /* TRACED3 */ 2316 #define TRACED3_PE6 \ 2317 GD32_PINMUX_AF('E', 6, AF0) 2318 #define TRACED3_PG14 \ 2319 GD32_PINMUX_AF('G', 14, AF0) 2320 2321 /* TRACESWO */ 2322 #define TRACESWO_PB3 \ 2323 GD32_PINMUX_AF('B', 3, AF0) 2324 2325 /* UART3_RX */ 2326 #define UART3_RX_PA1 \ 2327 GD32_PINMUX_AF('A', 1, AF8) 2328 #define UART3_RX_PC11 \ 2329 GD32_PINMUX_AF('C', 11, AF8) 2330 2331 /* UART3_TX */ 2332 #define UART3_TX_PA0 \ 2333 GD32_PINMUX_AF('A', 0, AF8) 2334 #define UART3_TX_PC10 \ 2335 GD32_PINMUX_AF('C', 10, AF8) 2336 2337 /* UART4_RX */ 2338 #define UART4_RX_PC12 \ 2339 GD32_PINMUX_AF('C', 12, AF8) 2340 #define UART4_RX_PD2 \ 2341 GD32_PINMUX_AF('D', 2, AF8) 2342 2343 /* UART6_RX */ 2344 #define UART6_RX_PE7 \ 2345 GD32_PINMUX_AF('E', 7, AF8) 2346 #define UART6_RX_PF6 \ 2347 GD32_PINMUX_AF('F', 6, AF8) 2348 2349 /* UART6_TX */ 2350 #define UART6_TX_PE8 \ 2351 GD32_PINMUX_AF('E', 8, AF8) 2352 #define UART6_TX_PF7 \ 2353 GD32_PINMUX_AF('F', 7, AF8) 2354 2355 /* UART7_RX */ 2356 #define UART7_RX_PE0 \ 2357 GD32_PINMUX_AF('E', 0, AF8) 2358 2359 /* UART7_TX */ 2360 #define UART7_TX_PE1 \ 2361 GD32_PINMUX_AF('E', 1, AF8) 2362 2363 /* USART0_CK */ 2364 #define USART0_CK_PA8 \ 2365 GD32_PINMUX_AF('A', 8, AF7) 2366 2367 /* USART0_CTS */ 2368 #define USART0_CTS_PA11 \ 2369 GD32_PINMUX_AF('A', 11, AF7) 2370 2371 /* USART0_RTS */ 2372 #define USART0_RTS_PA12 \ 2373 GD32_PINMUX_AF('A', 12, AF7) 2374 2375 /* USART0_RX */ 2376 #define USART0_RX_PA10 \ 2377 GD32_PINMUX_AF('A', 10, AF7) 2378 #define USART0_RX_PB3 \ 2379 GD32_PINMUX_AF('B', 3, AF7) 2380 #define USART0_RX_PB7 \ 2381 GD32_PINMUX_AF('B', 7, AF7) 2382 2383 /* USART0_TX */ 2384 #define USART0_TX_PA9 \ 2385 GD32_PINMUX_AF('A', 9, AF7) 2386 #define USART0_TX_PA15 \ 2387 GD32_PINMUX_AF('A', 15, AF7) 2388 #define USART0_TX_PB6 \ 2389 GD32_PINMUX_AF('B', 6, AF7) 2390 2391 /* USART1_CK */ 2392 #define USART1_CK_PA4 \ 2393 GD32_PINMUX_AF('A', 4, AF7) 2394 #define USART1_CK_PD7 \ 2395 GD32_PINMUX_AF('D', 7, AF7) 2396 2397 /* USART1_CTS */ 2398 #define USART1_CTS_PA0 \ 2399 GD32_PINMUX_AF('A', 0, AF7) 2400 #define USART1_CTS_PD3 \ 2401 GD32_PINMUX_AF('D', 3, AF7) 2402 2403 /* USART1_RTS */ 2404 #define USART1_RTS_PA1 \ 2405 GD32_PINMUX_AF('A', 1, AF7) 2406 #define USART1_RTS_PD4 \ 2407 GD32_PINMUX_AF('D', 4, AF7) 2408 2409 /* USART1_RX */ 2410 #define USART1_RX_PA3 \ 2411 GD32_PINMUX_AF('A', 3, AF7) 2412 #define USART1_RX_PD6 \ 2413 GD32_PINMUX_AF('D', 6, AF7) 2414 2415 /* USART1_TX */ 2416 #define USART1_TX_PA2 \ 2417 GD32_PINMUX_AF('A', 2, AF7) 2418 #define USART1_TX_PD5 \ 2419 GD32_PINMUX_AF('D', 5, AF7) 2420 2421 /* USART2_CK */ 2422 #define USART2_CK_PB12 \ 2423 GD32_PINMUX_AF('B', 12, AF7) 2424 #define USART2_CK_PC12 \ 2425 GD32_PINMUX_AF('C', 12, AF7) 2426 #define USART2_CK_PD10 \ 2427 GD32_PINMUX_AF('D', 10, AF7) 2428 2429 /* USART2_CTS */ 2430 #define USART2_CTS_PB13 \ 2431 GD32_PINMUX_AF('B', 13, AF7) 2432 #define USART2_CTS_PD11 \ 2433 GD32_PINMUX_AF('D', 11, AF7) 2434 2435 /* USART2_RTS */ 2436 #define USART2_RTS_PB14 \ 2437 GD32_PINMUX_AF('B', 14, AF7) 2438 #define USART2_RTS_PD12 \ 2439 GD32_PINMUX_AF('D', 12, AF7) 2440 2441 /* USART2_RX */ 2442 #define USART2_RX_PB11 \ 2443 GD32_PINMUX_AF('B', 11, AF7) 2444 #define USART2_RX_PC5 \ 2445 GD32_PINMUX_AF('C', 5, AF7) 2446 #define USART2_RX_PC11 \ 2447 GD32_PINMUX_AF('C', 11, AF7) 2448 #define USART2_RX_PD9 \ 2449 GD32_PINMUX_AF('D', 9, AF7) 2450 2451 /* USART2_TX */ 2452 #define USART2_TX_PB10 \ 2453 GD32_PINMUX_AF('B', 10, AF7) 2454 #define USART2_TX_PC10 \ 2455 GD32_PINMUX_AF('C', 10, AF7) 2456 #define USART2_TX_PD8 \ 2457 GD32_PINMUX_AF('D', 8, AF7) 2458 2459 /* USART5_CK */ 2460 #define USART5_CK_PC8 \ 2461 GD32_PINMUX_AF('C', 8, AF8) 2462 #define USART5_CK_PG7 \ 2463 GD32_PINMUX_AF('G', 7, AF8) 2464 2465 /* USART5_CTS */ 2466 #define USART5_CTS_PG13 \ 2467 GD32_PINMUX_AF('G', 13, AF8) 2468 #define USART5_CTS_PG15 \ 2469 GD32_PINMUX_AF('G', 15, AF8) 2470 2471 /* USART5_RTS */ 2472 #define USART5_RTS_PG8 \ 2473 GD32_PINMUX_AF('G', 8, AF8) 2474 #define USART5_RTS_PG12 \ 2475 GD32_PINMUX_AF('G', 12, AF8) 2476 2477 /* USART5_RX */ 2478 #define USART5_RX_PA12 \ 2479 GD32_PINMUX_AF('A', 12, AF8) 2480 #define USART5_RX_PC7 \ 2481 GD32_PINMUX_AF('C', 7, AF8) 2482 #define USART5_RX_PG9 \ 2483 GD32_PINMUX_AF('G', 9, AF8) 2484 2485 /* USART5_TX */ 2486 #define USART5_TX_PA11 \ 2487 GD32_PINMUX_AF('A', 11, AF8) 2488 #define USART5_TX_PC6 \ 2489 GD32_PINMUX_AF('C', 6, AF8) 2490 #define USART5_TX_PG14 \ 2491 GD32_PINMUX_AF('G', 14, AF8) 2492 2493 /* USBFS_DM */ 2494 #define USBFS_DM_PA11 \ 2495 GD32_PINMUX_AF('A', 11, AF10) 2496 2497 /* USBFS_DP */ 2498 #define USBFS_DP_PA12 \ 2499 GD32_PINMUX_AF('A', 12, AF10) 2500 2501 /* USBFS_ID */ 2502 #define USBFS_ID_PA10 \ 2503 GD32_PINMUX_AF('A', 10, AF10) 2504 2505 /* USBFS_SOF */ 2506 #define USBFS_SOF_PA8 \ 2507 GD32_PINMUX_AF('A', 8, AF10) 2508 2509 /* USBHS_DM */ 2510 #define USBHS_DM_PB14 \ 2511 GD32_PINMUX_AF('B', 14, AF12) 2512 2513 /* USBHS_DP */ 2514 #define USBHS_DP_PB15 \ 2515 GD32_PINMUX_AF('B', 15, AF12) 2516 2517 /* USBHS_ID */ 2518 #define USBHS_ID_PB12 \ 2519 GD32_PINMUX_AF('B', 12, AF12) 2520 2521 /* USBHS_SOF */ 2522 #define USBHS_SOF_PA4 \ 2523 GD32_PINMUX_AF('A', 4, AF12) 2524 2525 /* USBHS_ULPI_CK */ 2526 #define USBHS_ULPI_CK_PA5 \ 2527 GD32_PINMUX_AF('A', 5, AF10) 2528 2529 /* USBHS_ULPI_D0 */ 2530 #define USBHS_ULPI_D0_PA3 \ 2531 GD32_PINMUX_AF('A', 3, AF10) 2532 2533 /* USBHS_ULPI_D1 */ 2534 #define USBHS_ULPI_D1_PB0 \ 2535 GD32_PINMUX_AF('B', 0, AF10) 2536 2537 /* USBHS_ULPI_D2 */ 2538 #define USBHS_ULPI_D2_PB1 \ 2539 GD32_PINMUX_AF('B', 1, AF10) 2540 2541 /* USBHS_ULPI_D3 */ 2542 #define USBHS_ULPI_D3_PB10 \ 2543 GD32_PINMUX_AF('B', 10, AF10) 2544 2545 /* USBHS_ULPI_D4 */ 2546 #define USBHS_ULPI_D4_PB2 \ 2547 GD32_PINMUX_AF('B', 2, AF10) 2548 #define USBHS_ULPI_D4_PB11 \ 2549 GD32_PINMUX_AF('B', 11, AF10) 2550 2551 /* USBHS_ULPI_D5 */ 2552 #define USBHS_ULPI_D5_PB12 \ 2553 GD32_PINMUX_AF('B', 12, AF10) 2554 2555 /* USBHS_ULPI_D6 */ 2556 #define USBHS_ULPI_D6_PB13 \ 2557 GD32_PINMUX_AF('B', 13, AF10) 2558 2559 /* USBHS_ULPI_D7 */ 2560 #define USBHS_ULPI_D7_PB5 \ 2561 GD32_PINMUX_AF('B', 5, AF10) 2562 2563 /* USBHS_ULPI_DIR */ 2564 #define USBHS_ULPI_DIR_PC2 \ 2565 GD32_PINMUX_AF('C', 2, AF10) 2566 #define USBHS_ULPI_DIR_PI11 \ 2567 GD32_PINMUX_AF('I', 11, AF10) 2568 2569 /* USBHS_ULPI_NXT */ 2570 #define USBHS_ULPI_NXT_PC3 \ 2571 GD32_PINMUX_AF('C', 3, AF10) 2572 #define USBHS_ULPI_NXT_PH4 \ 2573 GD32_PINMUX_AF('H', 4, AF10) 2574 2575 /* USBHS_ULPI_STP */ 2576 #define USBHS_ULPI_STP_PC0 \ 2577 GD32_PINMUX_AF('C', 0, AF10) 2578
