1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32-af.h" 8 9 /* ADC012_IN0 */ 10 #define ADC012_IN0_PA0 \ 11 GD32_PINMUX_AF('A', 0, ANALOG) 12 13 /* ADC012_IN1 */ 14 #define ADC012_IN1_PA1 \ 15 GD32_PINMUX_AF('A', 1, ANALOG) 16 17 /* ADC012_IN10 */ 18 #define ADC012_IN10_PC0 \ 19 GD32_PINMUX_AF('C', 0, ANALOG) 20 21 /* ADC012_IN11 */ 22 #define ADC012_IN11_PC1 \ 23 GD32_PINMUX_AF('C', 1, ANALOG) 24 25 /* ADC012_IN12 */ 26 #define ADC012_IN12_PC2 \ 27 GD32_PINMUX_AF('C', 2, ANALOG) 28 29 /* ADC012_IN13 */ 30 #define ADC012_IN13_PC3 \ 31 GD32_PINMUX_AF('C', 3, ANALOG) 32 33 /* ADC012_IN2 */ 34 #define ADC012_IN2_PA2 \ 35 GD32_PINMUX_AF('A', 2, ANALOG) 36 37 /* ADC012_IN3 */ 38 #define ADC012_IN3_PA3 \ 39 GD32_PINMUX_AF('A', 3, ANALOG) 40 41 /* ADC01_IN14 */ 42 #define ADC01_IN14_PC4 \ 43 GD32_PINMUX_AF('C', 4, ANALOG) 44 45 /* ADC01_IN15 */ 46 #define ADC01_IN15_PC5 \ 47 GD32_PINMUX_AF('C', 5, ANALOG) 48 49 /* ADC01_IN4 */ 50 #define ADC01_IN4_PA4 \ 51 GD32_PINMUX_AF('A', 4, ANALOG) 52 53 /* ADC01_IN5 */ 54 #define ADC01_IN5_PA5 \ 55 GD32_PINMUX_AF('A', 5, ANALOG) 56 57 /* ADC01_IN6 */ 58 #define ADC01_IN6_PA6 \ 59 GD32_PINMUX_AF('A', 6, ANALOG) 60 61 /* ADC01_IN7 */ 62 #define ADC01_IN7_PA7 \ 63 GD32_PINMUX_AF('A', 7, ANALOG) 64 65 /* ADC01_IN8 */ 66 #define ADC01_IN8_PB0 \ 67 GD32_PINMUX_AF('B', 0, ANALOG) 68 69 /* ADC01_IN9 */ 70 #define ADC01_IN9_PB1 \ 71 GD32_PINMUX_AF('B', 1, ANALOG) 72 73 /* ADC2_IN14 */ 74 #define ADC2_IN14_PF4 \ 75 GD32_PINMUX_AF('F', 4, ANALOG) 76 77 /* ADC2_IN15 */ 78 #define ADC2_IN15_PF5 \ 79 GD32_PINMUX_AF('F', 5, ANALOG) 80 81 /* ADC2_IN4 */ 82 #define ADC2_IN4_PF6 \ 83 GD32_PINMUX_AF('F', 6, ANALOG) 84 85 /* ADC2_IN5 */ 86 #define ADC2_IN5_PF7 \ 87 GD32_PINMUX_AF('F', 7, ANALOG) 88 89 /* ADC2_IN6 */ 90 #define ADC2_IN6_PF8 \ 91 GD32_PINMUX_AF('F', 8, ANALOG) 92 93 /* ADC2_IN7 */ 94 #define ADC2_IN7_PF9 \ 95 GD32_PINMUX_AF('F', 9, ANALOG) 96 97 /* ADC2_IN8 */ 98 #define ADC2_IN8_PF10 \ 99 GD32_PINMUX_AF('F', 10, ANALOG) 100 101 /* ADC2_IN9 */ 102 #define ADC2_IN9_PF3 \ 103 GD32_PINMUX_AF('F', 3, ANALOG) 104 105 /* ANALOG */ 106 #define ANALOG_PA0 \ 107 GD32_PINMUX_AF('A', 0, ANALOG) 108 #define ANALOG_PA1 \ 109 GD32_PINMUX_AF('A', 1, ANALOG) 110 #define ANALOG_PA2 \ 111 GD32_PINMUX_AF('A', 2, ANALOG) 112 #define ANALOG_PA3 \ 113 GD32_PINMUX_AF('A', 3, ANALOG) 114 #define ANALOG_PA4 \ 115 GD32_PINMUX_AF('A', 4, ANALOG) 116 #define ANALOG_PA5 \ 117 GD32_PINMUX_AF('A', 5, ANALOG) 118 #define ANALOG_PA6 \ 119 GD32_PINMUX_AF('A', 6, ANALOG) 120 #define ANALOG_PA7 \ 121 GD32_PINMUX_AF('A', 7, ANALOG) 122 #define ANALOG_PA8 \ 123 GD32_PINMUX_AF('A', 8, ANALOG) 124 #define ANALOG_PA9 \ 125 GD32_PINMUX_AF('A', 9, ANALOG) 126 #define ANALOG_PA10 \ 127 GD32_PINMUX_AF('A', 10, ANALOG) 128 #define ANALOG_PA11 \ 129 GD32_PINMUX_AF('A', 11, ANALOG) 130 #define ANALOG_PA12 \ 131 GD32_PINMUX_AF('A', 12, ANALOG) 132 #define ANALOG_PA13 \ 133 GD32_PINMUX_AF('A', 13, ANALOG) 134 #define ANALOG_PA14 \ 135 GD32_PINMUX_AF('A', 14, ANALOG) 136 #define ANALOG_PA15 \ 137 GD32_PINMUX_AF('A', 15, ANALOG) 138 #define ANALOG_PB0 \ 139 GD32_PINMUX_AF('B', 0, ANALOG) 140 #define ANALOG_PB1 \ 141 GD32_PINMUX_AF('B', 1, ANALOG) 142 #define ANALOG_PB2 \ 143 GD32_PINMUX_AF('B', 2, ANALOG) 144 #define ANALOG_PB3 \ 145 GD32_PINMUX_AF('B', 3, ANALOG) 146 #define ANALOG_PB4 \ 147 GD32_PINMUX_AF('B', 4, ANALOG) 148 #define ANALOG_PB5 \ 149 GD32_PINMUX_AF('B', 5, ANALOG) 150 #define ANALOG_PB6 \ 151 GD32_PINMUX_AF('B', 6, ANALOG) 152 #define ANALOG_PB7 \ 153 GD32_PINMUX_AF('B', 7, ANALOG) 154 #define ANALOG_PB8 \ 155 GD32_PINMUX_AF('B', 8, ANALOG) 156 #define ANALOG_PB9 \ 157 GD32_PINMUX_AF('B', 9, ANALOG) 158 #define ANALOG_PB10 \ 159 GD32_PINMUX_AF('B', 10, ANALOG) 160 #define ANALOG_PB11 \ 161 GD32_PINMUX_AF('B', 11, ANALOG) 162 #define ANALOG_PB12 \ 163 GD32_PINMUX_AF('B', 12, ANALOG) 164 #define ANALOG_PB13 \ 165 GD32_PINMUX_AF('B', 13, ANALOG) 166 #define ANALOG_PB14 \ 167 GD32_PINMUX_AF('B', 14, ANALOG) 168 #define ANALOG_PB15 \ 169 GD32_PINMUX_AF('B', 15, ANALOG) 170 #define ANALOG_PC0 \ 171 GD32_PINMUX_AF('C', 0, ANALOG) 172 #define ANALOG_PC1 \ 173 GD32_PINMUX_AF('C', 1, ANALOG) 174 #define ANALOG_PC2 \ 175 GD32_PINMUX_AF('C', 2, ANALOG) 176 #define ANALOG_PC3 \ 177 GD32_PINMUX_AF('C', 3, ANALOG) 178 #define ANALOG_PC4 \ 179 GD32_PINMUX_AF('C', 4, ANALOG) 180 #define ANALOG_PC5 \ 181 GD32_PINMUX_AF('C', 5, ANALOG) 182 #define ANALOG_PC6 \ 183 GD32_PINMUX_AF('C', 6, ANALOG) 184 #define ANALOG_PC7 \ 185 GD32_PINMUX_AF('C', 7, ANALOG) 186 #define ANALOG_PC8 \ 187 GD32_PINMUX_AF('C', 8, ANALOG) 188 #define ANALOG_PC9 \ 189 GD32_PINMUX_AF('C', 9, ANALOG) 190 #define ANALOG_PC10 \ 191 GD32_PINMUX_AF('C', 10, ANALOG) 192 #define ANALOG_PC11 \ 193 GD32_PINMUX_AF('C', 11, ANALOG) 194 #define ANALOG_PC12 \ 195 GD32_PINMUX_AF('C', 12, ANALOG) 196 #define ANALOG_PC13 \ 197 GD32_PINMUX_AF('C', 13, ANALOG) 198 #define ANALOG_PC14 \ 199 GD32_PINMUX_AF('C', 14, ANALOG) 200 #define ANALOG_PC15 \ 201 GD32_PINMUX_AF('C', 15, ANALOG) 202 #define ANALOG_PD0 \ 203 GD32_PINMUX_AF('D', 0, ANALOG) 204 #define ANALOG_PD1 \ 205 GD32_PINMUX_AF('D', 1, ANALOG) 206 #define ANALOG_PD2 \ 207 GD32_PINMUX_AF('D', 2, ANALOG) 208 #define ANALOG_PD3 \ 209 GD32_PINMUX_AF('D', 3, ANALOG) 210 #define ANALOG_PD4 \ 211 GD32_PINMUX_AF('D', 4, ANALOG) 212 #define ANALOG_PD5 \ 213 GD32_PINMUX_AF('D', 5, ANALOG) 214 #define ANALOG_PD6 \ 215 GD32_PINMUX_AF('D', 6, ANALOG) 216 #define ANALOG_PD7 \ 217 GD32_PINMUX_AF('D', 7, ANALOG) 218 #define ANALOG_PD8 \ 219 GD32_PINMUX_AF('D', 8, ANALOG) 220 #define ANALOG_PD9 \ 221 GD32_PINMUX_AF('D', 9, ANALOG) 222 #define ANALOG_PD10 \ 223 GD32_PINMUX_AF('D', 10, ANALOG) 224 #define ANALOG_PD11 \ 225 GD32_PINMUX_AF('D', 11, ANALOG) 226 #define ANALOG_PD12 \ 227 GD32_PINMUX_AF('D', 12, ANALOG) 228 #define ANALOG_PD13 \ 229 GD32_PINMUX_AF('D', 13, ANALOG) 230 #define ANALOG_PD14 \ 231 GD32_PINMUX_AF('D', 14, ANALOG) 232 #define ANALOG_PD15 \ 233 GD32_PINMUX_AF('D', 15, ANALOG) 234 #define ANALOG_PE0 \ 235 GD32_PINMUX_AF('E', 0, ANALOG) 236 #define ANALOG_PE1 \ 237 GD32_PINMUX_AF('E', 1, ANALOG) 238 #define ANALOG_PE2 \ 239 GD32_PINMUX_AF('E', 2, ANALOG) 240 #define ANALOG_PE3 \ 241 GD32_PINMUX_AF('E', 3, ANALOG) 242 #define ANALOG_PE4 \ 243 GD32_PINMUX_AF('E', 4, ANALOG) 244 #define ANALOG_PE5 \ 245 GD32_PINMUX_AF('E', 5, ANALOG) 246 #define ANALOG_PE6 \ 247 GD32_PINMUX_AF('E', 6, ANALOG) 248 #define ANALOG_PE7 \ 249 GD32_PINMUX_AF('E', 7, ANALOG) 250 #define ANALOG_PE8 \ 251 GD32_PINMUX_AF('E', 8, ANALOG) 252 #define ANALOG_PE9 \ 253 GD32_PINMUX_AF('E', 9, ANALOG) 254 #define ANALOG_PE10 \ 255 GD32_PINMUX_AF('E', 10, ANALOG) 256 #define ANALOG_PE11 \ 257 GD32_PINMUX_AF('E', 11, ANALOG) 258 #define ANALOG_PE12 \ 259 GD32_PINMUX_AF('E', 12, ANALOG) 260 #define ANALOG_PE13 \ 261 GD32_PINMUX_AF('E', 13, ANALOG) 262 #define ANALOG_PE14 \ 263 GD32_PINMUX_AF('E', 14, ANALOG) 264 #define ANALOG_PE15 \ 265 GD32_PINMUX_AF('E', 15, ANALOG) 266 #define ANALOG_PF0 \ 267 GD32_PINMUX_AF('F', 0, ANALOG) 268 #define ANALOG_PF1 \ 269 GD32_PINMUX_AF('F', 1, ANALOG) 270 #define ANALOG_PF2 \ 271 GD32_PINMUX_AF('F', 2, ANALOG) 272 #define ANALOG_PF3 \ 273 GD32_PINMUX_AF('F', 3, ANALOG) 274 #define ANALOG_PF4 \ 275 GD32_PINMUX_AF('F', 4, ANALOG) 276 #define ANALOG_PF5 \ 277 GD32_PINMUX_AF('F', 5, ANALOG) 278 #define ANALOG_PF6 \ 279 GD32_PINMUX_AF('F', 6, ANALOG) 280 #define ANALOG_PF7 \ 281 GD32_PINMUX_AF('F', 7, ANALOG) 282 #define ANALOG_PF8 \ 283 GD32_PINMUX_AF('F', 8, ANALOG) 284 #define ANALOG_PF9 \ 285 GD32_PINMUX_AF('F', 9, ANALOG) 286 #define ANALOG_PF10 \ 287 GD32_PINMUX_AF('F', 10, ANALOG) 288 #define ANALOG_PF11 \ 289 GD32_PINMUX_AF('F', 11, ANALOG) 290 #define ANALOG_PF12 \ 291 GD32_PINMUX_AF('F', 12, ANALOG) 292 #define ANALOG_PF13 \ 293 GD32_PINMUX_AF('F', 13, ANALOG) 294 #define ANALOG_PF14 \ 295 GD32_PINMUX_AF('F', 14, ANALOG) 296 #define ANALOG_PF15 \ 297 GD32_PINMUX_AF('F', 15, ANALOG) 298 #define ANALOG_PG0 \ 299 GD32_PINMUX_AF('G', 0, ANALOG) 300 #define ANALOG_PG1 \ 301 GD32_PINMUX_AF('G', 1, ANALOG) 302 #define ANALOG_PG2 \ 303 GD32_PINMUX_AF('G', 2, ANALOG) 304 #define ANALOG_PG3 \ 305 GD32_PINMUX_AF('G', 3, ANALOG) 306 #define ANALOG_PG4 \ 307 GD32_PINMUX_AF('G', 4, ANALOG) 308 #define ANALOG_PG5 \ 309 GD32_PINMUX_AF('G', 5, ANALOG) 310 #define ANALOG_PG6 \ 311 GD32_PINMUX_AF('G', 6, ANALOG) 312 #define ANALOG_PG7 \ 313 GD32_PINMUX_AF('G', 7, ANALOG) 314 #define ANALOG_PG8 \ 315 GD32_PINMUX_AF('G', 8, ANALOG) 316 #define ANALOG_PG9 \ 317 GD32_PINMUX_AF('G', 9, ANALOG) 318 #define ANALOG_PG10 \ 319 GD32_PINMUX_AF('G', 10, ANALOG) 320 #define ANALOG_PG11 \ 321 GD32_PINMUX_AF('G', 11, ANALOG) 322 #define ANALOG_PG12 \ 323 GD32_PINMUX_AF('G', 12, ANALOG) 324 #define ANALOG_PG13 \ 325 GD32_PINMUX_AF('G', 13, ANALOG) 326 #define ANALOG_PG14 \ 327 GD32_PINMUX_AF('G', 14, ANALOG) 328 #define ANALOG_PG15 \ 329 GD32_PINMUX_AF('G', 15, ANALOG) 330 331 /* CAN0_RX */ 332 #define CAN0_RX_PA11 \ 333 GD32_PINMUX_AF('A', 11, AF9) 334 #define CAN0_RX_PB8 \ 335 GD32_PINMUX_AF('B', 8, AF9) 336 #define CAN0_RX_PD0 \ 337 GD32_PINMUX_AF('D', 0, AF9) 338 339 /* CAN0_TX */ 340 #define CAN0_TX_PA12 \ 341 GD32_PINMUX_AF('A', 12, AF9) 342 #define CAN0_TX_PB9 \ 343 GD32_PINMUX_AF('B', 9, AF9) 344 #define CAN0_TX_PD1 \ 345 GD32_PINMUX_AF('D', 1, AF9) 346 347 /* CAN1_RX */ 348 #define CAN1_RX_PB5 \ 349 GD32_PINMUX_AF('B', 5, AF9) 350 #define CAN1_RX_PB12 \ 351 GD32_PINMUX_AF('B', 12, AF9) 352 353 /* CAN1_TX */ 354 #define CAN1_TX_PB6 \ 355 GD32_PINMUX_AF('B', 6, AF9) 356 #define CAN1_TX_PB13 \ 357 GD32_PINMUX_AF('B', 13, AF9) 358 359 /* CK_OUT0 */ 360 #define CK_OUT0_PA8 \ 361 GD32_PINMUX_AF('A', 8, AF0) 362 363 /* CK_OUT1 */ 364 #define CK_OUT1_PC9 \ 365 GD32_PINMUX_AF('C', 9, AF0) 366 367 /* CTC_SYNC */ 368 #define CTC_SYNC_PA8 \ 369 GD32_PINMUX_AF('A', 8, AF9) 370 #define CTC_SYNC_PD15 \ 371 GD32_PINMUX_AF('D', 15, AF0) 372 #define CTC_SYNC_PF0 \ 373 GD32_PINMUX_AF('F', 0, AF0) 374 375 /* DAC_OUT0 */ 376 #define DAC_OUT0_PA4 \ 377 GD32_PINMUX_AF('A', 4, ANALOG) 378 379 /* DAC_OUT1 */ 380 #define DAC_OUT1_PA5 \ 381 GD32_PINMUX_AF('A', 5, ANALOG) 382 383 /* DCI_D0 */ 384 #define DCI_D0_PA9 \ 385 GD32_PINMUX_AF('A', 9, AF13) 386 #define DCI_D0_PC6 \ 387 GD32_PINMUX_AF('C', 6, AF13) 388 389 /* DCI_D1 */ 390 #define DCI_D1_PA10 \ 391 GD32_PINMUX_AF('A', 10, AF13) 392 #define DCI_D1_PC7 \ 393 GD32_PINMUX_AF('C', 7, AF13) 394 395 /* DCI_D10 */ 396 #define DCI_D10_PB5 \ 397 GD32_PINMUX_AF('B', 5, AF13) 398 #define DCI_D10_PD6 \ 399 GD32_PINMUX_AF('D', 6, AF13) 400 401 /* DCI_D11 */ 402 #define DCI_D11_PD2 \ 403 GD32_PINMUX_AF('D', 2, AF13) 404 #define DCI_D11_PF10 \ 405 GD32_PINMUX_AF('F', 10, AF13) 406 407 /* DCI_D12 */ 408 #define DCI_D12_PF11 \ 409 GD32_PINMUX_AF('F', 11, AF13) 410 #define DCI_D12_PG6 \ 411 GD32_PINMUX_AF('G', 6, AF13) 412 413 /* DCI_D13 */ 414 #define DCI_D13_PG7 \ 415 GD32_PINMUX_AF('G', 7, AF13) 416 #define DCI_D13_PG15 \ 417 GD32_PINMUX_AF('G', 15, AF13) 418 419 /* DCI_D2 */ 420 #define DCI_D2_PC8 \ 421 GD32_PINMUX_AF('C', 8, AF13) 422 #define DCI_D2_PE0 \ 423 GD32_PINMUX_AF('E', 0, AF13) 424 #define DCI_D2_PG10 \ 425 GD32_PINMUX_AF('G', 10, AF13) 426 427 /* DCI_D3 */ 428 #define DCI_D3_PC9 \ 429 GD32_PINMUX_AF('C', 9, AF13) 430 #define DCI_D3_PE1 \ 431 GD32_PINMUX_AF('E', 1, AF13) 432 #define DCI_D3_PG11 \ 433 GD32_PINMUX_AF('G', 11, AF13) 434 435 /* DCI_D4 */ 436 #define DCI_D4_PC11 \ 437 GD32_PINMUX_AF('C', 11, AF13) 438 #define DCI_D4_PE4 \ 439 GD32_PINMUX_AF('E', 4, AF13) 440 441 /* DCI_D5 */ 442 #define DCI_D5_PB6 \ 443 GD32_PINMUX_AF('B', 6, AF13) 444 #define DCI_D5_PD3 \ 445 GD32_PINMUX_AF('D', 3, AF13) 446 447 /* DCI_D6 */ 448 #define DCI_D6_PB8 \ 449 GD32_PINMUX_AF('B', 8, AF13) 450 #define DCI_D6_PE5 \ 451 GD32_PINMUX_AF('E', 5, AF13) 452 453 /* DCI_D7 */ 454 #define DCI_D7_PB9 \ 455 GD32_PINMUX_AF('B', 9, AF13) 456 #define DCI_D7_PE6 \ 457 GD32_PINMUX_AF('E', 6, AF13) 458 459 /* DCI_D8 */ 460 #define DCI_D8_PC10 \ 461 GD32_PINMUX_AF('C', 10, AF13) 462 463 /* DCI_D9 */ 464 #define DCI_D9_PC12 \ 465 GD32_PINMUX_AF('C', 12, AF13) 466 467 /* DCI_HSYNC */ 468 #define DCI_HSYNC_PA4 \ 469 GD32_PINMUX_AF('A', 4, AF13) 470 471 /* DCI_PIXCLK */ 472 #define DCI_PIXCLK_PA6 \ 473 GD32_PINMUX_AF('A', 6, AF13) 474 475 /* DCI_VSYNC */ 476 #define DCI_VSYNC_PB7 \ 477 GD32_PINMUX_AF('B', 7, AF13) 478 #define DCI_VSYNC_PG9 \ 479 GD32_PINMUX_AF('G', 9, AF13) 480 481 /* ENET_MDC */ 482 #define ENET_MDC_PC1 \ 483 GD32_PINMUX_AF('C', 1, AF11) 484 485 /* ENET_MDIO */ 486 #define ENET_MDIO_PA2 \ 487 GD32_PINMUX_AF('A', 2, AF11) 488 489 /* ENET_MII_COL */ 490 #define ENET_MII_COL_PA3 \ 491 GD32_PINMUX_AF('A', 3, AF11) 492 493 /* ENET_MII_CRS */ 494 #define ENET_MII_CRS_PA0 \ 495 GD32_PINMUX_AF('A', 0, AF11) 496 497 /* ENET_MII_RXD0 */ 498 #define ENET_MII_RXD0_PC4 \ 499 GD32_PINMUX_AF('C', 4, AF11) 500 501 /* ENET_MII_RXD1 */ 502 #define ENET_MII_RXD1_PC5 \ 503 GD32_PINMUX_AF('C', 5, AF11) 504 505 /* ENET_MII_RXD2 */ 506 #define ENET_MII_RXD2_PB0 \ 507 GD32_PINMUX_AF('B', 0, AF11) 508 509 /* ENET_MII_RXD3 */ 510 #define ENET_MII_RXD3_PB1 \ 511 GD32_PINMUX_AF('B', 1, AF11) 512 513 /* ENET_MII_RX_CLK */ 514 #define ENET_MII_RX_CLK_PA1 \ 515 GD32_PINMUX_AF('A', 1, AF11) 516 517 /* ENET_MII_RX_DV */ 518 #define ENET_MII_RX_DV_PA7 \ 519 GD32_PINMUX_AF('A', 7, AF11) 520 521 /* ENET_MII_RX_ER */ 522 #define ENET_MII_RX_ER_PB9 \ 523 GD32_PINMUX_AF('B', 9, AF1) 524 525 /* ENET_MII_TXD0 */ 526 #define ENET_MII_TXD0_PB11 \ 527 GD32_PINMUX_AF('B', 11, AF11) 528 529 /* ENET_MII_TXD1 */ 530 #define ENET_MII_TXD1_PB12 \ 531 GD32_PINMUX_AF('B', 12, AF11) 532 533 /* ENET_MII_TXD2 */ 534 #define ENET_MII_TXD2_PC2 \ 535 GD32_PINMUX_AF('C', 2, AF11) 536 537 /* ENET_MII_TXD3 */ 538 #define ENET_MII_TXD3_PB8 \ 539 GD32_PINMUX_AF('B', 8, AF11) 540 #define ENET_MII_TXD3_PE2 \ 541 GD32_PINMUX_AF('E', 2, AF11) 542 543 /* ENET_MII_TX_CLK */ 544 #define ENET_MII_TX_CLK_PC3 \ 545 GD32_PINMUX_AF('C', 3, AF11) 546 547 /* ENET_MII_TX_EN */ 548 #define ENET_MII_TX_EN_PB10 \ 549 GD32_PINMUX_AF('B', 10, AF11) 550 551 /* ENET_PPS_OUT */ 552 #define ENET_PPS_OUT_PB5 \ 553 GD32_PINMUX_AF('B', 5, AF11) 554 555 /* ENET_RMII_CRS_DV */ 556 #define ENET_RMII_CRS_DV_PA7 \ 557 GD32_PINMUX_AF('A', 7, AF11) 558 559 /* ENET_RMII_REF_CLK */ 560 #define ENET_RMII_REF_CLK_PA1 \ 561 GD32_PINMUX_AF('A', 1, AF11) 562 563 /* ENET_RMII_RXD0 */ 564 #define ENET_RMII_RXD0_PC4 \ 565 GD32_PINMUX_AF('C', 4, AF11) 566 567 /* ENET_RMII_RXD1 */ 568 #define ENET_RMII_RXD1_PC5 \ 569 GD32_PINMUX_AF('C', 5, AF11) 570 571 /* ENET_RMII_TXD0 */ 572 #define ENET_RMII_TXD0_PB11 \ 573 GD32_PINMUX_AF('B', 11, AF11) 574 575 /* ENET_RMII_TXD1 */ 576 #define ENET_RMII_TXD1_PB12 \ 577 GD32_PINMUX_AF('B', 12, AF11) 578 579 /* ENET_RMII_TX_EN */ 580 #define ENET_RMII_TX_EN_PB10 \ 581 GD32_PINMUX_AF('B', 10, AF11) 582 583 /* EVENTOUT */ 584 #define EVENTOUT_PA0 \ 585 GD32_PINMUX_AF('A', 0, AF15) 586 #define EVENTOUT_PA1 \ 587 GD32_PINMUX_AF('A', 1, AF15) 588 #define EVENTOUT_PA2 \ 589 GD32_PINMUX_AF('A', 2, AF15) 590 #define EVENTOUT_PA3 \ 591 GD32_PINMUX_AF('A', 3, AF15) 592 #define EVENTOUT_PA4 \ 593 GD32_PINMUX_AF('A', 4, AF15) 594 #define EVENTOUT_PA5 \ 595 GD32_PINMUX_AF('A', 5, AF15) 596 #define EVENTOUT_PA6 \ 597 GD32_PINMUX_AF('A', 6, AF15) 598 #define EVENTOUT_PA7 \ 599 GD32_PINMUX_AF('A', 7, AF15) 600 #define EVENTOUT_PA8 \ 601 GD32_PINMUX_AF('A', 8, AF15) 602 #define EVENTOUT_PA9 \ 603 GD32_PINMUX_AF('A', 9, AF15) 604 #define EVENTOUT_PA10 \ 605 GD32_PINMUX_AF('A', 10, AF15) 606 #define EVENTOUT_PA11 \ 607 GD32_PINMUX_AF('A', 11, AF15) 608 #define EVENTOUT_PA12 \ 609 GD32_PINMUX_AF('A', 12, AF15) 610 #define EVENTOUT_PA13 \ 611 GD32_PINMUX_AF('A', 13, AF15) 612 #define EVENTOUT_PA14 \ 613 GD32_PINMUX_AF('A', 14, AF15) 614 #define EVENTOUT_PA15 \ 615 GD32_PINMUX_AF('A', 15, AF15) 616 #define EVENTOUT_PB0 \ 617 GD32_PINMUX_AF('B', 0, AF15) 618 #define EVENTOUT_PB1 \ 619 GD32_PINMUX_AF('B', 1, AF15) 620 #define EVENTOUT_PB2 \ 621 GD32_PINMUX_AF('B', 2, AF15) 622 #define EVENTOUT_PB3 \ 623 GD32_PINMUX_AF('B', 3, AF15) 624 #define EVENTOUT_PB4 \ 625 GD32_PINMUX_AF('B', 4, AF15) 626 #define EVENTOUT_PB5 \ 627 GD32_PINMUX_AF('B', 5, AF15) 628 #define EVENTOUT_PB6 \ 629 GD32_PINMUX_AF('B', 6, AF15) 630 #define EVENTOUT_PB7 \ 631 GD32_PINMUX_AF('B', 7, AF15) 632 #define EVENTOUT_PB8 \ 633 GD32_PINMUX_AF('B', 8, AF15) 634 #define EVENTOUT_PB9 \ 635 GD32_PINMUX_AF('B', 9, AF15) 636 #define EVENTOUT_PB10 \ 637 GD32_PINMUX_AF('B', 10, AF15) 638 #define EVENTOUT_PB11 \ 639 GD32_PINMUX_AF('B', 11, AF15) 640 #define EVENTOUT_PB12 \ 641 GD32_PINMUX_AF('B', 12, AF15) 642 #define EVENTOUT_PB13 \ 643 GD32_PINMUX_AF('B', 13, AF15) 644 #define EVENTOUT_PB14 \ 645 GD32_PINMUX_AF('B', 14, AF15) 646 #define EVENTOUT_PB15 \ 647 GD32_PINMUX_AF('B', 15, AF15) 648 #define EVENTOUT_PC0 \ 649 GD32_PINMUX_AF('C', 0, AF15) 650 #define EVENTOUT_PC1 \ 651 GD32_PINMUX_AF('C', 1, AF15) 652 #define EVENTOUT_PC2 \ 653 GD32_PINMUX_AF('C', 2, AF15) 654 #define EVENTOUT_PC3 \ 655 GD32_PINMUX_AF('C', 3, AF15) 656 #define EVENTOUT_PC4 \ 657 GD32_PINMUX_AF('C', 4, AF15) 658 #define EVENTOUT_PC5 \ 659 GD32_PINMUX_AF('C', 5, AF15) 660 #define EVENTOUT_PC6 \ 661 GD32_PINMUX_AF('C', 6, AF15) 662 #define EVENTOUT_PC7 \ 663 GD32_PINMUX_AF('C', 7, AF15) 664 #define EVENTOUT_PC8 \ 665 GD32_PINMUX_AF('C', 8, AF15) 666 #define EVENTOUT_PC9 \ 667 GD32_PINMUX_AF('C', 9, AF15) 668 #define EVENTOUT_PC10 \ 669 GD32_PINMUX_AF('C', 10, AF15) 670 #define EVENTOUT_PC11 \ 671 GD32_PINMUX_AF('C', 11, AF15) 672 #define EVENTOUT_PC12 \ 673 GD32_PINMUX_AF('C', 12, AF15) 674 #define EVENTOUT_PC13 \ 675 GD32_PINMUX_AF('C', 13, AF15) 676 #define EVENTOUT_PC14 \ 677 GD32_PINMUX_AF('C', 14, AF15) 678 #define EVENTOUT_PC15 \ 679 GD32_PINMUX_AF('C', 15, AF15) 680 #define EVENTOUT_PD0 \ 681 GD32_PINMUX_AF('D', 0, AF15) 682 #define EVENTOUT_PD1 \ 683 GD32_PINMUX_AF('D', 1, AF15) 684 #define EVENTOUT_PD2 \ 685 GD32_PINMUX_AF('D', 2, AF15) 686 #define EVENTOUT_PD3 \ 687 GD32_PINMUX_AF('D', 3, AF15) 688 #define EVENTOUT_PD4 \ 689 GD32_PINMUX_AF('D', 4, AF15) 690 #define EVENTOUT_PD5 \ 691 GD32_PINMUX_AF('D', 5, AF15) 692 #define EVENTOUT_PD6 \ 693 GD32_PINMUX_AF('D', 6, AF15) 694 #define EVENTOUT_PD7 \ 695 GD32_PINMUX_AF('D', 7, AF15) 696 #define EVENTOUT_PD8 \ 697 GD32_PINMUX_AF('D', 8, AF15) 698 #define EVENTOUT_PD9 \ 699 GD32_PINMUX_AF('D', 9, AF15) 700 #define EVENTOUT_PD10 \ 701 GD32_PINMUX_AF('D', 10, AF15) 702 #define EVENTOUT_PD11 \ 703 GD32_PINMUX_AF('D', 11, AF15) 704 #define EVENTOUT_PD12 \ 705 GD32_PINMUX_AF('D', 12, AF15) 706 #define EVENTOUT_PD13 \ 707 GD32_PINMUX_AF('D', 13, AF15) 708 #define EVENTOUT_PD14 \ 709 GD32_PINMUX_AF('D', 14, AF15) 710 #define EVENTOUT_PD15 \ 711 GD32_PINMUX_AF('D', 15, AF15) 712 #define EVENTOUT_PE0 \ 713 GD32_PINMUX_AF('E', 0, AF15) 714 #define EVENTOUT_PE1 \ 715 GD32_PINMUX_AF('E', 1, AF15) 716 #define EVENTOUT_PE2 \ 717 GD32_PINMUX_AF('E', 2, AF15) 718 #define EVENTOUT_PE3 \ 719 GD32_PINMUX_AF('E', 3, AF15) 720 #define EVENTOUT_PE4 \ 721 GD32_PINMUX_AF('E', 4, AF15) 722 #define EVENTOUT_PE5 \ 723 GD32_PINMUX_AF('E', 5, AF15) 724 #define EVENTOUT_PE6 \ 725 GD32_PINMUX_AF('E', 6, AF15) 726 #define EVENTOUT_PE7 \ 727 GD32_PINMUX_AF('E', 7, AF15) 728 #define EVENTOUT_PE8 \ 729 GD32_PINMUX_AF('E', 8, AF15) 730 #define EVENTOUT_PE9 \ 731 GD32_PINMUX_AF('E', 9, AF15) 732 #define EVENTOUT_PE10 \ 733 GD32_PINMUX_AF('E', 10, AF15) 734 #define EVENTOUT_PE11 \ 735 GD32_PINMUX_AF('E', 11, AF15) 736 #define EVENTOUT_PE12 \ 737 GD32_PINMUX_AF('E', 12, AF15) 738 #define EVENTOUT_PE13 \ 739 GD32_PINMUX_AF('E', 13, AF15) 740 #define EVENTOUT_PE14 \ 741 GD32_PINMUX_AF('E', 14, AF15) 742 #define EVENTOUT_PE15 \ 743 GD32_PINMUX_AF('E', 15, AF15) 744 #define EVENTOUT_PF0 \ 745 GD32_PINMUX_AF('F', 0, AF15) 746 #define EVENTOUT_PF1 \ 747 GD32_PINMUX_AF('F', 1, AF15) 748 #define EVENTOUT_PF2 \ 749 GD32_PINMUX_AF('F', 2, AF15) 750 #define EVENTOUT_PF3 \ 751 GD32_PINMUX_AF('F', 3, AF15) 752 #define EVENTOUT_PF4 \ 753 GD32_PINMUX_AF('F', 4, AF15) 754 #define EVENTOUT_PF5 \ 755 GD32_PINMUX_AF('F', 5, AF15) 756 #define EVENTOUT_PF6 \ 757 GD32_PINMUX_AF('F', 6, AF15) 758 #define EVENTOUT_PF7 \ 759 GD32_PINMUX_AF('F', 7, AF15) 760 #define EVENTOUT_PF8 \ 761 GD32_PINMUX_AF('F', 8, AF15) 762 #define EVENTOUT_PF9 \ 763 GD32_PINMUX_AF('F', 9, AF15) 764 #define EVENTOUT_PF10 \ 765 GD32_PINMUX_AF('F', 10, AF15) 766 #define EVENTOUT_PF11 \ 767 GD32_PINMUX_AF('F', 11, AF15) 768 #define EVENTOUT_PF12 \ 769 GD32_PINMUX_AF('F', 12, AF15) 770 #define EVENTOUT_PF13 \ 771 GD32_PINMUX_AF('F', 13, AF15) 772 #define EVENTOUT_PF14 \ 773 GD32_PINMUX_AF('F', 14, AF15) 774 #define EVENTOUT_PF15 \ 775 GD32_PINMUX_AF('F', 15, AF15) 776 #define EVENTOUT_PG0 \ 777 GD32_PINMUX_AF('G', 0, AF15) 778 #define EVENTOUT_PG1 \ 779 GD32_PINMUX_AF('G', 1, AF15) 780 #define EVENTOUT_PG2 \ 781 GD32_PINMUX_AF('G', 2, AF15) 782 #define EVENTOUT_PG3 \ 783 GD32_PINMUX_AF('G', 3, AF15) 784 #define EVENTOUT_PG4 \ 785 GD32_PINMUX_AF('G', 4, AF15) 786 #define EVENTOUT_PG5 \ 787 GD32_PINMUX_AF('G', 5, AF15) 788 #define EVENTOUT_PG6 \ 789 GD32_PINMUX_AF('G', 6, AF15) 790 #define EVENTOUT_PG7 \ 791 GD32_PINMUX_AF('G', 7, AF15) 792 #define EVENTOUT_PG8 \ 793 GD32_PINMUX_AF('G', 8, AF15) 794 #define EVENTOUT_PG9 \ 795 GD32_PINMUX_AF('G', 9, AF15) 796 #define EVENTOUT_PG10 \ 797 GD32_PINMUX_AF('G', 10, AF15) 798 #define EVENTOUT_PG11 \ 799 GD32_PINMUX_AF('G', 11, AF15) 800 #define EVENTOUT_PG12 \ 801 GD32_PINMUX_AF('G', 12, AF15) 802 #define EVENTOUT_PG13 \ 803 GD32_PINMUX_AF('G', 13, AF15) 804 #define EVENTOUT_PG14 \ 805 GD32_PINMUX_AF('G', 14, AF15) 806 #define EVENTOUT_PG15 \ 807 GD32_PINMUX_AF('G', 15, AF15) 808 809 /* EXMC_A0 */ 810 #define EXMC_A0_PF0 \ 811 GD32_PINMUX_AF('F', 0, AF12) 812 813 /* EXMC_A1 */ 814 #define EXMC_A1_PF1 \ 815 GD32_PINMUX_AF('F', 1, AF12) 816 817 /* EXMC_A10 */ 818 #define EXMC_A10_PG0 \ 819 GD32_PINMUX_AF('G', 0, AF12) 820 821 /* EXMC_A11 */ 822 #define EXMC_A11_PG1 \ 823 GD32_PINMUX_AF('G', 1, AF12) 824 825 /* EXMC_A12 */ 826 #define EXMC_A12_PG2 \ 827 GD32_PINMUX_AF('G', 2, AF12) 828 829 /* EXMC_A13 */ 830 #define EXMC_A13_PG3 \ 831 GD32_PINMUX_AF('G', 3, AF12) 832 833 /* EXMC_A14 */ 834 #define EXMC_A14_PG4 \ 835 GD32_PINMUX_AF('G', 4, AF12) 836 837 /* EXMC_A15 */ 838 #define EXMC_A15_PG5 \ 839 GD32_PINMUX_AF('G', 5, AF12) 840 841 /* EXMC_A16 */ 842 #define EXMC_A16_PD11 \ 843 GD32_PINMUX_AF('D', 11, AF12) 844 845 /* EXMC_A17 */ 846 #define EXMC_A17_PD12 \ 847 GD32_PINMUX_AF('D', 12, AF12) 848 849 /* EXMC_A18 */ 850 #define EXMC_A18_PD13 \ 851 GD32_PINMUX_AF('D', 13, AF12) 852 853 /* EXMC_A19 */ 854 #define EXMC_A19_PE3 \ 855 GD32_PINMUX_AF('E', 3, AF12) 856 857 /* EXMC_A2 */ 858 #define EXMC_A2_PF2 \ 859 GD32_PINMUX_AF('F', 2, AF12) 860 861 /* EXMC_A20 */ 862 #define EXMC_A20_PE4 \ 863 GD32_PINMUX_AF('E', 4, AF12) 864 865 /* EXMC_A21 */ 866 #define EXMC_A21_PE5 \ 867 GD32_PINMUX_AF('E', 5, AF12) 868 869 /* EXMC_A22 */ 870 #define EXMC_A22_PE6 \ 871 GD32_PINMUX_AF('E', 6, AF12) 872 873 /* EXMC_A23 */ 874 #define EXMC_A23_PE2 \ 875 GD32_PINMUX_AF('E', 2, AF12) 876 877 /* EXMC_A24 */ 878 #define EXMC_A24_PG13 \ 879 GD32_PINMUX_AF('G', 13, AF12) 880 881 /* EXMC_A25 */ 882 #define EXMC_A25_PG14 \ 883 GD32_PINMUX_AF('G', 14, AF12) 884 885 /* EXMC_A3 */ 886 #define EXMC_A3_PF3 \ 887 GD32_PINMUX_AF('F', 3, AF12) 888 889 /* EXMC_A4 */ 890 #define EXMC_A4_PF4 \ 891 GD32_PINMUX_AF('F', 4, AF12) 892 893 /* EXMC_A5 */ 894 #define EXMC_A5_PF5 \ 895 GD32_PINMUX_AF('F', 5, AF12) 896 897 /* EXMC_A6 */ 898 #define EXMC_A6_PF12 \ 899 GD32_PINMUX_AF('F', 12, AF12) 900 901 /* EXMC_A7 */ 902 #define EXMC_A7_PF13 \ 903 GD32_PINMUX_AF('F', 13, AF12) 904 905 /* EXMC_A8 */ 906 #define EXMC_A8_PF14 \ 907 GD32_PINMUX_AF('F', 14, AF12) 908 909 /* EXMC_A9 */ 910 #define EXMC_A9_PF15 \ 911 GD32_PINMUX_AF('F', 15, AF12) 912 913 /* EXMC_ALE */ 914 #define EXMC_ALE_PD12 \ 915 GD32_PINMUX_AF('D', 12, AF12) 916 917 /* EXMC_CD */ 918 #define EXMC_CD_PF9 \ 919 GD32_PINMUX_AF('F', 9, AF12) 920 921 /* EXMC_CLE */ 922 #define EXMC_CLE_PD11 \ 923 GD32_PINMUX_AF('D', 11, AF12) 924 925 /* EXMC_CLK */ 926 #define EXMC_CLK_PD3 \ 927 GD32_PINMUX_AF('D', 3, AF12) 928 929 /* EXMC_D0 */ 930 #define EXMC_D0_PD14 \ 931 GD32_PINMUX_AF('D', 14, AF12) 932 933 /* EXMC_D1 */ 934 #define EXMC_D1_PD15 \ 935 GD32_PINMUX_AF('D', 15, AF12) 936 937 /* EXMC_D10 */ 938 #define EXMC_D10_PE13 \ 939 GD32_PINMUX_AF('E', 13, AF12) 940 941 /* EXMC_D11 */ 942 #define EXMC_D11_PE14 \ 943 GD32_PINMUX_AF('E', 14, AF12) 944 945 /* EXMC_D12 */ 946 #define EXMC_D12_PE15 \ 947 GD32_PINMUX_AF('E', 15, AF12) 948 949 /* EXMC_D13 */ 950 #define EXMC_D13_PD8 \ 951 GD32_PINMUX_AF('D', 8, AF12) 952 953 /* EXMC_D14 */ 954 #define EXMC_D14_PD9 \ 955 GD32_PINMUX_AF('D', 9, AF12) 956 957 /* EXMC_D15 */ 958 #define EXMC_D15_PD10 \ 959 GD32_PINMUX_AF('D', 10, AF12) 960 961 /* EXMC_D2 */ 962 #define EXMC_D2_PD0 \ 963 GD32_PINMUX_AF('D', 0, AF12) 964 965 /* EXMC_D3 */ 966 #define EXMC_D3_PD1 \ 967 GD32_PINMUX_AF('D', 1, AF12) 968 969 /* EXMC_D4 */ 970 #define EXMC_D4_PE7 \ 971 GD32_PINMUX_AF('E', 7, AF12) 972 973 /* EXMC_D5 */ 974 #define EXMC_D5_PE8 \ 975 GD32_PINMUX_AF('E', 8, AF12) 976 977 /* EXMC_D6 */ 978 #define EXMC_D6_PE9 \ 979 GD32_PINMUX_AF('E', 9, AF12) 980 981 /* EXMC_D7 */ 982 #define EXMC_D7_PE10 \ 983 GD32_PINMUX_AF('E', 10, AF12) 984 985 /* EXMC_D8 */ 986 #define EXMC_D8_PE11 \ 987 GD32_PINMUX_AF('E', 11, AF12) 988 989 /* EXMC_D9 */ 990 #define EXMC_D9_PE12 \ 991 GD32_PINMUX_AF('E', 12, AF12) 992 993 /* EXMC_INT1 */ 994 #define EXMC_INT1_PG6 \ 995 GD32_PINMUX_AF('G', 6, AF12) 996 997 /* EXMC_INT2 */ 998 #define EXMC_INT2_PG7 \ 999 GD32_PINMUX_AF('G', 7, AF12) 1000 1001 /* EXMC_INTR */ 1002 #define EXMC_INTR_PF10 \ 1003 GD32_PINMUX_AF('F', 10, AF12) 1004 1005 /* EXMC_NADV */ 1006 #define EXMC_NADV_PB7 \ 1007 GD32_PINMUX_AF('B', 7, AF12) 1008 1009 /* EXMC_NBL0 */ 1010 #define EXMC_NBL0_PE0 \ 1011 GD32_PINMUX_AF('E', 0, AF12) 1012 1013 /* EXMC_NBL1 */ 1014 #define EXMC_NBL1_PE1 \ 1015 GD32_PINMUX_AF('E', 1, AF12) 1016 1017 /* EXMC_NCE1 */ 1018 #define EXMC_NCE1_PD7 \ 1019 GD32_PINMUX_AF('D', 7, AF12) 1020 1021 /* EXMC_NCE2 */ 1022 #define EXMC_NCE2_PG9 \ 1023 GD32_PINMUX_AF('G', 9, AF12) 1024 1025 /* EXMC_NCE3_0 */ 1026 #define EXMC_NCE3_0_PG10 \ 1027 GD32_PINMUX_AF('G', 10, AF12) 1028 1029 /* EXMC_NCE3_1 */ 1030 #define EXMC_NCE3_1_PG11 \ 1031 GD32_PINMUX_AF('G', 11, AF12) 1032 1033 /* EXMC_NE0 */ 1034 #define EXMC_NE0_PD7 \ 1035 GD32_PINMUX_AF('D', 7, AF12) 1036 1037 /* EXMC_NE1 */ 1038 #define EXMC_NE1_PG9 \ 1039 GD32_PINMUX_AF('G', 9, AF12) 1040 1041 /* EXMC_NE2 */ 1042 #define EXMC_NE2_PG10 \ 1043 GD32_PINMUX_AF('G', 10, AF12) 1044 1045 /* EXMC_NE3 */ 1046 #define EXMC_NE3_PG12 \ 1047 GD32_PINMUX_AF('G', 12, AF12) 1048 1049 /* EXMC_NIORD */ 1050 #define EXMC_NIORD_PF6 \ 1051 GD32_PINMUX_AF('F', 6, AF12) 1052 1053 /* EXMC_NIOWR */ 1054 #define EXMC_NIOWR_PF8 \ 1055 GD32_PINMUX_AF('F', 8, AF12) 1056 1057 /* EXMC_NL */ 1058 #define EXMC_NL_PB7 \ 1059 GD32_PINMUX_AF('B', 7, AF12) 1060 1061 /* EXMC_NOE */ 1062 #define EXMC_NOE_PD4 \ 1063 GD32_PINMUX_AF('D', 4, AF12) 1064 1065 /* EXMC_NREG */ 1066 #define EXMC_NREG_PF7 \ 1067 GD32_PINMUX_AF('F', 7, AF12) 1068 1069 /* EXMC_NWAIT */ 1070 #define EXMC_NWAIT_PD6 \ 1071 GD32_PINMUX_AF('D', 6, AF12) 1072 1073 /* EXMC_NWE */ 1074 #define EXMC_NWE_PD5 \ 1075 GD32_PINMUX_AF('D', 5, AF12) 1076 1077 /* EXMC_SDCKE0 */ 1078 #define EXMC_SDCKE0_PC3 \ 1079 GD32_PINMUX_AF('C', 3, AF12) 1080 #define EXMC_SDCKE0_PC5 \ 1081 GD32_PINMUX_AF('C', 5, AF12) 1082 1083 /* EXMC_SDCKE1 */ 1084 #define EXMC_SDCKE1_PB5 \ 1085 GD32_PINMUX_AF('B', 5, AF12) 1086 1087 /* EXMC_SDCLK */ 1088 #define EXMC_SDCLK_PG8 \ 1089 GD32_PINMUX_AF('G', 8, AF12) 1090 1091 /* EXMC_SDNCAS */ 1092 #define EXMC_SDNCAS_PG15 \ 1093 GD32_PINMUX_AF('G', 15, AF12) 1094 1095 /* EXMC_SDNE0 */ 1096 #define EXMC_SDNE0_PC2 \ 1097 GD32_PINMUX_AF('C', 2, AF12) 1098 #define EXMC_SDNE0_PC4 \ 1099 GD32_PINMUX_AF('C', 4, AF12) 1100 1101 /* EXMC_SDNE1 */ 1102 #define EXMC_SDNE1_PB6 \ 1103 GD32_PINMUX_AF('B', 6, AF11) 1104 1105 /* EXMC_SDNRAS */ 1106 #define EXMC_SDNRAS_PF11 \ 1107 GD32_PINMUX_AF('F', 11, AF12) 1108 1109 /* EXMC_SDNWE */ 1110 #define EXMC_SDNWE_PC0 \ 1111 GD32_PINMUX_AF('C', 0, AF12) 1112 1113 /* EXMC_SD_NWE */ 1114 #define EXMC_SD_NWE_PA7 \ 1115 GD32_PINMUX_AF('A', 7, AF12) 1116 1117 /* I2C0_SCL */ 1118 #define I2C0_SCL_PB6 \ 1119 GD32_PINMUX_AF('B', 6, AF4) 1120 #define I2C0_SCL_PB8 \ 1121 GD32_PINMUX_AF('B', 8, AF4) 1122 1123 /* I2C0_SDA */ 1124 #define I2C0_SDA_PB7 \ 1125 GD32_PINMUX_AF('B', 7, AF4) 1126 #define I2C0_SDA_PB9 \ 1127 GD32_PINMUX_AF('B', 9, AF4) 1128 1129 /* I2C0_SMBA */ 1130 #define I2C0_SMBA_PB5 \ 1131 GD32_PINMUX_AF('B', 5, AF4) 1132 1133 /* I2C0_TXFRAME */ 1134 #define I2C0_TXFRAME_PB4 \ 1135 GD32_PINMUX_AF('B', 4, AF4) 1136 1137 /* I2C1_SCL */ 1138 #define I2C1_SCL_PB10 \ 1139 GD32_PINMUX_AF('B', 10, AF4) 1140 #define I2C1_SCL_PF1 \ 1141 GD32_PINMUX_AF('F', 1, AF4) 1142 1143 /* I2C1_SDA */ 1144 #define I2C1_SDA_PB3 \ 1145 GD32_PINMUX_AF('B', 3, AF9) 1146 #define I2C1_SDA_PB11 \ 1147 GD32_PINMUX_AF('B', 11, AF4) 1148 #define I2C1_SDA_PC12 \ 1149 GD32_PINMUX_AF('C', 12, AF4) 1150 #define I2C1_SDA_PF0 \ 1151 GD32_PINMUX_AF('F', 0, AF4) 1152 1153 /* I2C1_SMBA */ 1154 #define I2C1_SMBA_PB12 \ 1155 GD32_PINMUX_AF('B', 12, AF4) 1156 #define I2C1_SMBA_PF2 \ 1157 GD32_PINMUX_AF('F', 2, AF4) 1158 1159 /* I2C1_TXFRAME */ 1160 #define I2C1_TXFRAME_PB13 \ 1161 GD32_PINMUX_AF('B', 13, AF4) 1162 #define I2C1_TXFRAME_PF3 \ 1163 GD32_PINMUX_AF('F', 3, AF4) 1164 1165 /* I2C2_SCL */ 1166 #define I2C2_SCL_PA8 \ 1167 GD32_PINMUX_AF('A', 8, AF4) 1168 1169 /* I2C2_SDA */ 1170 #define I2C2_SDA_PB4 \ 1171 GD32_PINMUX_AF('B', 4, AF9) 1172 #define I2C2_SDA_PC9 \ 1173 GD32_PINMUX_AF('C', 9, AF4) 1174 1175 /* I2C2_SMBA */ 1176 #define I2C2_SMBA_PA9 \ 1177 GD32_PINMUX_AF('A', 9, AF4) 1178 1179 /* I2C2_TXFRAME */ 1180 #define I2C2_TXFRAME_PA10 \ 1181 GD32_PINMUX_AF('A', 10, AF4) 1182 1183 /* I2S1_ADD_SD */ 1184 #define I2S1_ADD_SD_PB14 \ 1185 GD32_PINMUX_AF('B', 14, AF6) 1186 #define I2S1_ADD_SD_PC2 \ 1187 GD32_PINMUX_AF('C', 2, AF6) 1188 1189 /* I2S1_CK */ 1190 #define I2S1_CK_PA9 \ 1191 GD32_PINMUX_AF('A', 9, AF5) 1192 #define I2S1_CK_PB10 \ 1193 GD32_PINMUX_AF('B', 10, AF5) 1194 #define I2S1_CK_PB13 \ 1195 GD32_PINMUX_AF('B', 13, AF5) 1196 #define I2S1_CK_PC7 \ 1197 GD32_PINMUX_AF('C', 7, AF5) 1198 #define I2S1_CK_PD3 \ 1199 GD32_PINMUX_AF('D', 3, AF5) 1200 1201 /* I2S1_MCK */ 1202 #define I2S1_MCK_PA3 \ 1203 GD32_PINMUX_AF('A', 3, AF5) 1204 #define I2S1_MCK_PA6 \ 1205 GD32_PINMUX_AF('A', 6, AF6) 1206 #define I2S1_MCK_PC6 \ 1207 GD32_PINMUX_AF('C', 6, AF5) 1208 1209 /* I2S1_SD */ 1210 #define I2S1_SD_PB15 \ 1211 GD32_PINMUX_AF('B', 15, AF5) 1212 #define I2S1_SD_PC1 \ 1213 GD32_PINMUX_AF('C', 1, AF7) 1214 #define I2S1_SD_PC3 \ 1215 GD32_PINMUX_AF('C', 3, AF5) 1216 1217 /* I2S1_WS */ 1218 #define I2S1_WS_PB9 \ 1219 GD32_PINMUX_AF('B', 9, AF5) 1220 #define I2S1_WS_PB12 \ 1221 GD32_PINMUX_AF('B', 12, AF5) 1222 #define I2S1_WS_PD1 \ 1223 GD32_PINMUX_AF('D', 1, AF7) 1224 1225 /* I2S2_ADD_SD */ 1226 #define I2S2_ADD_SD_PB4 \ 1227 GD32_PINMUX_AF('B', 4, AF7) 1228 #define I2S2_ADD_SD_PC11 \ 1229 GD32_PINMUX_AF('C', 11, AF5) 1230 1231 /* I2S2_CK */ 1232 #define I2S2_CK_PB3 \ 1233 GD32_PINMUX_AF('B', 3, AF6) 1234 #define I2S2_CK_PC10 \ 1235 GD32_PINMUX_AF('C', 10, AF6) 1236 1237 /* I2S2_MCK */ 1238 #define I2S2_MCK_PB10 \ 1239 GD32_PINMUX_AF('B', 10, AF6) 1240 #define I2S2_MCK_PC7 \ 1241 GD32_PINMUX_AF('C', 7, AF6) 1242 1243 /* I2S2_SD */ 1244 #define I2S2_SD_PB0 \ 1245 GD32_PINMUX_AF('B', 0, AF7) 1246 #define I2S2_SD_PB2 \ 1247 GD32_PINMUX_AF('B', 2, AF7) 1248 #define I2S2_SD_PB5 \ 1249 GD32_PINMUX_AF('B', 5, AF6) 1250 #define I2S2_SD_PC1 \ 1251 GD32_PINMUX_AF('C', 1, AF5) 1252 #define I2S2_SD_PC12 \ 1253 GD32_PINMUX_AF('C', 12, AF6) 1254 #define I2S2_SD_PD0 \ 1255 GD32_PINMUX_AF('D', 0, AF6) 1256 #define I2S2_SD_PD6 \ 1257 GD32_PINMUX_AF('D', 6, AF5) 1258 1259 /* I2S2_WS */ 1260 #define I2S2_WS_PA4 \ 1261 GD32_PINMUX_AF('A', 4, AF6) 1262 #define I2S2_WS_PA15 \ 1263 GD32_PINMUX_AF('A', 15, AF6) 1264 1265 /* I2S_CKIN */ 1266 #define I2S_CKIN_PA2 \ 1267 GD32_PINMUX_AF('A', 2, AF5) 1268 #define I2S_CKIN_PB11 \ 1269 GD32_PINMUX_AF('B', 11, AF5) 1270 #define I2S_CKIN_PC9 \ 1271 GD32_PINMUX_AF('C', 9, AF5) 1272 1273 /* JTCK */ 1274 #define JTCK_PA14 \ 1275 GD32_PINMUX_AF('A', 14, AF0) 1276 1277 /* JTDI */ 1278 #define JTDI_PA15 \ 1279 GD32_PINMUX_AF('A', 15, AF0) 1280 1281 /* JTDO */ 1282 #define JTDO_PB3 \ 1283 GD32_PINMUX_AF('B', 3, AF0) 1284 1285 /* JTMS */ 1286 #define JTMS_PA13 \ 1287 GD32_PINMUX_AF('A', 13, AF0) 1288 1289 /* NJTRST */ 1290 #define NJTRST_PB4 \ 1291 GD32_PINMUX_AF('B', 4, AF0) 1292 1293 /* RTC_REFIN */ 1294 #define RTC_REFIN_PB15 \ 1295 GD32_PINMUX_AF('B', 15, AF0) 1296 1297 /* SDIO_CK */ 1298 #define SDIO_CK_PB2 \ 1299 GD32_PINMUX_AF('B', 2, AF12) 1300 #define SDIO_CK_PC12 \ 1301 GD32_PINMUX_AF('C', 12, AF12) 1302 1303 /* SDIO_CMD */ 1304 #define SDIO_CMD_PA6 \ 1305 GD32_PINMUX_AF('A', 6, AF12) 1306 #define SDIO_CMD_PD2 \ 1307 GD32_PINMUX_AF('D', 2, AF12) 1308 1309 /* SDIO_D0 */ 1310 #define SDIO_D0_PB4 \ 1311 GD32_PINMUX_AF('B', 4, AF12) 1312 #define SDIO_D0_PC8 \ 1313 GD32_PINMUX_AF('C', 8, AF12) 1314 1315 /* SDIO_D1 */ 1316 #define SDIO_D1_PA8 \ 1317 GD32_PINMUX_AF('A', 8, AF12) 1318 #define SDIO_D1_PB0 \ 1319 GD32_PINMUX_AF('B', 0, AF12) 1320 #define SDIO_D1_PC9 \ 1321 GD32_PINMUX_AF('C', 9, AF12) 1322 1323 /* SDIO_D2 */ 1324 #define SDIO_D2_PA9 \ 1325 GD32_PINMUX_AF('A', 9, AF12) 1326 #define SDIO_D2_PB1 \ 1327 GD32_PINMUX_AF('B', 1, AF12) 1328 #define SDIO_D2_PC10 \ 1329 GD32_PINMUX_AF('C', 10, AF12) 1330 1331 /* SDIO_D3 */ 1332 #define SDIO_D3_PC11 \ 1333 GD32_PINMUX_AF('C', 11, AF12) 1334 1335 /* SDIO_D4 */ 1336 #define SDIO_D4_PB8 \ 1337 GD32_PINMUX_AF('B', 8, AF12) 1338 1339 /* SDIO_D5 */ 1340 #define SDIO_D5_PB9 \ 1341 GD32_PINMUX_AF('B', 9, AF12) 1342 1343 /* SDIO_D6 */ 1344 #define SDIO_D6_PC6 \ 1345 GD32_PINMUX_AF('C', 6, AF12) 1346 1347 /* SDIO_D7 */ 1348 #define SDIO_D7_PB10 \ 1349 GD32_PINMUX_AF('B', 10, AF12) 1350 #define SDIO_D7_PC7 \ 1351 GD32_PINMUX_AF('C', 7, AF12) 1352 1353 /* SPI0_MISO */ 1354 #define SPI0_MISO_PA6 \ 1355 GD32_PINMUX_AF('A', 6, AF5) 1356 #define SPI0_MISO_PB4 \ 1357 GD32_PINMUX_AF('B', 4, AF5) 1358 1359 /* SPI0_MOSI */ 1360 #define SPI0_MOSI_PA7 \ 1361 GD32_PINMUX_AF('A', 7, AF5) 1362 #define SPI0_MOSI_PB5 \ 1363 GD32_PINMUX_AF('B', 5, AF5) 1364 1365 /* SPI0_NSS */ 1366 #define SPI0_NSS_PA4 \ 1367 GD32_PINMUX_AF('A', 4, AF5) 1368 #define SPI0_NSS_PA15 \ 1369 GD32_PINMUX_AF('A', 15, AF5) 1370 1371 /* SPI0_SCK */ 1372 #define SPI0_SCK_PA5 \ 1373 GD32_PINMUX_AF('A', 5, AF5) 1374 #define SPI0_SCK_PB3 \ 1375 GD32_PINMUX_AF('B', 3, AF5) 1376 1377 /* SPI1_MISO */ 1378 #define SPI1_MISO_PB14 \ 1379 GD32_PINMUX_AF('B', 14, AF5) 1380 #define SPI1_MISO_PC2 \ 1381 GD32_PINMUX_AF('C', 2, AF5) 1382 1383 /* SPI1_MOSI */ 1384 #define SPI1_MOSI_PB15 \ 1385 GD32_PINMUX_AF('B', 15, AF5) 1386 #define SPI1_MOSI_PC1 \ 1387 GD32_PINMUX_AF('C', 1, AF7) 1388 #define SPI1_MOSI_PC3 \ 1389 GD32_PINMUX_AF('C', 3, AF5) 1390 1391 /* SPI1_NSS */ 1392 #define SPI1_NSS_PB9 \ 1393 GD32_PINMUX_AF('B', 9, AF5) 1394 #define SPI1_NSS_PB12 \ 1395 GD32_PINMUX_AF('B', 12, AF5) 1396 #define SPI1_NSS_PD1 \ 1397 GD32_PINMUX_AF('D', 1, AF7) 1398 1399 /* SPI1_SCK */ 1400 #define SPI1_SCK_PA9 \ 1401 GD32_PINMUX_AF('A', 9, AF5) 1402 #define SPI1_SCK_PB10 \ 1403 GD32_PINMUX_AF('B', 10, AF5) 1404 #define SPI1_SCK_PB13 \ 1405 GD32_PINMUX_AF('B', 13, AF5) 1406 #define SPI1_SCK_PC7 \ 1407 GD32_PINMUX_AF('C', 7, AF5) 1408 #define SPI1_SCK_PD3 \ 1409 GD32_PINMUX_AF('D', 3, AF5) 1410 1411 /* SPI2_MISO */ 1412 #define SPI2_MISO_PB4 \ 1413 GD32_PINMUX_AF('B', 4, AF6) 1414 #define SPI2_MISO_PC11 \ 1415 GD32_PINMUX_AF('C', 11, AF6) 1416 1417 /* SPI2_MOSI */ 1418 #define SPI2_MOSI_PB0 \ 1419 GD32_PINMUX_AF('B', 0, AF7) 1420 #define SPI2_MOSI_PB2 \ 1421 GD32_PINMUX_AF('B', 2, AF7) 1422 #define SPI2_MOSI_PB5 \ 1423 GD32_PINMUX_AF('B', 5, AF6) 1424 #define SPI2_MOSI_PC1 \ 1425 GD32_PINMUX_AF('C', 1, AF5) 1426 #define SPI2_MOSI_PC12 \ 1427 GD32_PINMUX_AF('C', 12, AF6) 1428 #define SPI2_MOSI_PD0 \ 1429 GD32_PINMUX_AF('D', 0, AF6) 1430 #define SPI2_MOSI_PD6 \ 1431 GD32_PINMUX_AF('D', 6, AF5) 1432 1433 /* SPI2_NSS */ 1434 #define SPI2_NSS_PA4 \ 1435 GD32_PINMUX_AF('A', 4, AF6) 1436 #define SPI2_NSS_PA15 \ 1437 GD32_PINMUX_AF('A', 15, AF6) 1438 1439 /* SPI2_SCK */ 1440 #define SPI2_SCK_PB3 \ 1441 GD32_PINMUX_AF('B', 3, AF6) 1442 #define SPI2_SCK_PC10 \ 1443 GD32_PINMUX_AF('C', 10, AF6) 1444 1445 /* SWCLK */ 1446 #define SWCLK_PA14 \ 1447 GD32_PINMUX_AF('A', 14, AF0) 1448 1449 /* SWDIO */ 1450 #define SWDIO_PA13 \ 1451 GD32_PINMUX_AF('A', 13, AF0) 1452 1453 /* TIMER0_BRKIN */ 1454 #define TIMER0_BRKIN_PA6 \ 1455 GD32_PINMUX_AF('A', 6, AF1) 1456 #define TIMER0_BRKIN_PB12 \ 1457 GD32_PINMUX_AF('B', 12, AF1) 1458 #define TIMER0_BRKIN_PE15 \ 1459 GD32_PINMUX_AF('E', 15, AF1) 1460 1461 /* TIMER0_CH0 */ 1462 #define TIMER0_CH0_PA8 \ 1463 GD32_PINMUX_AF('A', 8, AF1) 1464 #define TIMER0_CH0_PE9 \ 1465 GD32_PINMUX_AF('E', 9, AF0) 1466 1467 /* TIMER0_CH0_ON */ 1468 #define TIMER0_CH0_ON_PA7 \ 1469 GD32_PINMUX_AF('A', 7, AF1) 1470 #define TIMER0_CH0_ON_PB13 \ 1471 GD32_PINMUX_AF('B', 13, AF1) 1472 #define TIMER0_CH0_ON_PE8 \ 1473 GD32_PINMUX_AF('E', 8, AF1) 1474 1475 /* TIMER0_CH1 */ 1476 #define TIMER0_CH1_PA9 \ 1477 GD32_PINMUX_AF('A', 9, AF1) 1478 #define TIMER0_CH1_PE11 \ 1479 GD32_PINMUX_AF('E', 11, AF0) 1480 1481 /* TIMER0_CH1_ON */ 1482 #define TIMER0_CH1_ON_PB0 \ 1483 GD32_PINMUX_AF('B', 0, AF1) 1484 #define TIMER0_CH1_ON_PB14 \ 1485 GD32_PINMUX_AF('B', 14, AF1) 1486 #define TIMER0_CH1_ON_PE1 \ 1487 GD32_PINMUX_AF('E', 1, AF1) 1488 #define TIMER0_CH1_ON_PE10 \ 1489 GD32_PINMUX_AF('E', 10, AF1) 1490 1491 /* TIMER0_CH2 */ 1492 #define TIMER0_CH2_PA10 \ 1493 GD32_PINMUX_AF('A', 10, AF1) 1494 #define TIMER0_CH2_PE13 \ 1495 GD32_PINMUX_AF('E', 13, AF0) 1496 1497 /* TIMER0_CH2_ON */ 1498 #define TIMER0_CH2_ON_PB1 \ 1499 GD32_PINMUX_AF('B', 1, AF1) 1500 #define TIMER0_CH2_ON_PB15 \ 1501 GD32_PINMUX_AF('B', 15, AF1) 1502 #define TIMER0_CH2_ON_PE12 \ 1503 GD32_PINMUX_AF('E', 12, AF1) 1504 1505 /* TIMER0_CH3 */ 1506 #define TIMER0_CH3_PA11 \ 1507 GD32_PINMUX_AF('A', 11, AF1) 1508 #define TIMER0_CH3_PE14 \ 1509 GD32_PINMUX_AF('E', 14, AF0) 1510 1511 /* TIMER0_ETI */ 1512 #define TIMER0_ETI_PA12 \ 1513 GD32_PINMUX_AF('A', 12, AF1) 1514 #define TIMER0_ETI_PE7 \ 1515 GD32_PINMUX_AF('E', 7, AF0) 1516 1517 /* TIMER10_CH0 */ 1518 #define TIMER10_CH0_PB9 \ 1519 GD32_PINMUX_AF('B', 9, AF3) 1520 #define TIMER10_CH0_PF7 \ 1521 GD32_PINMUX_AF('F', 7, AF3) 1522 1523 /* TIMER11_CH0 */ 1524 #define TIMER11_CH0_PB14 \ 1525 GD32_PINMUX_AF('B', 14, AF9) 1526 1527 /* TIMER11_CH1 */ 1528 #define TIMER11_CH1_PB15 \ 1529 GD32_PINMUX_AF('B', 15, AF9) 1530 1531 /* TIMER12_CH0 */ 1532 #define TIMER12_CH0_PA6 \ 1533 GD32_PINMUX_AF('A', 6, AF9) 1534 #define TIMER12_CH0_PF8 \ 1535 GD32_PINMUX_AF('F', 8, AF9) 1536 1537 /* TIMER13_CH0 */ 1538 #define TIMER13_CH0_PA7 \ 1539 GD32_PINMUX_AF('A', 7, AF9) 1540 #define TIMER13_CH0_PF9 \ 1541 GD32_PINMUX_AF('F', 9, AF9) 1542 1543 /* TIMER1_CH0 */ 1544 #define TIMER1_CH0_PA0 \ 1545 GD32_PINMUX_AF('A', 0, AF1) 1546 #define TIMER1_CH0_PA5 \ 1547 GD32_PINMUX_AF('A', 5, AF1) 1548 #define TIMER1_CH0_PA15 \ 1549 GD32_PINMUX_AF('A', 15, AF1) 1550 #define TIMER1_CH0_PB8 \ 1551 GD32_PINMUX_AF('B', 8, AF1) 1552 1553 /* TIMER1_CH1 */ 1554 #define TIMER1_CH1_PA1 \ 1555 GD32_PINMUX_AF('A', 1, AF1) 1556 #define TIMER1_CH1_PB3 \ 1557 GD32_PINMUX_AF('B', 3, AF1) 1558 #define TIMER1_CH1_PB9 \ 1559 GD32_PINMUX_AF('B', 9, AF1) 1560 1561 /* TIMER1_CH2 */ 1562 #define TIMER1_CH2_PA2 \ 1563 GD32_PINMUX_AF('A', 2, AF1) 1564 #define TIMER1_CH2_PB10 \ 1565 GD32_PINMUX_AF('B', 10, AF1) 1566 1567 /* TIMER1_CH3 */ 1568 #define TIMER1_CH3_PA3 \ 1569 GD32_PINMUX_AF('A', 3, AF1) 1570 #define TIMER1_CH3_PB2 \ 1571 GD32_PINMUX_AF('B', 2, AF1) 1572 #define TIMER1_CH3_PB11 \ 1573 GD32_PINMUX_AF('B', 11, AF1) 1574 1575 /* TIMER1_ETI */ 1576 #define TIMER1_ETI_PA0 \ 1577 GD32_PINMUX_AF('A', 0, AF1) 1578 #define TIMER1_ETI_PA5 \ 1579 GD32_PINMUX_AF('A', 5, AF1) 1580 #define TIMER1_ETI_PA15 \ 1581 GD32_PINMUX_AF('A', 15, AF1) 1582 #define TIMER1_ETI_PB8 \ 1583 GD32_PINMUX_AF('B', 8, AF1) 1584 1585 /* TIMER2_CH0 */ 1586 #define TIMER2_CH0_PA6 \ 1587 GD32_PINMUX_AF('A', 6, AF2) 1588 #define TIMER2_CH0_PB4 \ 1589 GD32_PINMUX_AF('B', 4, AF2) 1590 #define TIMER2_CH0_PC6 \ 1591 GD32_PINMUX_AF('C', 6, AF2) 1592 1593 /* TIMER2_CH1 */ 1594 #define TIMER2_CH1_PA7 \ 1595 GD32_PINMUX_AF('A', 7, AF2) 1596 #define TIMER2_CH1_PB5 \ 1597 GD32_PINMUX_AF('B', 5, AF2) 1598 #define TIMER2_CH1_PC7 \ 1599 GD32_PINMUX_AF('C', 7, AF2) 1600 1601 /* TIMER2_CH2 */ 1602 #define TIMER2_CH2_PB0 \ 1603 GD32_PINMUX_AF('B', 0, AF2) 1604 #define TIMER2_CH2_PC8 \ 1605 GD32_PINMUX_AF('C', 8, AF2) 1606 1607 /* TIMER2_CH3 */ 1608 #define TIMER2_CH3_PB1 \ 1609 GD32_PINMUX_AF('B', 1, AF2) 1610 #define TIMER2_CH3_PC9 \ 1611 GD32_PINMUX_AF('C', 9, AF2) 1612 1613 /* TIMER2_ETI */ 1614 #define TIMER2_ETI_PD2 \ 1615 GD32_PINMUX_AF('D', 2, AF2) 1616 1617 /* TIMER3_CH0 */ 1618 #define TIMER3_CH0_PB6 \ 1619 GD32_PINMUX_AF('B', 6, AF2) 1620 #define TIMER3_CH0_PD12 \ 1621 GD32_PINMUX_AF('D', 12, AF2) 1622 1623 /* TIMER3_CH1 */ 1624 #define TIMER3_CH1_PB7 \ 1625 GD32_PINMUX_AF('B', 7, AF2) 1626 #define TIMER3_CH1_PD13 \ 1627 GD32_PINMUX_AF('D', 13, AF2) 1628 1629 /* TIMER3_CH2 */ 1630 #define TIMER3_CH2_PB8 \ 1631 GD32_PINMUX_AF('B', 8, AF2) 1632 #define TIMER3_CH2_PD14 \ 1633 GD32_PINMUX_AF('D', 14, AF2) 1634 1635 /* TIMER3_CH3 */ 1636 #define TIMER3_CH3_PB9 \ 1637 GD32_PINMUX_AF('B', 9, AF2) 1638 #define TIMER3_CH3_PD15 \ 1639 GD32_PINMUX_AF('D', 15, AF2) 1640 1641 /* TIMER3_ETI */ 1642 #define TIMER3_ETI_PE0 \ 1643 GD32_PINMUX_AF('E', 0, AF2) 1644 1645 /* TIMER4_CH0 */ 1646 #define TIMER4_CH0_PA0 \ 1647 GD32_PINMUX_AF('A', 0, AF2) 1648 1649 /* TIMER4_CH1 */ 1650 #define TIMER4_CH1_PA1 \ 1651 GD32_PINMUX_AF('A', 1, AF2) 1652 1653 /* TIMER4_CH2 */ 1654 #define TIMER4_CH2_PA2 \ 1655 GD32_PINMUX_AF('A', 2, AF2) 1656 1657 /* TIMER4_CH3 */ 1658 #define TIMER4_CH3_PA3 \ 1659 GD32_PINMUX_AF('A', 3, AF2) 1660 1661 /* TIMER7_BRKIN */ 1662 #define TIMER7_BRKIN_PA6 \ 1663 GD32_PINMUX_AF('A', 6, AF3) 1664 1665 /* TIMER7_CH0 */ 1666 #define TIMER7_CH0_PC6 \ 1667 GD32_PINMUX_AF('C', 6, AF3) 1668 1669 /* TIMER7_CH0_ON */ 1670 #define TIMER7_CH0_ON_PA5 \ 1671 GD32_PINMUX_AF('A', 5, AF3) 1672 #define TIMER7_CH0_ON_PA7 \ 1673 GD32_PINMUX_AF('A', 7, AF3) 1674 1675 /* TIMER7_CH1 */ 1676 #define TIMER7_CH1_PC7 \ 1677 GD32_PINMUX_AF('C', 7, AF3) 1678 1679 /* TIMER7_CH1_ON */ 1680 #define TIMER7_CH1_ON_PB0 \ 1681 GD32_PINMUX_AF('B', 0, AF3) 1682 #define TIMER7_CH1_ON_PB14 \ 1683 GD32_PINMUX_AF('B', 14, AF3) 1684 1685 /* TIMER7_CH2 */ 1686 #define TIMER7_CH2_PC8 \ 1687 GD32_PINMUX_AF('C', 8, AF3) 1688 1689 /* TIMER7_CH2_ON */ 1690 #define TIMER7_CH2_ON_PB1 \ 1691 GD32_PINMUX_AF('B', 1, AF3) 1692 #define TIMER7_CH2_ON_PB15 \ 1693 GD32_PINMUX_AF('B', 15, AF3) 1694 1695 /* TIMER7_CH3 */ 1696 #define TIMER7_CH3_PC9 \ 1697 GD32_PINMUX_AF('C', 9, AF3) 1698 1699 /* TIMER7_ETI */ 1700 #define TIMER7_ETI_PA0 \ 1701 GD32_PINMUX_AF('A', 0, AF3) 1702 1703 /* TIMER8_CH0 */ 1704 #define TIMER8_CH0_PA2 \ 1705 GD32_PINMUX_AF('A', 2, AF3) 1706 #define TIMER8_CH0_PE5 \ 1707 GD32_PINMUX_AF('E', 5, AF3) 1708 1709 /* TIMER8_CH1 */ 1710 #define TIMER8_CH1_PA3 \ 1711 GD32_PINMUX_AF('A', 3, AF3) 1712 #define TIMER8_CH1_PE6 \ 1713 GD32_PINMUX_AF('E', 6, AF3) 1714 1715 /* TIMER9_CH0 */ 1716 #define TIMER9_CH0_PB8 \ 1717 GD32_PINMUX_AF('B', 8, AF3) 1718 #define TIMER9_CH0_PF6 \ 1719 GD32_PINMUX_AF('F', 6, AF3) 1720 1721 /* TRACECK */ 1722 #define TRACECK_PE2 \ 1723 GD32_PINMUX_AF('E', 2, AF0) 1724 1725 /* TRACED0 */ 1726 #define TRACED0_PC8 \ 1727 GD32_PINMUX_AF('C', 8, AF0) 1728 #define TRACED0_PE3 \ 1729 GD32_PINMUX_AF('E', 3, AF0) 1730 1731 /* TRACED1 */ 1732 #define TRACED1_PD3 \ 1733 GD32_PINMUX_AF('D', 3, AF0) 1734 #define TRACED1_PE4 \ 1735 GD32_PINMUX_AF('E', 4, AF0) 1736 1737 /* TRACED2 */ 1738 #define TRACED2_PE5 \ 1739 GD32_PINMUX_AF('E', 5, AF0) 1740 #define TRACED2_PG13 \ 1741 GD32_PINMUX_AF('G', 13, AF0) 1742 1743 /* TRACED3 */ 1744 #define TRACED3_PE6 \ 1745 GD32_PINMUX_AF('E', 6, AF0) 1746 #define TRACED3_PG14 \ 1747 GD32_PINMUX_AF('G', 14, AF0) 1748 1749 /* TRACESWO */ 1750 #define TRACESWO_PB3 \ 1751 GD32_PINMUX_AF('B', 3, AF0) 1752 1753 /* UART3_RX */ 1754 #define UART3_RX_PA1 \ 1755 GD32_PINMUX_AF('A', 1, AF8) 1756 #define UART3_RX_PC11 \ 1757 GD32_PINMUX_AF('C', 11, AF8) 1758 1759 /* UART3_TX */ 1760 #define UART3_TX_PA0 \ 1761 GD32_PINMUX_AF('A', 0, AF8) 1762 #define UART3_TX_PC10 \ 1763 GD32_PINMUX_AF('C', 10, AF8) 1764 1765 /* UART4_RX */ 1766 #define UART4_RX_PD2 \ 1767 GD32_PINMUX_AF('D', 2, AF8) 1768 1769 /* UART4_TX */ 1770 #define UART4_TX_PC12 \ 1771 GD32_PINMUX_AF('C', 12, AF8) 1772 1773 /* USART0_CK */ 1774 #define USART0_CK_PA8 \ 1775 GD32_PINMUX_AF('A', 8, AF7) 1776 1777 /* USART0_CTS */ 1778 #define USART0_CTS_PA11 \ 1779 GD32_PINMUX_AF('A', 11, AF7) 1780 1781 /* USART0_RTS */ 1782 #define USART0_RTS_PA12 \ 1783 GD32_PINMUX_AF('A', 12, AF7) 1784 1785 /* USART0_RX */ 1786 #define USART0_RX_PA10 \ 1787 GD32_PINMUX_AF('A', 10, AF7) 1788 #define USART0_RX_PB3 \ 1789 GD32_PINMUX_AF('B', 3, AF7) 1790 #define USART0_RX_PB7 \ 1791 GD32_PINMUX_AF('B', 7, AF7) 1792 1793 /* USART0_TX */ 1794 #define USART0_TX_PA9 \ 1795 GD32_PINMUX_AF('A', 9, AF7) 1796 #define USART0_TX_PA15 \ 1797 GD32_PINMUX_AF('A', 15, AF7) 1798 #define USART0_TX_PB6 \ 1799 GD32_PINMUX_AF('B', 6, AF7) 1800 1801 /* USART1_CK */ 1802 #define USART1_CK_PA4 \ 1803 GD32_PINMUX_AF('A', 4, AF7) 1804 #define USART1_CK_PD7 \ 1805 GD32_PINMUX_AF('D', 7, AF7) 1806 1807 /* USART1_CTS */ 1808 #define USART1_CTS_PA0 \ 1809 GD32_PINMUX_AF('A', 0, AF7) 1810 #define USART1_CTS_PD3 \ 1811 GD32_PINMUX_AF('D', 3, AF7) 1812 1813 /* USART1_RTS */ 1814 #define USART1_RTS_PA1 \ 1815 GD32_PINMUX_AF('A', 1, AF7) 1816 #define USART1_RTS_PD4 \ 1817 GD32_PINMUX_AF('D', 4, AF7) 1818 1819 /* USART1_RX */ 1820 #define USART1_RX_PA3 \ 1821 GD32_PINMUX_AF('A', 3, AF7) 1822 #define USART1_RX_PD6 \ 1823 GD32_PINMUX_AF('D', 6, AF7) 1824 1825 /* USART1_TX */ 1826 #define USART1_TX_PA2 \ 1827 GD32_PINMUX_AF('A', 2, AF7) 1828 #define USART1_TX_PD5 \ 1829 GD32_PINMUX_AF('D', 5, AF7) 1830 1831 /* USART2_CK */ 1832 #define USART2_CK_PB12 \ 1833 GD32_PINMUX_AF('B', 12, AF7) 1834 #define USART2_CK_PC12 \ 1835 GD32_PINMUX_AF('C', 12, AF7) 1836 #define USART2_CK_PD10 \ 1837 GD32_PINMUX_AF('D', 10, AF7) 1838 1839 /* USART2_CTS */ 1840 #define USART2_CTS_PB13 \ 1841 GD32_PINMUX_AF('B', 13, AF7) 1842 #define USART2_CTS_PD11 \ 1843 GD32_PINMUX_AF('D', 11, AF7) 1844 1845 /* USART2_RTS */ 1846 #define USART2_RTS_PB14 \ 1847 GD32_PINMUX_AF('B', 14, AF7) 1848 #define USART2_RTS_PD12 \ 1849 GD32_PINMUX_AF('D', 12, AF7) 1850 1851 /* USART2_RX */ 1852 #define USART2_RX_PB11 \ 1853 GD32_PINMUX_AF('B', 11, AF7) 1854 #define USART2_RX_PC5 \ 1855 GD32_PINMUX_AF('C', 5, AF7) 1856 #define USART2_RX_PC11 \ 1857 GD32_PINMUX_AF('C', 11, AF7) 1858 #define USART2_RX_PD9 \ 1859 GD32_PINMUX_AF('D', 9, AF7) 1860 1861 /* USART2_TX */ 1862 #define USART2_TX_PB10 \ 1863 GD32_PINMUX_AF('B', 10, AF7) 1864 #define USART2_TX_PC10 \ 1865 GD32_PINMUX_AF('C', 10, AF7) 1866 #define USART2_TX_PD8 \ 1867 GD32_PINMUX_AF('D', 8, AF7) 1868 1869 /* USART5_CK */ 1870 #define USART5_CK_PC8 \ 1871 GD32_PINMUX_AF('C', 8, AF8) 1872 #define USART5_CK_PG7 \ 1873 GD32_PINMUX_AF('G', 7, AF8) 1874 1875 /* USART5_CTS */ 1876 #define USART5_CTS_PG13 \ 1877 GD32_PINMUX_AF('G', 13, AF8) 1878 #define USART5_CTS_PG15 \ 1879 GD32_PINMUX_AF('G', 15, AF8) 1880 1881 /* USART5_RTS */ 1882 #define USART5_RTS_PG8 \ 1883 GD32_PINMUX_AF('G', 8, AF8) 1884 #define USART5_RTS_PG12 \ 1885 GD32_PINMUX_AF('G', 12, AF8) 1886 1887 /* USART5_RX */ 1888 #define USART5_RX_PA12 \ 1889 GD32_PINMUX_AF('A', 12, AF8) 1890 #define USART5_RX_PC7 \ 1891 GD32_PINMUX_AF('C', 7, AF8) 1892 #define USART5_RX_PG9 \ 1893 GD32_PINMUX_AF('G', 9, AF8) 1894 1895 /* USART5_TX */ 1896 #define USART5_TX_PA11 \ 1897 GD32_PINMUX_AF('A', 11, AF8) 1898 #define USART5_TX_PC6 \ 1899 GD32_PINMUX_AF('C', 6, AF8) 1900 #define USART5_TX_PG14 \ 1901 GD32_PINMUX_AF('G', 14, AF8) 1902 1903 /* USBFS_DM */ 1904 #define USBFS_DM_PA11 \ 1905 GD32_PINMUX_AF('A', 11, AF10) 1906 1907 /* USBFS_DP */ 1908 #define USBFS_DP_PA12 \ 1909 GD32_PINMUX_AF('A', 12, AF10) 1910 1911 /* USBFS_ID */ 1912 #define USBFS_ID_PA10 \ 1913 GD32_PINMUX_AF('A', 10, AF10) 1914 1915 /* USBFS_SOF */ 1916 #define USBFS_SOF_PA8 \ 1917 GD32_PINMUX_AF('A', 8, AF10) 1918 1919 /* USBHS_DM */ 1920 #define USBHS_DM_PB14 \ 1921 GD32_PINMUX_AF('B', 14, AF12) 1922 1923 /* USBHS_DP */ 1924 #define USBHS_DP_PB15 \ 1925 GD32_PINMUX_AF('B', 15, AF12) 1926 1927 /* USBHS_ID */ 1928 #define USBHS_ID_PB12 \ 1929 GD32_PINMUX_AF('B', 12, AF12) 1930 1931 /* USBHS_SOF */ 1932 #define USBHS_SOF_PA4 \ 1933 GD32_PINMUX_AF('A', 4, AF12) 1934 1935 /* USBHS_ULPI_CK */ 1936 #define USBHS_ULPI_CK_PA5 \ 1937 GD32_PINMUX_AF('A', 5, AF10) 1938 1939 /* USBHS_ULPI_D0 */ 1940 #define USBHS_ULPI_D0_PA3 \ 1941 GD32_PINMUX_AF('A', 3, AF10) 1942 1943 /* USBHS_ULPI_D1 */ 1944 #define USBHS_ULPI_D1_PB0 \ 1945 GD32_PINMUX_AF('B', 0, AF10) 1946 1947 /* USBHS_ULPI_D2 */ 1948 #define USBHS_ULPI_D2_PB1 \ 1949 GD32_PINMUX_AF('B', 1, AF10) 1950 1951 /* USBHS_ULPI_D3 */ 1952 #define USBHS_ULPI_D3_PB10 \ 1953 GD32_PINMUX_AF('B', 10, AF10) 1954 1955 /* USBHS_ULPI_D4 */ 1956 #define USBHS_ULPI_D4_PB2 \ 1957 GD32_PINMUX_AF('B', 2, AF10) 1958 #define USBHS_ULPI_D4_PB11 \ 1959 GD32_PINMUX_AF('B', 11, AF10) 1960 1961 /* USBHS_ULPI_D5 */ 1962 #define USBHS_ULPI_D5_PB12 \ 1963 GD32_PINMUX_AF('B', 12, AF10) 1964 1965 /* USBHS_ULPI_D6 */ 1966 #define USBHS_ULPI_D6_PB13 \ 1967 GD32_PINMUX_AF('B', 13, AF10) 1968 1969 /* USBHS_ULPI_D7 */ 1970 #define USBHS_ULPI_D7_PB5 \ 1971 GD32_PINMUX_AF('B', 5, AF10) 1972 1973 /* USBHS_ULPI_DIR */ 1974 #define USBHS_ULPI_DIR_PC2 \ 1975 GD32_PINMUX_AF('C', 2, AF10) 1976 1977 /* USBHS_ULPI_NXT */ 1978 #define USBHS_ULPI_NXT_PC3 \ 1979 GD32_PINMUX_AF('C', 3, AF10) 1980 1981 /* USBHS_ULPI_STP */ 1982 #define USBHS_ULPI_STP_PC0 \ 1983 GD32_PINMUX_AF('C', 0, AF10) 1984
