1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32-af.h" 8 9 /* ADC012_IN0 */ 10 #define ADC012_IN0_PA0 \ 11 GD32_PINMUX_AF('A', 0, ANALOG) 12 13 /* ADC012_IN1 */ 14 #define ADC012_IN1_PA1 \ 15 GD32_PINMUX_AF('A', 1, ANALOG) 16 17 /* ADC012_IN10 */ 18 #define ADC012_IN10_PC0 \ 19 GD32_PINMUX_AF('C', 0, ANALOG) 20 21 /* ADC012_IN11 */ 22 #define ADC012_IN11_PC1 \ 23 GD32_PINMUX_AF('C', 1, ANALOG) 24 25 /* ADC012_IN12 */ 26 #define ADC012_IN12_PC2 \ 27 GD32_PINMUX_AF('C', 2, ANALOG) 28 29 /* ADC012_IN13 */ 30 #define ADC012_IN13_PC3 \ 31 GD32_PINMUX_AF('C', 3, ANALOG) 32 33 /* ADC012_IN2 */ 34 #define ADC012_IN2_PA2 \ 35 GD32_PINMUX_AF('A', 2, ANALOG) 36 37 /* ADC012_IN3 */ 38 #define ADC012_IN3_PA3 \ 39 GD32_PINMUX_AF('A', 3, ANALOG) 40 41 /* ADC01_IN14 */ 42 #define ADC01_IN14_PC4 \ 43 GD32_PINMUX_AF('C', 4, ANALOG) 44 45 /* ADC01_IN15 */ 46 #define ADC01_IN15_PC5 \ 47 GD32_PINMUX_AF('C', 5, ANALOG) 48 49 /* ADC01_IN4 */ 50 #define ADC01_IN4_PA4 \ 51 GD32_PINMUX_AF('A', 4, ANALOG) 52 53 /* ADC01_IN5 */ 54 #define ADC01_IN5_PA5 \ 55 GD32_PINMUX_AF('A', 5, ANALOG) 56 57 /* ADC01_IN6 */ 58 #define ADC01_IN6_PA6 \ 59 GD32_PINMUX_AF('A', 6, ANALOG) 60 61 /* ADC01_IN7 */ 62 #define ADC01_IN7_PA7 \ 63 GD32_PINMUX_AF('A', 7, ANALOG) 64 65 /* ADC01_IN8 */ 66 #define ADC01_IN8_PB0 \ 67 GD32_PINMUX_AF('B', 0, ANALOG) 68 69 /* ADC01_IN9 */ 70 #define ADC01_IN9_PB1 \ 71 GD32_PINMUX_AF('B', 1, ANALOG) 72 73 /* ANALOG */ 74 #define ANALOG_PA0 \ 75 GD32_PINMUX_AF('A', 0, ANALOG) 76 #define ANALOG_PA1 \ 77 GD32_PINMUX_AF('A', 1, ANALOG) 78 #define ANALOG_PA2 \ 79 GD32_PINMUX_AF('A', 2, ANALOG) 80 #define ANALOG_PA3 \ 81 GD32_PINMUX_AF('A', 3, ANALOG) 82 #define ANALOG_PA4 \ 83 GD32_PINMUX_AF('A', 4, ANALOG) 84 #define ANALOG_PA5 \ 85 GD32_PINMUX_AF('A', 5, ANALOG) 86 #define ANALOG_PA6 \ 87 GD32_PINMUX_AF('A', 6, ANALOG) 88 #define ANALOG_PA7 \ 89 GD32_PINMUX_AF('A', 7, ANALOG) 90 #define ANALOG_PA8 \ 91 GD32_PINMUX_AF('A', 8, ANALOG) 92 #define ANALOG_PA9 \ 93 GD32_PINMUX_AF('A', 9, ANALOG) 94 #define ANALOG_PA10 \ 95 GD32_PINMUX_AF('A', 10, ANALOG) 96 #define ANALOG_PA11 \ 97 GD32_PINMUX_AF('A', 11, ANALOG) 98 #define ANALOG_PA12 \ 99 GD32_PINMUX_AF('A', 12, ANALOG) 100 #define ANALOG_PA13 \ 101 GD32_PINMUX_AF('A', 13, ANALOG) 102 #define ANALOG_PA14 \ 103 GD32_PINMUX_AF('A', 14, ANALOG) 104 #define ANALOG_PA15 \ 105 GD32_PINMUX_AF('A', 15, ANALOG) 106 #define ANALOG_PB0 \ 107 GD32_PINMUX_AF('B', 0, ANALOG) 108 #define ANALOG_PB1 \ 109 GD32_PINMUX_AF('B', 1, ANALOG) 110 #define ANALOG_PB2 \ 111 GD32_PINMUX_AF('B', 2, ANALOG) 112 #define ANALOG_PB3 \ 113 GD32_PINMUX_AF('B', 3, ANALOG) 114 #define ANALOG_PB4 \ 115 GD32_PINMUX_AF('B', 4, ANALOG) 116 #define ANALOG_PB5 \ 117 GD32_PINMUX_AF('B', 5, ANALOG) 118 #define ANALOG_PB6 \ 119 GD32_PINMUX_AF('B', 6, ANALOG) 120 #define ANALOG_PB7 \ 121 GD32_PINMUX_AF('B', 7, ANALOG) 122 #define ANALOG_PB8 \ 123 GD32_PINMUX_AF('B', 8, ANALOG) 124 #define ANALOG_PB9 \ 125 GD32_PINMUX_AF('B', 9, ANALOG) 126 #define ANALOG_PB10 \ 127 GD32_PINMUX_AF('B', 10, ANALOG) 128 #define ANALOG_PB11 \ 129 GD32_PINMUX_AF('B', 11, ANALOG) 130 #define ANALOG_PB12 \ 131 GD32_PINMUX_AF('B', 12, ANALOG) 132 #define ANALOG_PB13 \ 133 GD32_PINMUX_AF('B', 13, ANALOG) 134 #define ANALOG_PB14 \ 135 GD32_PINMUX_AF('B', 14, ANALOG) 136 #define ANALOG_PB15 \ 137 GD32_PINMUX_AF('B', 15, ANALOG) 138 #define ANALOG_PC0 \ 139 GD32_PINMUX_AF('C', 0, ANALOG) 140 #define ANALOG_PC1 \ 141 GD32_PINMUX_AF('C', 1, ANALOG) 142 #define ANALOG_PC2 \ 143 GD32_PINMUX_AF('C', 2, ANALOG) 144 #define ANALOG_PC3 \ 145 GD32_PINMUX_AF('C', 3, ANALOG) 146 #define ANALOG_PC4 \ 147 GD32_PINMUX_AF('C', 4, ANALOG) 148 #define ANALOG_PC5 \ 149 GD32_PINMUX_AF('C', 5, ANALOG) 150 #define ANALOG_PC6 \ 151 GD32_PINMUX_AF('C', 6, ANALOG) 152 #define ANALOG_PC7 \ 153 GD32_PINMUX_AF('C', 7, ANALOG) 154 #define ANALOG_PC8 \ 155 GD32_PINMUX_AF('C', 8, ANALOG) 156 #define ANALOG_PC9 \ 157 GD32_PINMUX_AF('C', 9, ANALOG) 158 #define ANALOG_PC10 \ 159 GD32_PINMUX_AF('C', 10, ANALOG) 160 #define ANALOG_PC11 \ 161 GD32_PINMUX_AF('C', 11, ANALOG) 162 #define ANALOG_PC12 \ 163 GD32_PINMUX_AF('C', 12, ANALOG) 164 #define ANALOG_PC13 \ 165 GD32_PINMUX_AF('C', 13, ANALOG) 166 #define ANALOG_PC14 \ 167 GD32_PINMUX_AF('C', 14, ANALOG) 168 #define ANALOG_PC15 \ 169 GD32_PINMUX_AF('C', 15, ANALOG) 170 #define ANALOG_PD0 \ 171 GD32_PINMUX_AF('D', 0, ANALOG) 172 #define ANALOG_PD1 \ 173 GD32_PINMUX_AF('D', 1, ANALOG) 174 #define ANALOG_PD2 \ 175 GD32_PINMUX_AF('D', 2, ANALOG) 176 #define ANALOG_PD3 \ 177 GD32_PINMUX_AF('D', 3, ANALOG) 178 #define ANALOG_PD4 \ 179 GD32_PINMUX_AF('D', 4, ANALOG) 180 #define ANALOG_PD5 \ 181 GD32_PINMUX_AF('D', 5, ANALOG) 182 #define ANALOG_PD6 \ 183 GD32_PINMUX_AF('D', 6, ANALOG) 184 #define ANALOG_PD7 \ 185 GD32_PINMUX_AF('D', 7, ANALOG) 186 #define ANALOG_PD8 \ 187 GD32_PINMUX_AF('D', 8, ANALOG) 188 #define ANALOG_PD9 \ 189 GD32_PINMUX_AF('D', 9, ANALOG) 190 #define ANALOG_PD10 \ 191 GD32_PINMUX_AF('D', 10, ANALOG) 192 #define ANALOG_PD11 \ 193 GD32_PINMUX_AF('D', 11, ANALOG) 194 #define ANALOG_PD12 \ 195 GD32_PINMUX_AF('D', 12, ANALOG) 196 #define ANALOG_PD13 \ 197 GD32_PINMUX_AF('D', 13, ANALOG) 198 #define ANALOG_PD14 \ 199 GD32_PINMUX_AF('D', 14, ANALOG) 200 #define ANALOG_PD15 \ 201 GD32_PINMUX_AF('D', 15, ANALOG) 202 #define ANALOG_PE0 \ 203 GD32_PINMUX_AF('E', 0, ANALOG) 204 #define ANALOG_PE1 \ 205 GD32_PINMUX_AF('E', 1, ANALOG) 206 #define ANALOG_PE2 \ 207 GD32_PINMUX_AF('E', 2, ANALOG) 208 #define ANALOG_PE3 \ 209 GD32_PINMUX_AF('E', 3, ANALOG) 210 #define ANALOG_PE4 \ 211 GD32_PINMUX_AF('E', 4, ANALOG) 212 #define ANALOG_PE5 \ 213 GD32_PINMUX_AF('E', 5, ANALOG) 214 #define ANALOG_PE6 \ 215 GD32_PINMUX_AF('E', 6, ANALOG) 216 #define ANALOG_PE7 \ 217 GD32_PINMUX_AF('E', 7, ANALOG) 218 #define ANALOG_PE8 \ 219 GD32_PINMUX_AF('E', 8, ANALOG) 220 #define ANALOG_PE9 \ 221 GD32_PINMUX_AF('E', 9, ANALOG) 222 #define ANALOG_PE10 \ 223 GD32_PINMUX_AF('E', 10, ANALOG) 224 #define ANALOG_PE11 \ 225 GD32_PINMUX_AF('E', 11, ANALOG) 226 #define ANALOG_PE12 \ 227 GD32_PINMUX_AF('E', 12, ANALOG) 228 #define ANALOG_PE13 \ 229 GD32_PINMUX_AF('E', 13, ANALOG) 230 #define ANALOG_PE14 \ 231 GD32_PINMUX_AF('E', 14, ANALOG) 232 #define ANALOG_PE15 \ 233 GD32_PINMUX_AF('E', 15, ANALOG) 234 235 /* CAN0_RX */ 236 #define CAN0_RX_PA11 \ 237 GD32_PINMUX_AF('A', 11, AF9) 238 #define CAN0_RX_PB8 \ 239 GD32_PINMUX_AF('B', 8, AF9) 240 #define CAN0_RX_PD0 \ 241 GD32_PINMUX_AF('D', 0, AF9) 242 243 /* CAN0_TX */ 244 #define CAN0_TX_PA12 \ 245 GD32_PINMUX_AF('A', 12, AF9) 246 #define CAN0_TX_PB9 \ 247 GD32_PINMUX_AF('B', 9, AF9) 248 #define CAN0_TX_PD1 \ 249 GD32_PINMUX_AF('D', 1, AF9) 250 251 /* CAN1_RX */ 252 #define CAN1_RX_PB5 \ 253 GD32_PINMUX_AF('B', 5, AF9) 254 #define CAN1_RX_PB12 \ 255 GD32_PINMUX_AF('B', 12, AF9) 256 257 /* CAN1_TX */ 258 #define CAN1_TX_PB6 \ 259 GD32_PINMUX_AF('B', 6, AF9) 260 #define CAN1_TX_PB13 \ 261 GD32_PINMUX_AF('B', 13, AF9) 262 263 /* CK_OUT0 */ 264 #define CK_OUT0_PA8 \ 265 GD32_PINMUX_AF('A', 8, AF0) 266 267 /* CK_OUT1 */ 268 #define CK_OUT1_PC9 \ 269 GD32_PINMUX_AF('C', 9, AF0) 270 271 /* CTC_SYNC */ 272 #define CTC_SYNC_PA8 \ 273 GD32_PINMUX_AF('A', 8, AF9) 274 #define CTC_SYNC_PD15 \ 275 GD32_PINMUX_AF('D', 15, AF0) 276 277 /* DAC_OUT0 */ 278 #define DAC_OUT0_PA4 \ 279 GD32_PINMUX_AF('A', 4, ANALOG) 280 281 /* DAC_OUT1 */ 282 #define DAC_OUT1_PA5 \ 283 GD32_PINMUX_AF('A', 5, ANALOG) 284 285 /* DCI_D0 */ 286 #define DCI_D0_PA9 \ 287 GD32_PINMUX_AF('A', 9, AF13) 288 #define DCI_D0_PC6 \ 289 GD32_PINMUX_AF('C', 6, AF13) 290 291 /* DCI_D1 */ 292 #define DCI_D1_PA10 \ 293 GD32_PINMUX_AF('A', 10, AF13) 294 #define DCI_D1_PC7 \ 295 GD32_PINMUX_AF('C', 7, AF13) 296 297 /* DCI_D10 */ 298 #define DCI_D10_PB5 \ 299 GD32_PINMUX_AF('B', 5, AF13) 300 #define DCI_D10_PD6 \ 301 GD32_PINMUX_AF('D', 6, AF13) 302 303 /* DCI_D11 */ 304 #define DCI_D11_PD2 \ 305 GD32_PINMUX_AF('D', 2, AF13) 306 307 /* DCI_D2 */ 308 #define DCI_D2_PC8 \ 309 GD32_PINMUX_AF('C', 8, AF13) 310 #define DCI_D2_PE0 \ 311 GD32_PINMUX_AF('E', 0, AF13) 312 313 /* DCI_D3 */ 314 #define DCI_D3_PC9 \ 315 GD32_PINMUX_AF('C', 9, AF13) 316 #define DCI_D3_PE1 \ 317 GD32_PINMUX_AF('E', 1, AF13) 318 319 /* DCI_D4 */ 320 #define DCI_D4_PC11 \ 321 GD32_PINMUX_AF('C', 11, AF13) 322 #define DCI_D4_PE4 \ 323 GD32_PINMUX_AF('E', 4, AF13) 324 325 /* DCI_D5 */ 326 #define DCI_D5_PB6 \ 327 GD32_PINMUX_AF('B', 6, AF13) 328 #define DCI_D5_PD3 \ 329 GD32_PINMUX_AF('D', 3, AF13) 330 331 /* DCI_D6 */ 332 #define DCI_D6_PB8 \ 333 GD32_PINMUX_AF('B', 8, AF13) 334 #define DCI_D6_PE5 \ 335 GD32_PINMUX_AF('E', 5, AF13) 336 337 /* DCI_D7 */ 338 #define DCI_D7_PB9 \ 339 GD32_PINMUX_AF('B', 9, AF13) 340 #define DCI_D7_PE6 \ 341 GD32_PINMUX_AF('E', 6, AF13) 342 343 /* DCI_D8 */ 344 #define DCI_D8_PC10 \ 345 GD32_PINMUX_AF('C', 10, AF13) 346 347 /* DCI_D9 */ 348 #define DCI_D9_PC12 \ 349 GD32_PINMUX_AF('C', 12, AF13) 350 351 /* DCI_HSYNC */ 352 #define DCI_HSYNC_PA4 \ 353 GD32_PINMUX_AF('A', 4, AF13) 354 355 /* DCI_PIXCLK */ 356 #define DCI_PIXCLK_PA6 \ 357 GD32_PINMUX_AF('A', 6, AF13) 358 359 /* DCI_VSYNC */ 360 #define DCI_VSYNC_PB7 \ 361 GD32_PINMUX_AF('B', 7, AF13) 362 363 /* ENET_MDC */ 364 #define ENET_MDC_PC1 \ 365 GD32_PINMUX_AF('C', 1, AF11) 366 367 /* ENET_MDIO */ 368 #define ENET_MDIO_PA2 \ 369 GD32_PINMUX_AF('A', 2, AF11) 370 371 /* ENET_MII_COL */ 372 #define ENET_MII_COL_PA3 \ 373 GD32_PINMUX_AF('A', 3, AF11) 374 375 /* ENET_MII_CRS */ 376 #define ENET_MII_CRS_PA0 \ 377 GD32_PINMUX_AF('A', 0, AF11) 378 379 /* ENET_MII_RXD0 */ 380 #define ENET_MII_RXD0_PC4 \ 381 GD32_PINMUX_AF('C', 4, AF11) 382 383 /* ENET_MII_RXD1 */ 384 #define ENET_MII_RXD1_PC5 \ 385 GD32_PINMUX_AF('C', 5, AF11) 386 387 /* ENET_MII_RXD2 */ 388 #define ENET_MII_RXD2_PB0 \ 389 GD32_PINMUX_AF('B', 0, AF11) 390 391 /* ENET_MII_RXD3 */ 392 #define ENET_MII_RXD3_PB1 \ 393 GD32_PINMUX_AF('B', 1, AF11) 394 395 /* ENET_MII_RX_CLK */ 396 #define ENET_MII_RX_CLK_PA1 \ 397 GD32_PINMUX_AF('A', 1, AF11) 398 399 /* ENET_MII_RX_DV */ 400 #define ENET_MII_RX_DV_PA7 \ 401 GD32_PINMUX_AF('A', 7, AF11) 402 403 /* ENET_MII_RX_ER */ 404 #define ENET_MII_RX_ER_PB9 \ 405 GD32_PINMUX_AF('B', 9, AF1) 406 407 /* ENET_MII_TXD0 */ 408 #define ENET_MII_TXD0_PB11 \ 409 GD32_PINMUX_AF('B', 11, AF11) 410 411 /* ENET_MII_TXD1 */ 412 #define ENET_MII_TXD1_PB12 \ 413 GD32_PINMUX_AF('B', 12, AF11) 414 415 /* ENET_MII_TXD2 */ 416 #define ENET_MII_TXD2_PC2 \ 417 GD32_PINMUX_AF('C', 2, AF11) 418 419 /* ENET_MII_TXD3 */ 420 #define ENET_MII_TXD3_PB8 \ 421 GD32_PINMUX_AF('B', 8, AF11) 422 #define ENET_MII_TXD3_PE2 \ 423 GD32_PINMUX_AF('E', 2, AF11) 424 425 /* ENET_MII_TX_CLK */ 426 #define ENET_MII_TX_CLK_PC3 \ 427 GD32_PINMUX_AF('C', 3, AF11) 428 429 /* ENET_MII_TX_EN */ 430 #define ENET_MII_TX_EN_PB10 \ 431 GD32_PINMUX_AF('B', 10, AF11) 432 433 /* ENET_PPS_OUT */ 434 #define ENET_PPS_OUT_PB5 \ 435 GD32_PINMUX_AF('B', 5, AF11) 436 437 /* ENET_RMII_CRS_DV */ 438 #define ENET_RMII_CRS_DV_PA7 \ 439 GD32_PINMUX_AF('A', 7, AF11) 440 441 /* ENET_RMII_REF_CLK */ 442 #define ENET_RMII_REF_CLK_PA1 \ 443 GD32_PINMUX_AF('A', 1, AF11) 444 445 /* ENET_RMII_RXD0 */ 446 #define ENET_RMII_RXD0_PC4 \ 447 GD32_PINMUX_AF('C', 4, AF11) 448 449 /* ENET_RMII_RXD1 */ 450 #define ENET_RMII_RXD1_PC5 \ 451 GD32_PINMUX_AF('C', 5, AF11) 452 453 /* ENET_RMII_TXD0 */ 454 #define ENET_RMII_TXD0_PB11 \ 455 GD32_PINMUX_AF('B', 11, AF11) 456 457 /* ENET_RMII_TXD1 */ 458 #define ENET_RMII_TXD1_PB12 \ 459 GD32_PINMUX_AF('B', 12, AF11) 460 461 /* ENET_RMII_TX_EN */ 462 #define ENET_RMII_TX_EN_PB10 \ 463 GD32_PINMUX_AF('B', 10, AF11) 464 465 /* EVENTOUT */ 466 #define EVENTOUT_PA0 \ 467 GD32_PINMUX_AF('A', 0, AF15) 468 #define EVENTOUT_PA1 \ 469 GD32_PINMUX_AF('A', 1, AF15) 470 #define EVENTOUT_PA2 \ 471 GD32_PINMUX_AF('A', 2, AF15) 472 #define EVENTOUT_PA3 \ 473 GD32_PINMUX_AF('A', 3, AF15) 474 #define EVENTOUT_PA4 \ 475 GD32_PINMUX_AF('A', 4, AF15) 476 #define EVENTOUT_PA5 \ 477 GD32_PINMUX_AF('A', 5, AF15) 478 #define EVENTOUT_PA6 \ 479 GD32_PINMUX_AF('A', 6, AF15) 480 #define EVENTOUT_PA7 \ 481 GD32_PINMUX_AF('A', 7, AF15) 482 #define EVENTOUT_PA8 \ 483 GD32_PINMUX_AF('A', 8, AF15) 484 #define EVENTOUT_PA9 \ 485 GD32_PINMUX_AF('A', 9, AF15) 486 #define EVENTOUT_PA10 \ 487 GD32_PINMUX_AF('A', 10, AF15) 488 #define EVENTOUT_PA11 \ 489 GD32_PINMUX_AF('A', 11, AF15) 490 #define EVENTOUT_PA12 \ 491 GD32_PINMUX_AF('A', 12, AF15) 492 #define EVENTOUT_PA13 \ 493 GD32_PINMUX_AF('A', 13, AF15) 494 #define EVENTOUT_PA14 \ 495 GD32_PINMUX_AF('A', 14, AF15) 496 #define EVENTOUT_PA15 \ 497 GD32_PINMUX_AF('A', 15, AF15) 498 #define EVENTOUT_PB0 \ 499 GD32_PINMUX_AF('B', 0, AF15) 500 #define EVENTOUT_PB1 \ 501 GD32_PINMUX_AF('B', 1, AF15) 502 #define EVENTOUT_PB2 \ 503 GD32_PINMUX_AF('B', 2, AF15) 504 #define EVENTOUT_PB3 \ 505 GD32_PINMUX_AF('B', 3, AF15) 506 #define EVENTOUT_PB4 \ 507 GD32_PINMUX_AF('B', 4, AF15) 508 #define EVENTOUT_PB5 \ 509 GD32_PINMUX_AF('B', 5, AF15) 510 #define EVENTOUT_PB6 \ 511 GD32_PINMUX_AF('B', 6, AF15) 512 #define EVENTOUT_PB7 \ 513 GD32_PINMUX_AF('B', 7, AF15) 514 #define EVENTOUT_PB8 \ 515 GD32_PINMUX_AF('B', 8, AF15) 516 #define EVENTOUT_PB9 \ 517 GD32_PINMUX_AF('B', 9, AF15) 518 #define EVENTOUT_PB10 \ 519 GD32_PINMUX_AF('B', 10, AF15) 520 #define EVENTOUT_PB11 \ 521 GD32_PINMUX_AF('B', 11, AF15) 522 #define EVENTOUT_PB12 \ 523 GD32_PINMUX_AF('B', 12, AF15) 524 #define EVENTOUT_PB13 \ 525 GD32_PINMUX_AF('B', 13, AF15) 526 #define EVENTOUT_PB14 \ 527 GD32_PINMUX_AF('B', 14, AF15) 528 #define EVENTOUT_PB15 \ 529 GD32_PINMUX_AF('B', 15, AF15) 530 #define EVENTOUT_PC0 \ 531 GD32_PINMUX_AF('C', 0, AF15) 532 #define EVENTOUT_PC1 \ 533 GD32_PINMUX_AF('C', 1, AF15) 534 #define EVENTOUT_PC2 \ 535 GD32_PINMUX_AF('C', 2, AF15) 536 #define EVENTOUT_PC3 \ 537 GD32_PINMUX_AF('C', 3, AF15) 538 #define EVENTOUT_PC4 \ 539 GD32_PINMUX_AF('C', 4, AF15) 540 #define EVENTOUT_PC5 \ 541 GD32_PINMUX_AF('C', 5, AF15) 542 #define EVENTOUT_PC6 \ 543 GD32_PINMUX_AF('C', 6, AF15) 544 #define EVENTOUT_PC7 \ 545 GD32_PINMUX_AF('C', 7, AF15) 546 #define EVENTOUT_PC8 \ 547 GD32_PINMUX_AF('C', 8, AF15) 548 #define EVENTOUT_PC9 \ 549 GD32_PINMUX_AF('C', 9, AF15) 550 #define EVENTOUT_PC10 \ 551 GD32_PINMUX_AF('C', 10, AF15) 552 #define EVENTOUT_PC11 \ 553 GD32_PINMUX_AF('C', 11, AF15) 554 #define EVENTOUT_PC12 \ 555 GD32_PINMUX_AF('C', 12, AF15) 556 #define EVENTOUT_PC13 \ 557 GD32_PINMUX_AF('C', 13, AF15) 558 #define EVENTOUT_PC14 \ 559 GD32_PINMUX_AF('C', 14, AF15) 560 #define EVENTOUT_PC15 \ 561 GD32_PINMUX_AF('C', 15, AF15) 562 #define EVENTOUT_PD0 \ 563 GD32_PINMUX_AF('D', 0, AF15) 564 #define EVENTOUT_PD1 \ 565 GD32_PINMUX_AF('D', 1, AF15) 566 #define EVENTOUT_PD2 \ 567 GD32_PINMUX_AF('D', 2, AF15) 568 #define EVENTOUT_PD3 \ 569 GD32_PINMUX_AF('D', 3, AF15) 570 #define EVENTOUT_PD4 \ 571 GD32_PINMUX_AF('D', 4, AF15) 572 #define EVENTOUT_PD5 \ 573 GD32_PINMUX_AF('D', 5, AF15) 574 #define EVENTOUT_PD6 \ 575 GD32_PINMUX_AF('D', 6, AF15) 576 #define EVENTOUT_PD7 \ 577 GD32_PINMUX_AF('D', 7, AF15) 578 #define EVENTOUT_PD8 \ 579 GD32_PINMUX_AF('D', 8, AF15) 580 #define EVENTOUT_PD9 \ 581 GD32_PINMUX_AF('D', 9, AF15) 582 #define EVENTOUT_PD10 \ 583 GD32_PINMUX_AF('D', 10, AF15) 584 #define EVENTOUT_PD11 \ 585 GD32_PINMUX_AF('D', 11, AF15) 586 #define EVENTOUT_PD12 \ 587 GD32_PINMUX_AF('D', 12, AF15) 588 #define EVENTOUT_PD13 \ 589 GD32_PINMUX_AF('D', 13, AF15) 590 #define EVENTOUT_PD14 \ 591 GD32_PINMUX_AF('D', 14, AF15) 592 #define EVENTOUT_PD15 \ 593 GD32_PINMUX_AF('D', 15, AF15) 594 #define EVENTOUT_PE0 \ 595 GD32_PINMUX_AF('E', 0, AF15) 596 #define EVENTOUT_PE1 \ 597 GD32_PINMUX_AF('E', 1, AF15) 598 #define EVENTOUT_PE2 \ 599 GD32_PINMUX_AF('E', 2, AF15) 600 #define EVENTOUT_PE3 \ 601 GD32_PINMUX_AF('E', 3, AF15) 602 #define EVENTOUT_PE4 \ 603 GD32_PINMUX_AF('E', 4, AF15) 604 #define EVENTOUT_PE5 \ 605 GD32_PINMUX_AF('E', 5, AF15) 606 #define EVENTOUT_PE6 \ 607 GD32_PINMUX_AF('E', 6, AF15) 608 #define EVENTOUT_PE7 \ 609 GD32_PINMUX_AF('E', 7, AF15) 610 #define EVENTOUT_PE8 \ 611 GD32_PINMUX_AF('E', 8, AF15) 612 #define EVENTOUT_PE9 \ 613 GD32_PINMUX_AF('E', 9, AF15) 614 #define EVENTOUT_PE10 \ 615 GD32_PINMUX_AF('E', 10, AF15) 616 #define EVENTOUT_PE11 \ 617 GD32_PINMUX_AF('E', 11, AF15) 618 #define EVENTOUT_PE12 \ 619 GD32_PINMUX_AF('E', 12, AF15) 620 #define EVENTOUT_PE13 \ 621 GD32_PINMUX_AF('E', 13, AF15) 622 #define EVENTOUT_PE14 \ 623 GD32_PINMUX_AF('E', 14, AF15) 624 #define EVENTOUT_PE15 \ 625 GD32_PINMUX_AF('E', 15, AF15) 626 627 /* EXMC_A16 */ 628 #define EXMC_A16_PD11 \ 629 GD32_PINMUX_AF('D', 11, AF12) 630 631 /* EXMC_A17 */ 632 #define EXMC_A17_PD12 \ 633 GD32_PINMUX_AF('D', 12, AF12) 634 635 /* EXMC_A18 */ 636 #define EXMC_A18_PD13 \ 637 GD32_PINMUX_AF('D', 13, AF12) 638 639 /* EXMC_A19 */ 640 #define EXMC_A19_PE3 \ 641 GD32_PINMUX_AF('E', 3, AF12) 642 643 /* EXMC_A20 */ 644 #define EXMC_A20_PE4 \ 645 GD32_PINMUX_AF('E', 4, AF12) 646 647 /* EXMC_A21 */ 648 #define EXMC_A21_PE5 \ 649 GD32_PINMUX_AF('E', 5, AF12) 650 651 /* EXMC_A22 */ 652 #define EXMC_A22_PE6 \ 653 GD32_PINMUX_AF('E', 6, AF12) 654 655 /* EXMC_A23 */ 656 #define EXMC_A23_PE2 \ 657 GD32_PINMUX_AF('E', 2, AF12) 658 659 /* EXMC_ALE */ 660 #define EXMC_ALE_PD12 \ 661 GD32_PINMUX_AF('D', 12, AF12) 662 663 /* EXMC_CLE */ 664 #define EXMC_CLE_PD11 \ 665 GD32_PINMUX_AF('D', 11, AF12) 666 667 /* EXMC_CLK */ 668 #define EXMC_CLK_PD3 \ 669 GD32_PINMUX_AF('D', 3, AF12) 670 671 /* EXMC_D0 */ 672 #define EXMC_D0_PD14 \ 673 GD32_PINMUX_AF('D', 14, AF12) 674 675 /* EXMC_D1 */ 676 #define EXMC_D1_PD15 \ 677 GD32_PINMUX_AF('D', 15, AF12) 678 679 /* EXMC_D10 */ 680 #define EXMC_D10_PE13 \ 681 GD32_PINMUX_AF('E', 13, AF12) 682 683 /* EXMC_D11 */ 684 #define EXMC_D11_PE14 \ 685 GD32_PINMUX_AF('E', 14, AF12) 686 687 /* EXMC_D12 */ 688 #define EXMC_D12_PE15 \ 689 GD32_PINMUX_AF('E', 15, AF12) 690 691 /* EXMC_D13 */ 692 #define EXMC_D13_PD8 \ 693 GD32_PINMUX_AF('D', 8, AF12) 694 695 /* EXMC_D14 */ 696 #define EXMC_D14_PD9 \ 697 GD32_PINMUX_AF('D', 9, AF12) 698 699 /* EXMC_D15 */ 700 #define EXMC_D15_PD10 \ 701 GD32_PINMUX_AF('D', 10, AF12) 702 703 /* EXMC_D2 */ 704 #define EXMC_D2_PD0 \ 705 GD32_PINMUX_AF('D', 0, AF12) 706 707 /* EXMC_D3 */ 708 #define EXMC_D3_PD1 \ 709 GD32_PINMUX_AF('D', 1, AF12) 710 711 /* EXMC_D4 */ 712 #define EXMC_D4_PE7 \ 713 GD32_PINMUX_AF('E', 7, AF12) 714 715 /* EXMC_D5 */ 716 #define EXMC_D5_PE8 \ 717 GD32_PINMUX_AF('E', 8, AF12) 718 719 /* EXMC_D6 */ 720 #define EXMC_D6_PE9 \ 721 GD32_PINMUX_AF('E', 9, AF12) 722 723 /* EXMC_D7 */ 724 #define EXMC_D7_PE10 \ 725 GD32_PINMUX_AF('E', 10, AF12) 726 727 /* EXMC_D8 */ 728 #define EXMC_D8_PE11 \ 729 GD32_PINMUX_AF('E', 11, AF12) 730 731 /* EXMC_D9 */ 732 #define EXMC_D9_PE12 \ 733 GD32_PINMUX_AF('E', 12, AF12) 734 735 /* EXMC_NADV */ 736 #define EXMC_NADV_PB7 \ 737 GD32_PINMUX_AF('B', 7, AF12) 738 739 /* EXMC_NBL0 */ 740 #define EXMC_NBL0_PE0 \ 741 GD32_PINMUX_AF('E', 0, AF12) 742 743 /* EXMC_NBL1 */ 744 #define EXMC_NBL1_PE1 \ 745 GD32_PINMUX_AF('E', 1, AF12) 746 747 /* EXMC_NCE1 */ 748 #define EXMC_NCE1_PD7 \ 749 GD32_PINMUX_AF('D', 7, AF12) 750 751 /* EXMC_NE0 */ 752 #define EXMC_NE0_PD7 \ 753 GD32_PINMUX_AF('D', 7, AF12) 754 755 /* EXMC_NL */ 756 #define EXMC_NL_PB7 \ 757 GD32_PINMUX_AF('B', 7, AF12) 758 759 /* EXMC_NOE */ 760 #define EXMC_NOE_PD4 \ 761 GD32_PINMUX_AF('D', 4, AF12) 762 763 /* EXMC_NWAIT */ 764 #define EXMC_NWAIT_PD6 \ 765 GD32_PINMUX_AF('D', 6, AF12) 766 767 /* EXMC_NWE */ 768 #define EXMC_NWE_PD5 \ 769 GD32_PINMUX_AF('D', 5, AF12) 770 771 /* EXMC_SDCKE0 */ 772 #define EXMC_SDCKE0_PC3 \ 773 GD32_PINMUX_AF('C', 3, AF12) 774 #define EXMC_SDCKE0_PC5 \ 775 GD32_PINMUX_AF('C', 5, AF12) 776 777 /* EXMC_SDCKE1 */ 778 #define EXMC_SDCKE1_PB5 \ 779 GD32_PINMUX_AF('B', 5, AF12) 780 781 /* EXMC_SDNE0 */ 782 #define EXMC_SDNE0_PC2 \ 783 GD32_PINMUX_AF('C', 2, AF12) 784 #define EXMC_SDNE0_PC4 \ 785 GD32_PINMUX_AF('C', 4, AF12) 786 787 /* EXMC_SDNE1 */ 788 #define EXMC_SDNE1_PB6 \ 789 GD32_PINMUX_AF('B', 6, AF11) 790 791 /* EXMC_SDNWE */ 792 #define EXMC_SDNWE_PC0 \ 793 GD32_PINMUX_AF('C', 0, AF12) 794 795 /* EXMC_SD_NWE */ 796 #define EXMC_SD_NWE_PA7 \ 797 GD32_PINMUX_AF('A', 7, AF12) 798 799 /* I2C0_SCL */ 800 #define I2C0_SCL_PB6 \ 801 GD32_PINMUX_AF('B', 6, AF4) 802 #define I2C0_SCL_PB8 \ 803 GD32_PINMUX_AF('B', 8, AF4) 804 805 /* I2C0_SDA */ 806 #define I2C0_SDA_PB7 \ 807 GD32_PINMUX_AF('B', 7, AF4) 808 #define I2C0_SDA_PB9 \ 809 GD32_PINMUX_AF('B', 9, AF4) 810 811 /* I2C0_SMBA */ 812 #define I2C0_SMBA_PB5 \ 813 GD32_PINMUX_AF('B', 5, AF4) 814 815 /* I2C0_TXFRAME */ 816 #define I2C0_TXFRAME_PB4 \ 817 GD32_PINMUX_AF('B', 4, AF4) 818 819 /* I2C1_SCL */ 820 #define I2C1_SCL_PB10 \ 821 GD32_PINMUX_AF('B', 10, AF4) 822 823 /* I2C1_SDA */ 824 #define I2C1_SDA_PB3 \ 825 GD32_PINMUX_AF('B', 3, AF9) 826 #define I2C1_SDA_PB11 \ 827 GD32_PINMUX_AF('B', 11, AF4) 828 #define I2C1_SDA_PC12 \ 829 GD32_PINMUX_AF('C', 12, AF4) 830 831 /* I2C1_SMBA */ 832 #define I2C1_SMBA_PB12 \ 833 GD32_PINMUX_AF('B', 12, AF4) 834 835 /* I2C1_TXFRAME */ 836 #define I2C1_TXFRAME_PB13 \ 837 GD32_PINMUX_AF('B', 13, AF4) 838 839 /* I2C2_SCL */ 840 #define I2C2_SCL_PA8 \ 841 GD32_PINMUX_AF('A', 8, AF4) 842 843 /* I2C2_SDA */ 844 #define I2C2_SDA_PB4 \ 845 GD32_PINMUX_AF('B', 4, AF9) 846 #define I2C2_SDA_PC9 \ 847 GD32_PINMUX_AF('C', 9, AF4) 848 849 /* I2C2_SMBA */ 850 #define I2C2_SMBA_PA9 \ 851 GD32_PINMUX_AF('A', 9, AF4) 852 853 /* I2C2_TXFRAME */ 854 #define I2C2_TXFRAME_PA10 \ 855 GD32_PINMUX_AF('A', 10, AF4) 856 857 /* I2S1_ADD_SD */ 858 #define I2S1_ADD_SD_PB14 \ 859 GD32_PINMUX_AF('B', 14, AF6) 860 #define I2S1_ADD_SD_PC2 \ 861 GD32_PINMUX_AF('C', 2, AF6) 862 863 /* I2S1_CK */ 864 #define I2S1_CK_PA9 \ 865 GD32_PINMUX_AF('A', 9, AF5) 866 #define I2S1_CK_PB10 \ 867 GD32_PINMUX_AF('B', 10, AF5) 868 #define I2S1_CK_PB13 \ 869 GD32_PINMUX_AF('B', 13, AF5) 870 #define I2S1_CK_PC7 \ 871 GD32_PINMUX_AF('C', 7, AF5) 872 #define I2S1_CK_PD3 \ 873 GD32_PINMUX_AF('D', 3, AF5) 874 875 /* I2S1_MCK */ 876 #define I2S1_MCK_PA3 \ 877 GD32_PINMUX_AF('A', 3, AF5) 878 #define I2S1_MCK_PA6 \ 879 GD32_PINMUX_AF('A', 6, AF6) 880 #define I2S1_MCK_PC6 \ 881 GD32_PINMUX_AF('C', 6, AF5) 882 883 /* I2S1_SD */ 884 #define I2S1_SD_PB15 \ 885 GD32_PINMUX_AF('B', 15, AF5) 886 #define I2S1_SD_PC1 \ 887 GD32_PINMUX_AF('C', 1, AF7) 888 #define I2S1_SD_PC3 \ 889 GD32_PINMUX_AF('C', 3, AF5) 890 891 /* I2S1_WS */ 892 #define I2S1_WS_PB9 \ 893 GD32_PINMUX_AF('B', 9, AF5) 894 #define I2S1_WS_PB12 \ 895 GD32_PINMUX_AF('B', 12, AF5) 896 #define I2S1_WS_PD1 \ 897 GD32_PINMUX_AF('D', 1, AF7) 898 899 /* I2S2_ADD_SD */ 900 #define I2S2_ADD_SD_PB4 \ 901 GD32_PINMUX_AF('B', 4, AF7) 902 #define I2S2_ADD_SD_PC11 \ 903 GD32_PINMUX_AF('C', 11, AF5) 904 905 /* I2S2_CK */ 906 #define I2S2_CK_PB3 \ 907 GD32_PINMUX_AF('B', 3, AF6) 908 #define I2S2_CK_PC10 \ 909 GD32_PINMUX_AF('C', 10, AF6) 910 911 /* I2S2_MCK */ 912 #define I2S2_MCK_PB10 \ 913 GD32_PINMUX_AF('B', 10, AF6) 914 #define I2S2_MCK_PC7 \ 915 GD32_PINMUX_AF('C', 7, AF6) 916 917 /* I2S2_SD */ 918 #define I2S2_SD_PB0 \ 919 GD32_PINMUX_AF('B', 0, AF7) 920 #define I2S2_SD_PB2 \ 921 GD32_PINMUX_AF('B', 2, AF7) 922 #define I2S2_SD_PB5 \ 923 GD32_PINMUX_AF('B', 5, AF6) 924 #define I2S2_SD_PC1 \ 925 GD32_PINMUX_AF('C', 1, AF5) 926 #define I2S2_SD_PC12 \ 927 GD32_PINMUX_AF('C', 12, AF6) 928 #define I2S2_SD_PD0 \ 929 GD32_PINMUX_AF('D', 0, AF6) 930 #define I2S2_SD_PD6 \ 931 GD32_PINMUX_AF('D', 6, AF5) 932 933 /* I2S2_WS */ 934 #define I2S2_WS_PA4 \ 935 GD32_PINMUX_AF('A', 4, AF6) 936 #define I2S2_WS_PA15 \ 937 GD32_PINMUX_AF('A', 15, AF6) 938 939 /* I2S_CKIN */ 940 #define I2S_CKIN_PA2 \ 941 GD32_PINMUX_AF('A', 2, AF5) 942 #define I2S_CKIN_PB11 \ 943 GD32_PINMUX_AF('B', 11, AF5) 944 #define I2S_CKIN_PC9 \ 945 GD32_PINMUX_AF('C', 9, AF5) 946 947 /* JTCK */ 948 #define JTCK_PA14 \ 949 GD32_PINMUX_AF('A', 14, AF0) 950 951 /* JTDI */ 952 #define JTDI_PA15 \ 953 GD32_PINMUX_AF('A', 15, AF0) 954 955 /* JTDO */ 956 #define JTDO_PB3 \ 957 GD32_PINMUX_AF('B', 3, AF0) 958 959 /* JTMS */ 960 #define JTMS_PA13 \ 961 GD32_PINMUX_AF('A', 13, AF0) 962 963 /* NJTRST */ 964 #define NJTRST_PB4 \ 965 GD32_PINMUX_AF('B', 4, AF0) 966 967 /* RTC_REFIN */ 968 #define RTC_REFIN_PB15 \ 969 GD32_PINMUX_AF('B', 15, AF0) 970 971 /* SDIO_CK */ 972 #define SDIO_CK_PB2 \ 973 GD32_PINMUX_AF('B', 2, AF12) 974 #define SDIO_CK_PC12 \ 975 GD32_PINMUX_AF('C', 12, AF12) 976 977 /* SDIO_CMD */ 978 #define SDIO_CMD_PA6 \ 979 GD32_PINMUX_AF('A', 6, AF12) 980 #define SDIO_CMD_PD2 \ 981 GD32_PINMUX_AF('D', 2, AF12) 982 983 /* SDIO_D0 */ 984 #define SDIO_D0_PB4 \ 985 GD32_PINMUX_AF('B', 4, AF12) 986 #define SDIO_D0_PC8 \ 987 GD32_PINMUX_AF('C', 8, AF12) 988 989 /* SDIO_D1 */ 990 #define SDIO_D1_PA8 \ 991 GD32_PINMUX_AF('A', 8, AF12) 992 #define SDIO_D1_PB0 \ 993 GD32_PINMUX_AF('B', 0, AF12) 994 #define SDIO_D1_PC9 \ 995 GD32_PINMUX_AF('C', 9, AF12) 996 997 /* SDIO_D2 */ 998 #define SDIO_D2_PA9 \ 999 GD32_PINMUX_AF('A', 9, AF12) 1000 #define SDIO_D2_PB1 \ 1001 GD32_PINMUX_AF('B', 1, AF12) 1002 #define SDIO_D2_PC10 \ 1003 GD32_PINMUX_AF('C', 10, AF12) 1004 1005 /* SDIO_D3 */ 1006 #define SDIO_D3_PC11 \ 1007 GD32_PINMUX_AF('C', 11, AF12) 1008 1009 /* SDIO_D4 */ 1010 #define SDIO_D4_PB8 \ 1011 GD32_PINMUX_AF('B', 8, AF12) 1012 1013 /* SDIO_D5 */ 1014 #define SDIO_D5_PB9 \ 1015 GD32_PINMUX_AF('B', 9, AF12) 1016 1017 /* SDIO_D6 */ 1018 #define SDIO_D6_PC6 \ 1019 GD32_PINMUX_AF('C', 6, AF12) 1020 1021 /* SDIO_D7 */ 1022 #define SDIO_D7_PB10 \ 1023 GD32_PINMUX_AF('B', 10, AF12) 1024 #define SDIO_D7_PC7 \ 1025 GD32_PINMUX_AF('C', 7, AF12) 1026 1027 /* SPI0_MISO */ 1028 #define SPI0_MISO_PA6 \ 1029 GD32_PINMUX_AF('A', 6, AF5) 1030 #define SPI0_MISO_PB4 \ 1031 GD32_PINMUX_AF('B', 4, AF5) 1032 1033 /* SPI0_MOSI */ 1034 #define SPI0_MOSI_PA7 \ 1035 GD32_PINMUX_AF('A', 7, AF5) 1036 #define SPI0_MOSI_PB5 \ 1037 GD32_PINMUX_AF('B', 5, AF5) 1038 1039 /* SPI0_NSS */ 1040 #define SPI0_NSS_PA4 \ 1041 GD32_PINMUX_AF('A', 4, AF5) 1042 #define SPI0_NSS_PA15 \ 1043 GD32_PINMUX_AF('A', 15, AF5) 1044 1045 /* SPI0_SCK */ 1046 #define SPI0_SCK_PA5 \ 1047 GD32_PINMUX_AF('A', 5, AF5) 1048 #define SPI0_SCK_PB3 \ 1049 GD32_PINMUX_AF('B', 3, AF5) 1050 1051 /* SPI1_MISO */ 1052 #define SPI1_MISO_PB14 \ 1053 GD32_PINMUX_AF('B', 14, AF5) 1054 #define SPI1_MISO_PC2 \ 1055 GD32_PINMUX_AF('C', 2, AF5) 1056 1057 /* SPI1_MOSI */ 1058 #define SPI1_MOSI_PB15 \ 1059 GD32_PINMUX_AF('B', 15, AF5) 1060 #define SPI1_MOSI_PC1 \ 1061 GD32_PINMUX_AF('C', 1, AF7) 1062 #define SPI1_MOSI_PC3 \ 1063 GD32_PINMUX_AF('C', 3, AF5) 1064 1065 /* SPI1_NSS */ 1066 #define SPI1_NSS_PB9 \ 1067 GD32_PINMUX_AF('B', 9, AF5) 1068 #define SPI1_NSS_PB12 \ 1069 GD32_PINMUX_AF('B', 12, AF5) 1070 #define SPI1_NSS_PD1 \ 1071 GD32_PINMUX_AF('D', 1, AF7) 1072 1073 /* SPI1_SCK */ 1074 #define SPI1_SCK_PA9 \ 1075 GD32_PINMUX_AF('A', 9, AF5) 1076 #define SPI1_SCK_PB10 \ 1077 GD32_PINMUX_AF('B', 10, AF5) 1078 #define SPI1_SCK_PB13 \ 1079 GD32_PINMUX_AF('B', 13, AF5) 1080 #define SPI1_SCK_PC7 \ 1081 GD32_PINMUX_AF('C', 7, AF5) 1082 #define SPI1_SCK_PD3 \ 1083 GD32_PINMUX_AF('D', 3, AF5) 1084 1085 /* SPI2_MISO */ 1086 #define SPI2_MISO_PB4 \ 1087 GD32_PINMUX_AF('B', 4, AF6) 1088 #define SPI2_MISO_PC11 \ 1089 GD32_PINMUX_AF('C', 11, AF6) 1090 1091 /* SPI2_MOSI */ 1092 #define SPI2_MOSI_PB0 \ 1093 GD32_PINMUX_AF('B', 0, AF7) 1094 #define SPI2_MOSI_PB2 \ 1095 GD32_PINMUX_AF('B', 2, AF7) 1096 #define SPI2_MOSI_PB5 \ 1097 GD32_PINMUX_AF('B', 5, AF6) 1098 #define SPI2_MOSI_PC1 \ 1099 GD32_PINMUX_AF('C', 1, AF5) 1100 #define SPI2_MOSI_PC12 \ 1101 GD32_PINMUX_AF('C', 12, AF6) 1102 #define SPI2_MOSI_PD0 \ 1103 GD32_PINMUX_AF('D', 0, AF6) 1104 #define SPI2_MOSI_PD6 \ 1105 GD32_PINMUX_AF('D', 6, AF5) 1106 1107 /* SPI2_NSS */ 1108 #define SPI2_NSS_PA4 \ 1109 GD32_PINMUX_AF('A', 4, AF6) 1110 #define SPI2_NSS_PA15 \ 1111 GD32_PINMUX_AF('A', 15, AF6) 1112 1113 /* SPI2_SCK */ 1114 #define SPI2_SCK_PB3 \ 1115 GD32_PINMUX_AF('B', 3, AF6) 1116 #define SPI2_SCK_PC10 \ 1117 GD32_PINMUX_AF('C', 10, AF6) 1118 1119 /* SWCLK */ 1120 #define SWCLK_PA14 \ 1121 GD32_PINMUX_AF('A', 14, AF0) 1122 1123 /* SWDIO */ 1124 #define SWDIO_PA13 \ 1125 GD32_PINMUX_AF('A', 13, AF0) 1126 1127 /* TIMER0_BRKIN */ 1128 #define TIMER0_BRKIN_PA6 \ 1129 GD32_PINMUX_AF('A', 6, AF1) 1130 #define TIMER0_BRKIN_PB12 \ 1131 GD32_PINMUX_AF('B', 12, AF1) 1132 #define TIMER0_BRKIN_PE15 \ 1133 GD32_PINMUX_AF('E', 15, AF1) 1134 1135 /* TIMER0_CH0 */ 1136 #define TIMER0_CH0_PA8 \ 1137 GD32_PINMUX_AF('A', 8, AF1) 1138 #define TIMER0_CH0_PE9 \ 1139 GD32_PINMUX_AF('E', 9, AF0) 1140 1141 /* TIMER0_CH0_ON */ 1142 #define TIMER0_CH0_ON_PA7 \ 1143 GD32_PINMUX_AF('A', 7, AF1) 1144 #define TIMER0_CH0_ON_PB13 \ 1145 GD32_PINMUX_AF('B', 13, AF1) 1146 #define TIMER0_CH0_ON_PE8 \ 1147 GD32_PINMUX_AF('E', 8, AF1) 1148 1149 /* TIMER0_CH1 */ 1150 #define TIMER0_CH1_PA9 \ 1151 GD32_PINMUX_AF('A', 9, AF1) 1152 #define TIMER0_CH1_PE11 \ 1153 GD32_PINMUX_AF('E', 11, AF0) 1154 1155 /* TIMER0_CH1_ON */ 1156 #define TIMER0_CH1_ON_PB0 \ 1157 GD32_PINMUX_AF('B', 0, AF1) 1158 #define TIMER0_CH1_ON_PB14 \ 1159 GD32_PINMUX_AF('B', 14, AF1) 1160 #define TIMER0_CH1_ON_PE1 \ 1161 GD32_PINMUX_AF('E', 1, AF1) 1162 #define TIMER0_CH1_ON_PE10 \ 1163 GD32_PINMUX_AF('E', 10, AF1) 1164 1165 /* TIMER0_CH2 */ 1166 #define TIMER0_CH2_PA10 \ 1167 GD32_PINMUX_AF('A', 10, AF1) 1168 #define TIMER0_CH2_PE13 \ 1169 GD32_PINMUX_AF('E', 13, AF0) 1170 1171 /* TIMER0_CH2_ON */ 1172 #define TIMER0_CH2_ON_PB1 \ 1173 GD32_PINMUX_AF('B', 1, AF1) 1174 #define TIMER0_CH2_ON_PB15 \ 1175 GD32_PINMUX_AF('B', 15, AF1) 1176 #define TIMER0_CH2_ON_PE12 \ 1177 GD32_PINMUX_AF('E', 12, AF1) 1178 1179 /* TIMER0_CH3 */ 1180 #define TIMER0_CH3_PA11 \ 1181 GD32_PINMUX_AF('A', 11, AF1) 1182 #define TIMER0_CH3_PE14 \ 1183 GD32_PINMUX_AF('E', 14, AF0) 1184 1185 /* TIMER0_ETI */ 1186 #define TIMER0_ETI_PA12 \ 1187 GD32_PINMUX_AF('A', 12, AF1) 1188 #define TIMER0_ETI_PE7 \ 1189 GD32_PINMUX_AF('E', 7, AF0) 1190 1191 /* TIMER10_CH0 */ 1192 #define TIMER10_CH0_PB9 \ 1193 GD32_PINMUX_AF('B', 9, AF3) 1194 1195 /* TIMER11_CH0 */ 1196 #define TIMER11_CH0_PB14 \ 1197 GD32_PINMUX_AF('B', 14, AF9) 1198 1199 /* TIMER11_CH1 */ 1200 #define TIMER11_CH1_PB15 \ 1201 GD32_PINMUX_AF('B', 15, AF9) 1202 1203 /* TIMER12_CH0 */ 1204 #define TIMER12_CH0_PA6 \ 1205 GD32_PINMUX_AF('A', 6, AF9) 1206 1207 /* TIMER13_CH0 */ 1208 #define TIMER13_CH0_PA7 \ 1209 GD32_PINMUX_AF('A', 7, AF9) 1210 1211 /* TIMER1_CH0 */ 1212 #define TIMER1_CH0_PA0 \ 1213 GD32_PINMUX_AF('A', 0, AF1) 1214 #define TIMER1_CH0_PA5 \ 1215 GD32_PINMUX_AF('A', 5, AF1) 1216 #define TIMER1_CH0_PA15 \ 1217 GD32_PINMUX_AF('A', 15, AF1) 1218 #define TIMER1_CH0_PB8 \ 1219 GD32_PINMUX_AF('B', 8, AF1) 1220 1221 /* TIMER1_CH1 */ 1222 #define TIMER1_CH1_PA1 \ 1223 GD32_PINMUX_AF('A', 1, AF1) 1224 #define TIMER1_CH1_PB3 \ 1225 GD32_PINMUX_AF('B', 3, AF1) 1226 #define TIMER1_CH1_PB9 \ 1227 GD32_PINMUX_AF('B', 9, AF1) 1228 1229 /* TIMER1_CH2 */ 1230 #define TIMER1_CH2_PA2 \ 1231 GD32_PINMUX_AF('A', 2, AF1) 1232 #define TIMER1_CH2_PB10 \ 1233 GD32_PINMUX_AF('B', 10, AF1) 1234 1235 /* TIMER1_CH3 */ 1236 #define TIMER1_CH3_PA3 \ 1237 GD32_PINMUX_AF('A', 3, AF1) 1238 #define TIMER1_CH3_PB2 \ 1239 GD32_PINMUX_AF('B', 2, AF1) 1240 #define TIMER1_CH3_PB11 \ 1241 GD32_PINMUX_AF('B', 11, AF1) 1242 1243 /* TIMER1_ETI */ 1244 #define TIMER1_ETI_PA0 \ 1245 GD32_PINMUX_AF('A', 0, AF1) 1246 #define TIMER1_ETI_PA5 \ 1247 GD32_PINMUX_AF('A', 5, AF1) 1248 #define TIMER1_ETI_PA15 \ 1249 GD32_PINMUX_AF('A', 15, AF1) 1250 #define TIMER1_ETI_PB8 \ 1251 GD32_PINMUX_AF('B', 8, AF1) 1252 1253 /* TIMER2_CH0 */ 1254 #define TIMER2_CH0_PA6 \ 1255 GD32_PINMUX_AF('A', 6, AF2) 1256 #define TIMER2_CH0_PB4 \ 1257 GD32_PINMUX_AF('B', 4, AF2) 1258 #define TIMER2_CH0_PC6 \ 1259 GD32_PINMUX_AF('C', 6, AF2) 1260 1261 /* TIMER2_CH1 */ 1262 #define TIMER2_CH1_PA7 \ 1263 GD32_PINMUX_AF('A', 7, AF2) 1264 #define TIMER2_CH1_PB5 \ 1265 GD32_PINMUX_AF('B', 5, AF2) 1266 #define TIMER2_CH1_PC7 \ 1267 GD32_PINMUX_AF('C', 7, AF2) 1268 1269 /* TIMER2_CH2 */ 1270 #define TIMER2_CH2_PB0 \ 1271 GD32_PINMUX_AF('B', 0, AF2) 1272 #define TIMER2_CH2_PC8 \ 1273 GD32_PINMUX_AF('C', 8, AF2) 1274 1275 /* TIMER2_CH3 */ 1276 #define TIMER2_CH3_PB1 \ 1277 GD32_PINMUX_AF('B', 1, AF2) 1278 #define TIMER2_CH3_PC9 \ 1279 GD32_PINMUX_AF('C', 9, AF2) 1280 1281 /* TIMER2_ETI */ 1282 #define TIMER2_ETI_PD2 \ 1283 GD32_PINMUX_AF('D', 2, AF2) 1284 1285 /* TIMER3_CH0 */ 1286 #define TIMER3_CH0_PB6 \ 1287 GD32_PINMUX_AF('B', 6, AF2) 1288 #define TIMER3_CH0_PD12 \ 1289 GD32_PINMUX_AF('D', 12, AF2) 1290 1291 /* TIMER3_CH1 */ 1292 #define TIMER3_CH1_PB7 \ 1293 GD32_PINMUX_AF('B', 7, AF2) 1294 #define TIMER3_CH1_PD13 \ 1295 GD32_PINMUX_AF('D', 13, AF2) 1296 1297 /* TIMER3_CH2 */ 1298 #define TIMER3_CH2_PB8 \ 1299 GD32_PINMUX_AF('B', 8, AF2) 1300 #define TIMER3_CH2_PD14 \ 1301 GD32_PINMUX_AF('D', 14, AF2) 1302 1303 /* TIMER3_CH3 */ 1304 #define TIMER3_CH3_PB9 \ 1305 GD32_PINMUX_AF('B', 9, AF2) 1306 #define TIMER3_CH3_PD15 \ 1307 GD32_PINMUX_AF('D', 15, AF2) 1308 1309 /* TIMER3_ETI */ 1310 #define TIMER3_ETI_PE0 \ 1311 GD32_PINMUX_AF('E', 0, AF2) 1312 1313 /* TIMER4_CH0 */ 1314 #define TIMER4_CH0_PA0 \ 1315 GD32_PINMUX_AF('A', 0, AF2) 1316 1317 /* TIMER4_CH1 */ 1318 #define TIMER4_CH1_PA1 \ 1319 GD32_PINMUX_AF('A', 1, AF2) 1320 1321 /* TIMER4_CH2 */ 1322 #define TIMER4_CH2_PA2 \ 1323 GD32_PINMUX_AF('A', 2, AF2) 1324 1325 /* TIMER4_CH3 */ 1326 #define TIMER4_CH3_PA3 \ 1327 GD32_PINMUX_AF('A', 3, AF2) 1328 1329 /* TIMER7_BRKIN */ 1330 #define TIMER7_BRKIN_PA6 \ 1331 GD32_PINMUX_AF('A', 6, AF3) 1332 1333 /* TIMER7_CH0 */ 1334 #define TIMER7_CH0_PC6 \ 1335 GD32_PINMUX_AF('C', 6, AF3) 1336 1337 /* TIMER7_CH0_ON */ 1338 #define TIMER7_CH0_ON_PA5 \ 1339 GD32_PINMUX_AF('A', 5, AF3) 1340 #define TIMER7_CH0_ON_PA7 \ 1341 GD32_PINMUX_AF('A', 7, AF3) 1342 1343 /* TIMER7_CH1 */ 1344 #define TIMER7_CH1_PC7 \ 1345 GD32_PINMUX_AF('C', 7, AF3) 1346 1347 /* TIMER7_CH1_ON */ 1348 #define TIMER7_CH1_ON_PB0 \ 1349 GD32_PINMUX_AF('B', 0, AF3) 1350 #define TIMER7_CH1_ON_PB14 \ 1351 GD32_PINMUX_AF('B', 14, AF3) 1352 1353 /* TIMER7_CH2 */ 1354 #define TIMER7_CH2_PC8 \ 1355 GD32_PINMUX_AF('C', 8, AF3) 1356 1357 /* TIMER7_CH2_ON */ 1358 #define TIMER7_CH2_ON_PB1 \ 1359 GD32_PINMUX_AF('B', 1, AF3) 1360 #define TIMER7_CH2_ON_PB15 \ 1361 GD32_PINMUX_AF('B', 15, AF3) 1362 1363 /* TIMER7_CH3 */ 1364 #define TIMER7_CH3_PC9 \ 1365 GD32_PINMUX_AF('C', 9, AF3) 1366 1367 /* TIMER7_ETI */ 1368 #define TIMER7_ETI_PA0 \ 1369 GD32_PINMUX_AF('A', 0, AF3) 1370 1371 /* TIMER8_CH0 */ 1372 #define TIMER8_CH0_PA2 \ 1373 GD32_PINMUX_AF('A', 2, AF3) 1374 #define TIMER8_CH0_PE5 \ 1375 GD32_PINMUX_AF('E', 5, AF3) 1376 1377 /* TIMER8_CH1 */ 1378 #define TIMER8_CH1_PA3 \ 1379 GD32_PINMUX_AF('A', 3, AF3) 1380 #define TIMER8_CH1_PE6 \ 1381 GD32_PINMUX_AF('E', 6, AF3) 1382 1383 /* TIMER9_CH0 */ 1384 #define TIMER9_CH0_PB8 \ 1385 GD32_PINMUX_AF('B', 8, AF3) 1386 1387 /* TRACECK */ 1388 #define TRACECK_PE2 \ 1389 GD32_PINMUX_AF('E', 2, AF0) 1390 1391 /* TRACED0 */ 1392 #define TRACED0_PC8 \ 1393 GD32_PINMUX_AF('C', 8, AF0) 1394 #define TRACED0_PE3 \ 1395 GD32_PINMUX_AF('E', 3, AF0) 1396 1397 /* TRACED1 */ 1398 #define TRACED1_PD3 \ 1399 GD32_PINMUX_AF('D', 3, AF0) 1400 #define TRACED1_PE4 \ 1401 GD32_PINMUX_AF('E', 4, AF0) 1402 1403 /* TRACED2 */ 1404 #define TRACED2_PE5 \ 1405 GD32_PINMUX_AF('E', 5, AF0) 1406 1407 /* TRACED3 */ 1408 #define TRACED3_PE6 \ 1409 GD32_PINMUX_AF('E', 6, AF0) 1410 1411 /* TRACESWO */ 1412 #define TRACESWO_PB3 \ 1413 GD32_PINMUX_AF('B', 3, AF0) 1414 1415 /* UART3_RX */ 1416 #define UART3_RX_PA1 \ 1417 GD32_PINMUX_AF('A', 1, AF8) 1418 #define UART3_RX_PC11 \ 1419 GD32_PINMUX_AF('C', 11, AF8) 1420 1421 /* UART3_TX */ 1422 #define UART3_TX_PA0 \ 1423 GD32_PINMUX_AF('A', 0, AF8) 1424 #define UART3_TX_PC10 \ 1425 GD32_PINMUX_AF('C', 10, AF8) 1426 1427 /* UART4_RX */ 1428 #define UART4_RX_PD2 \ 1429 GD32_PINMUX_AF('D', 2, AF8) 1430 1431 /* UART4_TX */ 1432 #define UART4_TX_PC12 \ 1433 GD32_PINMUX_AF('C', 12, AF8) 1434 1435 /* USART0_CK */ 1436 #define USART0_CK_PA8 \ 1437 GD32_PINMUX_AF('A', 8, AF7) 1438 1439 /* USART0_CTS */ 1440 #define USART0_CTS_PA11 \ 1441 GD32_PINMUX_AF('A', 11, AF7) 1442 1443 /* USART0_RTS */ 1444 #define USART0_RTS_PA12 \ 1445 GD32_PINMUX_AF('A', 12, AF7) 1446 1447 /* USART0_RX */ 1448 #define USART0_RX_PA10 \ 1449 GD32_PINMUX_AF('A', 10, AF7) 1450 #define USART0_RX_PB3 \ 1451 GD32_PINMUX_AF('B', 3, AF7) 1452 #define USART0_RX_PB7 \ 1453 GD32_PINMUX_AF('B', 7, AF7) 1454 1455 /* USART0_TX */ 1456 #define USART0_TX_PA9 \ 1457 GD32_PINMUX_AF('A', 9, AF7) 1458 #define USART0_TX_PA15 \ 1459 GD32_PINMUX_AF('A', 15, AF7) 1460 #define USART0_TX_PB6 \ 1461 GD32_PINMUX_AF('B', 6, AF7) 1462 1463 /* USART1_CK */ 1464 #define USART1_CK_PA4 \ 1465 GD32_PINMUX_AF('A', 4, AF7) 1466 #define USART1_CK_PD7 \ 1467 GD32_PINMUX_AF('D', 7, AF7) 1468 1469 /* USART1_CTS */ 1470 #define USART1_CTS_PA0 \ 1471 GD32_PINMUX_AF('A', 0, AF7) 1472 #define USART1_CTS_PD3 \ 1473 GD32_PINMUX_AF('D', 3, AF7) 1474 1475 /* USART1_RTS */ 1476 #define USART1_RTS_PA1 \ 1477 GD32_PINMUX_AF('A', 1, AF7) 1478 #define USART1_RTS_PD4 \ 1479 GD32_PINMUX_AF('D', 4, AF7) 1480 1481 /* USART1_RX */ 1482 #define USART1_RX_PA3 \ 1483 GD32_PINMUX_AF('A', 3, AF7) 1484 #define USART1_RX_PD6 \ 1485 GD32_PINMUX_AF('D', 6, AF7) 1486 1487 /* USART1_TX */ 1488 #define USART1_TX_PA2 \ 1489 GD32_PINMUX_AF('A', 2, AF7) 1490 #define USART1_TX_PD5 \ 1491 GD32_PINMUX_AF('D', 5, AF7) 1492 1493 /* USART2_CK */ 1494 #define USART2_CK_PB12 \ 1495 GD32_PINMUX_AF('B', 12, AF7) 1496 #define USART2_CK_PC12 \ 1497 GD32_PINMUX_AF('C', 12, AF7) 1498 #define USART2_CK_PD10 \ 1499 GD32_PINMUX_AF('D', 10, AF7) 1500 1501 /* USART2_CTS */ 1502 #define USART2_CTS_PB13 \ 1503 GD32_PINMUX_AF('B', 13, AF7) 1504 #define USART2_CTS_PD11 \ 1505 GD32_PINMUX_AF('D', 11, AF7) 1506 1507 /* USART2_RTS */ 1508 #define USART2_RTS_PB14 \ 1509 GD32_PINMUX_AF('B', 14, AF7) 1510 #define USART2_RTS_PD12 \ 1511 GD32_PINMUX_AF('D', 12, AF7) 1512 1513 /* USART2_RX */ 1514 #define USART2_RX_PB11 \ 1515 GD32_PINMUX_AF('B', 11, AF7) 1516 #define USART2_RX_PC5 \ 1517 GD32_PINMUX_AF('C', 5, AF7) 1518 #define USART2_RX_PC11 \ 1519 GD32_PINMUX_AF('C', 11, AF7) 1520 #define USART2_RX_PD9 \ 1521 GD32_PINMUX_AF('D', 9, AF7) 1522 1523 /* USART2_TX */ 1524 #define USART2_TX_PB10 \ 1525 GD32_PINMUX_AF('B', 10, AF7) 1526 #define USART2_TX_PC10 \ 1527 GD32_PINMUX_AF('C', 10, AF7) 1528 #define USART2_TX_PD8 \ 1529 GD32_PINMUX_AF('D', 8, AF7) 1530 1531 /* USART5_CK */ 1532 #define USART5_CK_PC8 \ 1533 GD32_PINMUX_AF('C', 8, AF8) 1534 1535 /* USART5_RX */ 1536 #define USART5_RX_PA12 \ 1537 GD32_PINMUX_AF('A', 12, AF8) 1538 #define USART5_RX_PC7 \ 1539 GD32_PINMUX_AF('C', 7, AF8) 1540 1541 /* USART5_TX */ 1542 #define USART5_TX_PA11 \ 1543 GD32_PINMUX_AF('A', 11, AF8) 1544 #define USART5_TX_PC6 \ 1545 GD32_PINMUX_AF('C', 6, AF8) 1546 1547 /* USBFS_DM */ 1548 #define USBFS_DM_PA11 \ 1549 GD32_PINMUX_AF('A', 11, AF10) 1550 1551 /* USBFS_DP */ 1552 #define USBFS_DP_PA12 \ 1553 GD32_PINMUX_AF('A', 12, AF10) 1554 1555 /* USBFS_ID */ 1556 #define USBFS_ID_PA10 \ 1557 GD32_PINMUX_AF('A', 10, AF10) 1558 1559 /* USBFS_SOF */ 1560 #define USBFS_SOF_PA8 \ 1561 GD32_PINMUX_AF('A', 8, AF10) 1562 1563 /* USBHS_DM */ 1564 #define USBHS_DM_PB14 \ 1565 GD32_PINMUX_AF('B', 14, AF12) 1566 1567 /* USBHS_DP */ 1568 #define USBHS_DP_PB15 \ 1569 GD32_PINMUX_AF('B', 15, AF12) 1570 1571 /* USBHS_ID */ 1572 #define USBHS_ID_PB12 \ 1573 GD32_PINMUX_AF('B', 12, AF12) 1574 1575 /* USBHS_SOF */ 1576 #define USBHS_SOF_PA4 \ 1577 GD32_PINMUX_AF('A', 4, AF12) 1578 1579 /* USBHS_ULPI_CK */ 1580 #define USBHS_ULPI_CK_PA5 \ 1581 GD32_PINMUX_AF('A', 5, AF10) 1582 1583 /* USBHS_ULPI_D0 */ 1584 #define USBHS_ULPI_D0_PA3 \ 1585 GD32_PINMUX_AF('A', 3, AF10) 1586 1587 /* USBHS_ULPI_D1 */ 1588 #define USBHS_ULPI_D1_PB0 \ 1589 GD32_PINMUX_AF('B', 0, AF10) 1590 1591 /* USBHS_ULPI_D2 */ 1592 #define USBHS_ULPI_D2_PB1 \ 1593 GD32_PINMUX_AF('B', 1, AF10) 1594 1595 /* USBHS_ULPI_D3 */ 1596 #define USBHS_ULPI_D3_PB10 \ 1597 GD32_PINMUX_AF('B', 10, AF10) 1598 1599 /* USBHS_ULPI_D4 */ 1600 #define USBHS_ULPI_D4_PB2 \ 1601 GD32_PINMUX_AF('B', 2, AF10) 1602 #define USBHS_ULPI_D4_PB11 \ 1603 GD32_PINMUX_AF('B', 11, AF10) 1604 1605 /* USBHS_ULPI_D5 */ 1606 #define USBHS_ULPI_D5_PB12 \ 1607 GD32_PINMUX_AF('B', 12, AF10) 1608 1609 /* USBHS_ULPI_D6 */ 1610 #define USBHS_ULPI_D6_PB13 \ 1611 GD32_PINMUX_AF('B', 13, AF10) 1612 1613 /* USBHS_ULPI_D7 */ 1614 #define USBHS_ULPI_D7_PB5 \ 1615 GD32_PINMUX_AF('B', 5, AF10) 1616 1617 /* USBHS_ULPI_DIR */ 1618 #define USBHS_ULPI_DIR_PC2 \ 1619 GD32_PINMUX_AF('C', 2, AF10) 1620 1621 /* USBHS_ULPI_NXT */ 1622 #define USBHS_ULPI_NXT_PC3 \ 1623 GD32_PINMUX_AF('C', 3, AF10) 1624 1625 /* USBHS_ULPI_STP */ 1626 #define USBHS_ULPI_STP_PC0 \ 1627 GD32_PINMUX_AF('C', 0, AF10) 1628
