1 /*
2  * Autogenerated file
3  *
4  * SPDX-License-Identifier: Apache 2.0
5  */
6 
7 #include "gd32f403xx-afio.h"
8 
9 /* ADC012_IN0 */
10 #define ADC012_IN0_PA0 \
11 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
12 
13 /* ADC012_IN1 */
14 #define ADC012_IN1_PA1 \
15 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
16 
17 /* ADC012_IN13 */
18 #define ADC012_IN13_PC3 \
19 	GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP)
20 
21 /* ADC012_IN2 */
22 #define ADC012_IN2_PA2 \
23 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
24 
25 /* ADC012_IN3 */
26 #define ADC012_IN3_PA3 \
27 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
28 
29 /* ADC01_IN4 */
30 #define ADC01_IN4_PA4 \
31 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
32 
33 /* ADC01_IN5 */
34 #define ADC01_IN5_PA5 \
35 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
36 
37 /* ADC01_IN6 */
38 #define ADC01_IN6_PA6 \
39 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
40 
41 /* ADC01_IN7 */
42 #define ADC01_IN7_PA7 \
43 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
44 
45 /* ADC01_IN8 */
46 #define ADC01_IN8_PB0 \
47 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
48 
49 /* ADC01_IN9 */
50 #define ADC01_IN9_PB1 \
51 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
52 
53 /* ANALOG */
54 #define ANALOG_PA0 \
55 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
56 #define ANALOG_PA1 \
57 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
58 #define ANALOG_PA2 \
59 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
60 #define ANALOG_PA3 \
61 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
62 #define ANALOG_PA4 \
63 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
64 #define ANALOG_PA5 \
65 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
66 #define ANALOG_PA6 \
67 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
68 #define ANALOG_PA7 \
69 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
70 #define ANALOG_PA8 \
71 	GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP)
72 #define ANALOG_PA9 \
73 	GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP)
74 #define ANALOG_PA10 \
75 	GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP)
76 #define ANALOG_PA11 \
77 	GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP)
78 #define ANALOG_PA12 \
79 	GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP)
80 #define ANALOG_PA13 \
81 	GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP)
82 #define ANALOG_PA14 \
83 	GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP)
84 #define ANALOG_PA15 \
85 	GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP)
86 #define ANALOG_PB0 \
87 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
88 #define ANALOG_PB1 \
89 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
90 #define ANALOG_PB2 \
91 	GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP)
92 #define ANALOG_PB3 \
93 	GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP)
94 #define ANALOG_PB4 \
95 	GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP)
96 #define ANALOG_PB5 \
97 	GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP)
98 #define ANALOG_PB6 \
99 	GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP)
100 #define ANALOG_PB7 \
101 	GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP)
102 #define ANALOG_PC3 \
103 	GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP)
104 #define ANALOG_PD0 \
105 	GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP)
106 #define ANALOG_PD1 \
107 	GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP)
108 #define ANALOG_PD2 \
109 	GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP)
110 #define ANALOG_PD3 \
111 	GD32_PINMUX_AFIO('D', 3, ANALOG, NORMP)
112 #define ANALOG_PD4 \
113 	GD32_PINMUX_AFIO('D', 4, ANALOG, NORMP)
114 #define ANALOG_PD5 \
115 	GD32_PINMUX_AFIO('D', 5, ANALOG, NORMP)
116 #define ANALOG_PD6 \
117 	GD32_PINMUX_AFIO('D', 6, ANALOG, NORMP)
118 #define ANALOG_PD7 \
119 	GD32_PINMUX_AFIO('D', 7, ANALOG, NORMP)
120 #define ANALOG_PD8 \
121 	GD32_PINMUX_AFIO('D', 8, ANALOG, NORMP)
122 #define ANALOG_PD9 \
123 	GD32_PINMUX_AFIO('D', 9, ANALOG, NORMP)
124 #define ANALOG_PD10 \
125 	GD32_PINMUX_AFIO('D', 10, ANALOG, NORMP)
126 #define ANALOG_PD11 \
127 	GD32_PINMUX_AFIO('D', 11, ANALOG, NORMP)
128 #define ANALOG_PD12 \
129 	GD32_PINMUX_AFIO('D', 12, ANALOG, NORMP)
130 #define ANALOG_PD13 \
131 	GD32_PINMUX_AFIO('D', 13, ANALOG, NORMP)
132 #define ANALOG_PD14 \
133 	GD32_PINMUX_AFIO('D', 14, ANALOG, NORMP)
134 #define ANALOG_PD15 \
135 	GD32_PINMUX_AFIO('D', 15, ANALOG, NORMP)
136 #define ANALOG_PE0 \
137 	GD32_PINMUX_AFIO('E', 0, ANALOG, NORMP)
138 #define ANALOG_PE1 \
139 	GD32_PINMUX_AFIO('E', 1, ANALOG, NORMP)
140 #define ANALOG_PE2 \
141 	GD32_PINMUX_AFIO('E', 2, ANALOG, NORMP)
142 #define ANALOG_PE3 \
143 	GD32_PINMUX_AFIO('E', 3, ANALOG, NORMP)
144 #define ANALOG_PE4 \
145 	GD32_PINMUX_AFIO('E', 4, ANALOG, NORMP)
146 #define ANALOG_PE5 \
147 	GD32_PINMUX_AFIO('E', 5, ANALOG, NORMP)
148 #define ANALOG_PE6 \
149 	GD32_PINMUX_AFIO('E', 6, ANALOG, NORMP)
150 #define ANALOG_PE7 \
151 	GD32_PINMUX_AFIO('E', 7, ANALOG, NORMP)
152 #define ANALOG_PE8 \
153 	GD32_PINMUX_AFIO('E', 8, ANALOG, NORMP)
154 #define ANALOG_PE9 \
155 	GD32_PINMUX_AFIO('E', 9, ANALOG, NORMP)
156 #define ANALOG_PE10 \
157 	GD32_PINMUX_AFIO('E', 10, ANALOG, NORMP)
158 #define ANALOG_PE11 \
159 	GD32_PINMUX_AFIO('E', 11, ANALOG, NORMP)
160 #define ANALOG_PE12 \
161 	GD32_PINMUX_AFIO('E', 12, ANALOG, NORMP)
162 #define ANALOG_PE13 \
163 	GD32_PINMUX_AFIO('E', 13, ANALOG, NORMP)
164 #define ANALOG_PE14 \
165 	GD32_PINMUX_AFIO('E', 14, ANALOG, NORMP)
166 #define ANALOG_PE15 \
167 	GD32_PINMUX_AFIO('E', 15, ANALOG, NORMP)
168 #define ANALOG_PF0 \
169 	GD32_PINMUX_AFIO('F', 0, ANALOG, NORMP)
170 #define ANALOG_PF1 \
171 	GD32_PINMUX_AFIO('F', 1, ANALOG, NORMP)
172 #define ANALOG_PF2 \
173 	GD32_PINMUX_AFIO('F', 2, ANALOG, NORMP)
174 #define ANALOG_PF3 \
175 	GD32_PINMUX_AFIO('F', 3, ANALOG, NORMP)
176 #define ANALOG_PF4 \
177 	GD32_PINMUX_AFIO('F', 4, ANALOG, NORMP)
178 #define ANALOG_PF5 \
179 	GD32_PINMUX_AFIO('F', 5, ANALOG, NORMP)
180 #define ANALOG_PF6 \
181 	GD32_PINMUX_AFIO('F', 6, ANALOG, NORMP)
182 #define ANALOG_PF7 \
183 	GD32_PINMUX_AFIO('F', 7, ANALOG, NORMP)
184 #define ANALOG_PF8 \
185 	GD32_PINMUX_AFIO('F', 8, ANALOG, NORMP)
186 #define ANALOG_PF9 \
187 	GD32_PINMUX_AFIO('F', 9, ANALOG, NORMP)
188 #define ANALOG_PF10 \
189 	GD32_PINMUX_AFIO('F', 10, ANALOG, NORMP)
190 #define ANALOG_PF11 \
191 	GD32_PINMUX_AFIO('F', 11, ANALOG, NORMP)
192 #define ANALOG_PF12 \
193 	GD32_PINMUX_AFIO('F', 12, ANALOG, NORMP)
194 #define ANALOG_PF13 \
195 	GD32_PINMUX_AFIO('F', 13, ANALOG, NORMP)
196 #define ANALOG_PF14 \
197 	GD32_PINMUX_AFIO('F', 14, ANALOG, NORMP)
198 #define ANALOG_PF15 \
199 	GD32_PINMUX_AFIO('F', 15, ANALOG, NORMP)
200 #define ANALOG_PG0 \
201 	GD32_PINMUX_AFIO('G', 0, ANALOG, NORMP)
202 #define ANALOG_PG1 \
203 	GD32_PINMUX_AFIO('G', 1, ANALOG, NORMP)
204 #define ANALOG_PG2 \
205 	GD32_PINMUX_AFIO('G', 2, ANALOG, NORMP)
206 #define ANALOG_PG3 \
207 	GD32_PINMUX_AFIO('G', 3, ANALOG, NORMP)
208 #define ANALOG_PG4 \
209 	GD32_PINMUX_AFIO('G', 4, ANALOG, NORMP)
210 #define ANALOG_PG5 \
211 	GD32_PINMUX_AFIO('G', 5, ANALOG, NORMP)
212 #define ANALOG_PG6 \
213 	GD32_PINMUX_AFIO('G', 6, ANALOG, NORMP)
214 #define ANALOG_PG7 \
215 	GD32_PINMUX_AFIO('G', 7, ANALOG, NORMP)
216 #define ANALOG_PG8 \
217 	GD32_PINMUX_AFIO('G', 8, ANALOG, NORMP)
218 #define ANALOG_PG9 \
219 	GD32_PINMUX_AFIO('G', 9, ANALOG, NORMP)
220 #define ANALOG_PG10 \
221 	GD32_PINMUX_AFIO('G', 10, ANALOG, NORMP)
222 #define ANALOG_PG11 \
223 	GD32_PINMUX_AFIO('G', 11, ANALOG, NORMP)
224 #define ANALOG_PG12 \
225 	GD32_PINMUX_AFIO('G', 12, ANALOG, NORMP)
226 #define ANALOG_PG13 \
227 	GD32_PINMUX_AFIO('G', 13, ANALOG, NORMP)
228 #define ANALOG_PG14 \
229 	GD32_PINMUX_AFIO('G', 14, ANALOG, NORMP)
230 #define ANALOG_PG15 \
231 	GD32_PINMUX_AFIO('G', 15, ANALOG, NORMP)
232 
233 /* CAN0_RX */
234 #define CAN0_RX_PA11_NORMP \
235 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, CAN0_NORMP)
236 #define CAN0_RX_PD0_FRMP \
237 	GD32_PINMUX_AFIO('D', 0, GPIO_IN, CAN0_FRMP)
238 
239 /* CAN0_TX */
240 #define CAN0_TX_PA12_NORMP \
241 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, CAN0_NORMP)
242 #define CAN0_TX_PD1_FRMP \
243 	GD32_PINMUX_AFIO('D', 1, ALTERNATE, CAN0_FRMP)
244 
245 /* CAN1_RX */
246 #define CAN1_RX_PB5_RMP \
247 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, CAN1_RMP)
248 
249 /* CAN1_TX */
250 #define CAN1_TX_PB6_RMP \
251 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, CAN1_RMP)
252 
253 /* CK_OUT0 */
254 #define CK_OUT0_PA8 \
255 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
256 
257 /* CTC_SYNC */
258 #define CTC_SYNC_PA8_NORMP \
259 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, CTC_NORMP)
260 #define CTC_SYNC_PD15_PRMP \
261 	GD32_PINMUX_AFIO('D', 15, ALTERNATE, CTC_PRMP)
262 #define CTC_SYNC_PF0_FRMP \
263 	GD32_PINMUX_AFIO('F', 0, ALTERNATE, CTC_FRMP)
264 
265 /* DAC_OUT0 */
266 #define DAC_OUT0_PA4 \
267 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
268 
269 /* DAC_OUT1 */
270 #define DAC_OUT1_PA5 \
271 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
272 
273 /* EXMC_A0 */
274 #define EXMC_A0_PF0 \
275 	GD32_PINMUX_AFIO('F', 0, ALTERNATE, NORMP)
276 
277 /* EXMC_A1 */
278 #define EXMC_A1_PF1 \
279 	GD32_PINMUX_AFIO('F', 1, ALTERNATE, NORMP)
280 
281 /* EXMC_A10 */
282 #define EXMC_A10_PG0 \
283 	GD32_PINMUX_AFIO('G', 0, ALTERNATE, NORMP)
284 
285 /* EXMC_A11 */
286 #define EXMC_A11_PG1 \
287 	GD32_PINMUX_AFIO('G', 1, ALTERNATE, NORMP)
288 
289 /* EXMC_A12 */
290 #define EXMC_A12_PG2 \
291 	GD32_PINMUX_AFIO('G', 2, ALTERNATE, NORMP)
292 
293 /* EXMC_A13 */
294 #define EXMC_A13_PG3 \
295 	GD32_PINMUX_AFIO('G', 3, ALTERNATE, NORMP)
296 
297 /* EXMC_A14 */
298 #define EXMC_A14_PG4 \
299 	GD32_PINMUX_AFIO('G', 4, ALTERNATE, NORMP)
300 
301 /* EXMC_A15 */
302 #define EXMC_A15_PG5 \
303 	GD32_PINMUX_AFIO('G', 5, ALTERNATE, NORMP)
304 
305 /* EXMC_A16 */
306 #define EXMC_A16_PD11 \
307 	GD32_PINMUX_AFIO('D', 11, ALTERNATE, NORMP)
308 
309 /* EXMC_A17 */
310 #define EXMC_A17_PD12 \
311 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, NORMP)
312 
313 /* EXMC_A18 */
314 #define EXMC_A18_PD13 \
315 	GD32_PINMUX_AFIO('D', 13, ALTERNATE, NORMP)
316 
317 /* EXMC_A19 */
318 #define EXMC_A19_PE3 \
319 	GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP)
320 
321 /* EXMC_A2 */
322 #define EXMC_A2_PF2 \
323 	GD32_PINMUX_AFIO('F', 2, ALTERNATE, NORMP)
324 
325 /* EXMC_A20 */
326 #define EXMC_A20_PE4 \
327 	GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP)
328 
329 /* EXMC_A21 */
330 #define EXMC_A21_PE5 \
331 	GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP)
332 
333 /* EXMC_A22 */
334 #define EXMC_A22_PE6 \
335 	GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP)
336 
337 /* EXMC_A23 */
338 #define EXMC_A23_PE2 \
339 	GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP)
340 
341 /* EXMC_A24 */
342 #define EXMC_A24_PG13 \
343 	GD32_PINMUX_AFIO('G', 13, ALTERNATE, NORMP)
344 
345 /* EXMC_A25 */
346 #define EXMC_A25_PG14 \
347 	GD32_PINMUX_AFIO('G', 14, ALTERNATE, NORMP)
348 
349 /* EXMC_A3 */
350 #define EXMC_A3_PF3 \
351 	GD32_PINMUX_AFIO('F', 3, ALTERNATE, NORMP)
352 
353 /* EXMC_A4 */
354 #define EXMC_A4_PF4 \
355 	GD32_PINMUX_AFIO('F', 4, ALTERNATE, NORMP)
356 
357 /* EXMC_A5 */
358 #define EXMC_A5_PF5 \
359 	GD32_PINMUX_AFIO('F', 5, ALTERNATE, NORMP)
360 
361 /* EXMC_A6 */
362 #define EXMC_A6_PF12 \
363 	GD32_PINMUX_AFIO('F', 12, ALTERNATE, NORMP)
364 
365 /* EXMC_A7 */
366 #define EXMC_A7_PF13 \
367 	GD32_PINMUX_AFIO('F', 13, ALTERNATE, NORMP)
368 
369 /* EXMC_A8 */
370 #define EXMC_A8_PF14 \
371 	GD32_PINMUX_AFIO('F', 14, ALTERNATE, NORMP)
372 
373 /* EXMC_A9 */
374 #define EXMC_A9_PF15 \
375 	GD32_PINMUX_AFIO('F', 15, ALTERNATE, NORMP)
376 
377 /* EXMC_CD */
378 #define EXMC_CD_PF9 \
379 	GD32_PINMUX_AFIO('F', 9, GPIO_IN, NORMP)
380 
381 /* EXMC_CLK */
382 #define EXMC_CLK_PD3 \
383 	GD32_PINMUX_AFIO('D', 3, ALTERNATE, NORMP)
384 
385 /* EXMC_D0 */
386 #define EXMC_D0_PD14 \
387 	GD32_PINMUX_AFIO('D', 14, ALTERNATE, NORMP)
388 
389 /* EXMC_D1 */
390 #define EXMC_D1_PD15 \
391 	GD32_PINMUX_AFIO('D', 15, ALTERNATE, NORMP)
392 
393 /* EXMC_D10 */
394 #define EXMC_D10_PE13 \
395 	GD32_PINMUX_AFIO('E', 13, ALTERNATE, NORMP)
396 
397 /* EXMC_D11 */
398 #define EXMC_D11_PE14 \
399 	GD32_PINMUX_AFIO('E', 14, ALTERNATE, NORMP)
400 
401 /* EXMC_D12 */
402 #define EXMC_D12_PE15 \
403 	GD32_PINMUX_AFIO('E', 15, ALTERNATE, NORMP)
404 
405 /* EXMC_D13 */
406 #define EXMC_D13_PD8 \
407 	GD32_PINMUX_AFIO('D', 8, ALTERNATE, NORMP)
408 
409 /* EXMC_D14 */
410 #define EXMC_D14_PD9 \
411 	GD32_PINMUX_AFIO('D', 9, ALTERNATE, NORMP)
412 
413 /* EXMC_D15 */
414 #define EXMC_D15_PD10 \
415 	GD32_PINMUX_AFIO('D', 10, ALTERNATE, NORMP)
416 
417 /* EXMC_D2 */
418 #define EXMC_D2_PD0 \
419 	GD32_PINMUX_AFIO('D', 0, ALTERNATE, NORMP)
420 
421 /* EXMC_D3 */
422 #define EXMC_D3_PD1 \
423 	GD32_PINMUX_AFIO('D', 1, ALTERNATE, NORMP)
424 
425 /* EXMC_D4 */
426 #define EXMC_D4_PE7 \
427 	GD32_PINMUX_AFIO('E', 7, ALTERNATE, NORMP)
428 
429 /* EXMC_D5 */
430 #define EXMC_D5_PE8 \
431 	GD32_PINMUX_AFIO('E', 8, ALTERNATE, NORMP)
432 
433 /* EXMC_D6 */
434 #define EXMC_D6_PE9 \
435 	GD32_PINMUX_AFIO('E', 9, ALTERNATE, NORMP)
436 
437 /* EXMC_D7 */
438 #define EXMC_D7_PE10 \
439 	GD32_PINMUX_AFIO('E', 10, ALTERNATE, NORMP)
440 
441 /* EXMC_D8 */
442 #define EXMC_D8_PE11 \
443 	GD32_PINMUX_AFIO('E', 11, ALTERNATE, NORMP)
444 
445 /* EXMC_D9 */
446 #define EXMC_D9_PE12 \
447 	GD32_PINMUX_AFIO('E', 12, ALTERNATE, NORMP)
448 
449 /* EXMC_INT1 */
450 #define EXMC_INT1_PG6 \
451 	GD32_PINMUX_AFIO('G', 6, GPIO_IN, NORMP)
452 
453 /* EXMC_INT2 */
454 #define EXMC_INT2_PG7 \
455 	GD32_PINMUX_AFIO('G', 7, GPIO_IN, NORMP)
456 
457 /* EXMC_INTR */
458 #define EXMC_INTR_PF10 \
459 	GD32_PINMUX_AFIO('F', 10, GPIO_IN, NORMP)
460 
461 /* EXMC_NADV */
462 #define EXMC_NADV_PB7 \
463 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, NORMP)
464 
465 /* EXMC_NBL0 */
466 #define EXMC_NBL0_PE0 \
467 	GD32_PINMUX_AFIO('E', 0, ALTERNATE, NORMP)
468 
469 /* EXMC_NBL1 */
470 #define EXMC_NBL1_PE1 \
471 	GD32_PINMUX_AFIO('E', 1, ALTERNATE, NORMP)
472 
473 /* EXMC_NCE1 */
474 #define EXMC_NCE1_PD7 \
475 	GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP)
476 
477 /* EXMC_NCE2 */
478 #define EXMC_NCE2_PG9 \
479 	GD32_PINMUX_AFIO('G', 9, ALTERNATE, NORMP)
480 
481 /* EXMC_NCE3_0 */
482 #define EXMC_NCE3_0_PG10 \
483 	GD32_PINMUX_AFIO('G', 10, ALTERNATE, NORMP)
484 
485 /* EXMC_NCE3_1 */
486 #define EXMC_NCE3_1_PG11 \
487 	GD32_PINMUX_AFIO('G', 11, ALTERNATE, NORMP)
488 
489 /* EXMC_NE0 */
490 #define EXMC_NE0_PD7 \
491 	GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP)
492 
493 /* EXMC_NE1 */
494 #define EXMC_NE1_PG9 \
495 	GD32_PINMUX_AFIO('G', 9, ALTERNATE, NORMP)
496 
497 /* EXMC_NE2 */
498 #define EXMC_NE2_PG10 \
499 	GD32_PINMUX_AFIO('G', 10, ALTERNATE, NORMP)
500 
501 /* EXMC_NE3 */
502 #define EXMC_NE3_PG12 \
503 	GD32_PINMUX_AFIO('G', 12, ALTERNATE, NORMP)
504 
505 /* EXMC_NIORD */
506 #define EXMC_NIORD_PF6 \
507 	GD32_PINMUX_AFIO('F', 6, ALTERNATE, NORMP)
508 
509 /* EXMC_NIOS16 */
510 #define EXMC_NIOS16_PF11 \
511 	GD32_PINMUX_AFIO('F', 11, GPIO_IN, NORMP)
512 
513 /* EXMC_NIOWR */
514 #define EXMC_NIOWR_PF8 \
515 	GD32_PINMUX_AFIO('F', 8, ALTERNATE, NORMP)
516 
517 /* EXMC_NOE */
518 #define EXMC_NOE_PD4 \
519 	GD32_PINMUX_AFIO('D', 4, ALTERNATE, NORMP)
520 
521 /* EXMC_NREG */
522 #define EXMC_NREG_PF7 \
523 	GD32_PINMUX_AFIO('F', 7, ALTERNATE, NORMP)
524 
525 /* EXMC_NWAIT */
526 #define EXMC_NWAIT_PD6 \
527 	GD32_PINMUX_AFIO('D', 6, GPIO_IN, NORMP)
528 
529 /* EXMC_NWE */
530 #define EXMC_NWE_PD5 \
531 	GD32_PINMUX_AFIO('D', 5, ALTERNATE, NORMP)
532 
533 /* I2C0_SCL */
534 #define I2C0_SCL_PB6_NORMP \
535 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP)
536 
537 /* I2C0_SDA */
538 #define I2C0_SDA_PB7_NORMP \
539 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP)
540 
541 /* I2C0_SMBA */
542 #define I2C0_SMBA_PB5 \
543 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP)
544 
545 /* I2S2_CK */
546 #define I2S2_CK_PB3_INP_NORMP \
547 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, I2S2_NORMP)
548 #define I2S2_CK_PB3_OUT_NORMP \
549 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP)
550 
551 /* I2S2_SD */
552 #define I2S2_SD_PB5_INP_NORMP \
553 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP)
554 #define I2S2_SD_PB5_OUT_NORMP \
555 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP)
556 
557 /* I2S2_WS */
558 #define I2S2_WS_PA15_INP_NORMP \
559 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP)
560 #define I2S2_WS_PA15_OUT_NORMP \
561 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP)
562 #define I2S2_WS_PA4_INP_RMP \
563 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP)
564 #define I2S2_WS_PA4_OUT_RMP \
565 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP)
566 
567 /* SPI0_IO2 */
568 #define SPI0_IO2_PA2 \
569 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP)
570 
571 /* SPI0_IO3 */
572 #define SPI0_IO3_PA3 \
573 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP)
574 
575 /* SPI0_MISO */
576 #define SPI0_MISO_PA6_INP_NORMP \
577 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP)
578 #define SPI0_MISO_PA6_OUT_NORMP \
579 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP)
580 #define SPI0_MISO_PB4_INP_RMP \
581 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP)
582 #define SPI0_MISO_PB4_OUT_RMP \
583 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP)
584 
585 /* SPI0_MOSI */
586 #define SPI0_MOSI_PA7_INP_NORMP \
587 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP)
588 #define SPI0_MOSI_PA7_OUT_NORMP \
589 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP)
590 #define SPI0_MOSI_PB5_INP_RMP \
591 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP)
592 #define SPI0_MOSI_PB5_OUT_RMP \
593 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP)
594 
595 /* SPI0_NSS */
596 #define SPI0_NSS_PA4_INP_NORMP \
597 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP)
598 #define SPI0_NSS_PA4_OUT_NORMP \
599 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP)
600 #define SPI0_NSS_PA15_INP_RMP \
601 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP)
602 #define SPI0_NSS_PA15_OUT_RMP \
603 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP)
604 
605 /* SPI0_SCK */
606 #define SPI0_SCK_PA5_INP_NORMP \
607 	GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP)
608 #define SPI0_SCK_PA5_OUT_NORMP \
609 	GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP)
610 #define SPI0_SCK_PB3_INP_RMP \
611 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP)
612 #define SPI0_SCK_PB3_OUT_RMP \
613 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP)
614 
615 /* SPI2_MISO */
616 #define SPI2_MISO_PB4_INP_NORMP \
617 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP)
618 #define SPI2_MISO_PB4_OUT_NORMP \
619 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP)
620 
621 /* SPI2_MOSI */
622 #define SPI2_MOSI_PB5_INP_NORMP \
623 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP)
624 #define SPI2_MOSI_PB5_OUT_NORMP \
625 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP)
626 
627 /* SPI2_NSS */
628 #define SPI2_NSS_PA15_INP_NORMP \
629 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP)
630 #define SPI2_NSS_PA15_OUT_NORMP \
631 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP)
632 #define SPI2_NSS_PA4_INP_RMP \
633 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP)
634 #define SPI2_NSS_PA4_OUT_RMP \
635 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP)
636 
637 /* SPI2_SCK */
638 #define SPI2_SCK_PB3_INP_NORMP \
639 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP)
640 #define SPI2_SCK_PB3_OUT_NORMP \
641 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP)
642 
643 /* TIMER0_CH0 */
644 #define TIMER0_CH0_PA8_INP_NORMP \
645 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP)
646 #define TIMER0_CH0_PA8_OUT_NORMP \
647 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP)
648 #define TIMER0_CH0_PA8_INP_PRMP \
649 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP)
650 #define TIMER0_CH0_PA8_OUT_PRMP \
651 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP)
652 #define TIMER0_CH0_PE9_INP_FRMP \
653 	GD32_PINMUX_AFIO('E', 9, GPIO_IN, TIMER0_FRMP)
654 #define TIMER0_CH0_PE9_OUT_FRMP \
655 	GD32_PINMUX_AFIO('E', 9, ALTERNATE, TIMER0_FRMP)
656 
657 /* TIMER0_CH0_ON */
658 #define TIMER0_CH0_ON_PA7_PRMP \
659 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP)
660 #define TIMER0_CH0_ON_PE8_FRMP \
661 	GD32_PINMUX_AFIO('E', 8, ALTERNATE, TIMER0_FRMP)
662 
663 /* TIMER0_CH1 */
664 #define TIMER0_CH1_PA9_INP_NORMP \
665 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP)
666 #define TIMER0_CH1_PA9_OUT_NORMP \
667 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP)
668 #define TIMER0_CH1_PA9_INP_PRMP \
669 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP)
670 #define TIMER0_CH1_PA9_OUT_PRMP \
671 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP)
672 #define TIMER0_CH1_PE11_INP_FRMP \
673 	GD32_PINMUX_AFIO('E', 11, GPIO_IN, TIMER0_FRMP)
674 #define TIMER0_CH1_PE11_OUT_FRMP \
675 	GD32_PINMUX_AFIO('E', 11, ALTERNATE, TIMER0_FRMP)
676 
677 /* TIMER0_CH1_ON */
678 #define TIMER0_CH1_ON_PB0_PRMP \
679 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP)
680 #define TIMER0_CH1_ON_PE10_FRMP \
681 	GD32_PINMUX_AFIO('E', 10, ALTERNATE, TIMER0_FRMP)
682 
683 /* TIMER0_CH2 */
684 #define TIMER0_CH2_PA10_INP_NORMP \
685 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP)
686 #define TIMER0_CH2_PA10_OUT_NORMP \
687 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP)
688 #define TIMER0_CH2_PA10_INP_PRMP \
689 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP)
690 #define TIMER0_CH2_PA10_OUT_PRMP \
691 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP)
692 #define TIMER0_CH2_PE13_INP_FRMP \
693 	GD32_PINMUX_AFIO('E', 13, GPIO_IN, TIMER0_FRMP)
694 #define TIMER0_CH2_PE13_OUT_FRMP \
695 	GD32_PINMUX_AFIO('E', 13, ALTERNATE, TIMER0_FRMP)
696 
697 /* TIMER0_CH2_ON */
698 #define TIMER0_CH2_ON_PB1_PRMP \
699 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP)
700 #define TIMER0_CH2_ON_PE12_FRMP \
701 	GD32_PINMUX_AFIO('E', 12, ALTERNATE, TIMER0_FRMP)
702 
703 /* TIMER0_CH3 */
704 #define TIMER0_CH3_PA11_INP_NORMP \
705 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP)
706 #define TIMER0_CH3_PA11_OUT_NORMP \
707 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP)
708 #define TIMER0_CH3_PA11_INP_PRMP \
709 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP)
710 #define TIMER0_CH3_PA11_OUT_PRMP \
711 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP)
712 #define TIMER0_CH3_PE14_INP_FRMP \
713 	GD32_PINMUX_AFIO('E', 14, GPIO_IN, TIMER0_FRMP)
714 #define TIMER0_CH3_PE14_OUT_FRMP \
715 	GD32_PINMUX_AFIO('E', 14, ALTERNATE, TIMER0_FRMP)
716 
717 /* TIMER0_ETI */
718 #define TIMER0_ETI_PA12_NORMP \
719 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP)
720 #define TIMER0_ETI_PA12_PRMP \
721 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP)
722 #define TIMER0_ETI_PE7_FRMP \
723 	GD32_PINMUX_AFIO('E', 7, GPIO_IN, TIMER0_FRMP)
724 
725 /* TIMER10_CH0 */
726 #define TIMER10_CH0_PF7_INP_RMP \
727 	GD32_PINMUX_AFIO('F', 7, GPIO_IN, TIMER10_RMP)
728 #define TIMER10_CH0_PF7_OUT_RMP \
729 	GD32_PINMUX_AFIO('F', 7, ALTERNATE, TIMER10_RMP)
730 
731 /* TIMER12_CH0 */
732 #define TIMER12_CH0_PA6_INP_NORMP \
733 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER12_NORMP)
734 #define TIMER12_CH0_PA6_OUT_NORMP \
735 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER12_NORMP)
736 #define TIMER12_CH0_PF8_INP_RMP \
737 	GD32_PINMUX_AFIO('F', 8, GPIO_IN, TIMER12_RMP)
738 #define TIMER12_CH0_PF8_OUT_RMP \
739 	GD32_PINMUX_AFIO('F', 8, ALTERNATE, TIMER12_RMP)
740 
741 /* TIMER13_CH0 */
742 #define TIMER13_CH0_PA7_INP_NORMP \
743 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER13_NORMP)
744 #define TIMER13_CH0_PA7_OUT_NORMP \
745 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER13_NORMP)
746 #define TIMER13_CH0_PF9_INP_RMP \
747 	GD32_PINMUX_AFIO('F', 9, GPIO_IN, TIMER13_RMP)
748 #define TIMER13_CH0_PF9_OUT_RMP \
749 	GD32_PINMUX_AFIO('F', 9, ALTERNATE, TIMER13_RMP)
750 
751 /* TIMER2_CH0 */
752 #define TIMER2_CH0_PA6_INP_NORMP \
753 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP)
754 #define TIMER2_CH0_PA6_OUT_NORMP \
755 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP)
756 #define TIMER2_CH0_PB4_INP_PRMP \
757 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP)
758 #define TIMER2_CH0_PB4_OUT_PRMP \
759 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP)
760 
761 /* TIMER2_CH1 */
762 #define TIMER2_CH1_PA7_INP_NORMP \
763 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP)
764 #define TIMER2_CH1_PA7_OUT_NORMP \
765 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP)
766 #define TIMER2_CH1_PB5_INP_PRMP \
767 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP)
768 #define TIMER2_CH1_PB5_OUT_PRMP \
769 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP)
770 
771 /* TIMER2_CH2 */
772 #define TIMER2_CH2_PB0_INP_NORMP \
773 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP)
774 #define TIMER2_CH2_PB0_OUT_NORMP \
775 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP)
776 #define TIMER2_CH2_PB0_INP_PRMP \
777 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP)
778 #define TIMER2_CH2_PB0_OUT_PRMP \
779 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP)
780 
781 /* TIMER2_CH3 */
782 #define TIMER2_CH3_PB1_INP_NORMP \
783 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP)
784 #define TIMER2_CH3_PB1_OUT_NORMP \
785 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP)
786 #define TIMER2_CH3_PB1_INP_PRMP \
787 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP)
788 #define TIMER2_CH3_PB1_OUT_PRMP \
789 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP)
790 
791 /* TIMER2_ETI */
792 #define TIMER2_ETI_PD2 \
793 	GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP)
794 
795 /* TIMER3_CH0 */
796 #define TIMER3_CH0_PB6_INP_NORMP \
797 	GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP)
798 #define TIMER3_CH0_PB6_OUT_NORMP \
799 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP)
800 #define TIMER3_CH0_PD12_INP_RMP \
801 	GD32_PINMUX_AFIO('D', 12, GPIO_IN, TIMER3_RMP)
802 #define TIMER3_CH0_PD12_OUT_RMP \
803 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, TIMER3_RMP)
804 
805 /* TIMER3_CH1 */
806 #define TIMER3_CH1_PB7_INP_NORMP \
807 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP)
808 #define TIMER3_CH1_PB7_OUT_NORMP \
809 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP)
810 #define TIMER3_CH1_PD13_INP_RMP \
811 	GD32_PINMUX_AFIO('D', 13, GPIO_IN, TIMER3_RMP)
812 #define TIMER3_CH1_PD13_OUT_RMP \
813 	GD32_PINMUX_AFIO('D', 13, ALTERNATE, TIMER3_RMP)
814 
815 /* TIMER3_CH2 */
816 #define TIMER3_CH2_PD14_INP_RMP \
817 	GD32_PINMUX_AFIO('D', 14, GPIO_IN, TIMER3_RMP)
818 #define TIMER3_CH2_PD14_OUT_RMP \
819 	GD32_PINMUX_AFIO('D', 14, ALTERNATE, TIMER3_RMP)
820 
821 /* TIMER3_CH3 */
822 #define TIMER3_CH3_PD15_INP_RMP \
823 	GD32_PINMUX_AFIO('D', 15, GPIO_IN, TIMER3_RMP)
824 #define TIMER3_CH3_PD15_OUT_RMP \
825 	GD32_PINMUX_AFIO('D', 15, ALTERNATE, TIMER3_RMP)
826 
827 /* TIMER3_ETI */
828 #define TIMER3_ETI_PE0 \
829 	GD32_PINMUX_AFIO('E', 0, GPIO_IN, NORMP)
830 
831 /* TIMER7_BRKIN */
832 #define TIMER7_BRKIN_PA6 \
833 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP)
834 
835 /* TIMER7_CH0_ON */
836 #define TIMER7_CH0_ON_PA7 \
837 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP)
838 
839 /* TIMER7_CH1_ON */
840 #define TIMER7_CH1_ON_PB0 \
841 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, NORMP)
842 
843 /* TIMER7_CH2_ON */
844 #define TIMER7_CH2_ON_PB1 \
845 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP)
846 
847 /* TIMER7_ETI */
848 #define TIMER7_ETI_PA0 \
849 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
850 
851 /* TIMER8_CH0 */
852 #define TIMER8_CH0_PA2_INP_NORMP \
853 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER8_NORMP)
854 #define TIMER8_CH0_PA2_OUT_NORMP \
855 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER8_NORMP)
856 #define TIMER8_CH0_PE5_INP_RMP \
857 	GD32_PINMUX_AFIO('E', 5, GPIO_IN, TIMER8_RMP)
858 #define TIMER8_CH0_PE5_OUT_RMP \
859 	GD32_PINMUX_AFIO('E', 5, ALTERNATE, TIMER8_RMP)
860 
861 /* TIMER8_CH1 */
862 #define TIMER8_CH1_PA3_INP_NORMP \
863 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER8_NORMP)
864 #define TIMER8_CH1_PA3_OUT_NORMP \
865 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER8_NORMP)
866 #define TIMER8_CH1_PE6_INP_RMP \
867 	GD32_PINMUX_AFIO('E', 6, GPIO_IN, TIMER8_RMP)
868 #define TIMER8_CH1_PE6_OUT_RMP \
869 	GD32_PINMUX_AFIO('E', 6, ALTERNATE, TIMER8_RMP)
870 
871 /* TIMER9_CH0 */
872 #define TIMER9_CH0_PF6_INP_RMP \
873 	GD32_PINMUX_AFIO('F', 6, GPIO_IN, TIMER9_RMP)
874 #define TIMER9_CH0_PF6_OUT_RMP \
875 	GD32_PINMUX_AFIO('F', 6, ALTERNATE, TIMER9_RMP)
876 
877 /* TRACECK */
878 #define TRACECK_PE2 \
879 	GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP)
880 
881 /* TRACED0 */
882 #define TRACED0_PE3 \
883 	GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP)
884 
885 /* TRACED1 */
886 #define TRACED1_PE4 \
887 	GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP)
888 
889 /* TRACED2 */
890 #define TRACED2_PE5 \
891 	GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP)
892 
893 /* TRACED3 */
894 #define TRACED3_PE6 \
895 	GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP)
896 
897 /* UART4_RX */
898 #define UART4_RX_PD2 \
899 	GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP)
900 
901 /* USART0_CK */
902 #define USART0_CK_PA8 \
903 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
904 
905 /* USART0_CTS */
906 #define USART0_CTS_PA11 \
907 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
908 
909 /* USART0_RTS */
910 #define USART0_RTS_PA12 \
911 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
912 
913 /* USART0_RX */
914 #define USART0_RX_PA10_NORMP \
915 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP)
916 #define USART0_RX_PB7_RMP \
917 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP)
918 
919 /* USART0_TX */
920 #define USART0_TX_PA9_NORMP \
921 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP)
922 #define USART0_TX_PB6_RMP \
923 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP)
924 
925 /* USART1_CK */
926 #define USART1_CK_PA4_NORMP \
927 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP)
928 #define USART1_CK_PD7_RMP \
929 	GD32_PINMUX_AFIO('D', 7, ALTERNATE, USART1_RMP)
930 
931 /* USART1_CTS */
932 #define USART1_CTS_PA0_NORMP \
933 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP)
934 #define USART1_CTS_PD3_RMP \
935 	GD32_PINMUX_AFIO('D', 3, GPIO_IN, USART1_RMP)
936 
937 /* USART1_RTS */
938 #define USART1_RTS_PA1_NORMP \
939 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP)
940 #define USART1_RTS_PD4_RMP \
941 	GD32_PINMUX_AFIO('D', 4, ALTERNATE, USART1_RMP)
942 
943 /* USART1_RX */
944 #define USART1_RX_PA3_NORMP \
945 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP)
946 #define USART1_RX_PD6_RMP \
947 	GD32_PINMUX_AFIO('D', 6, GPIO_IN, USART1_RMP)
948 
949 /* USART1_TX */
950 #define USART1_TX_PA2_NORMP \
951 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP)
952 #define USART1_TX_PD5_RMP \
953 	GD32_PINMUX_AFIO('D', 5, ALTERNATE, USART1_RMP)
954 
955 /* USART2_CK */
956 #define USART2_CK_PD10_FRMP \
957 	GD32_PINMUX_AFIO('D', 10, ALTERNATE, USART2_FRMP)
958 
959 /* USART2_CTS */
960 #define USART2_CTS_PD11_FRMP \
961 	GD32_PINMUX_AFIO('D', 11, GPIO_IN, USART2_FRMP)
962 
963 /* USART2_RTS */
964 #define USART2_RTS_PD12_FRMP \
965 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, USART2_FRMP)
966 
967 /* USART2_RX */
968 #define USART2_RX_PD9_FRMP \
969 	GD32_PINMUX_AFIO('D', 9, GPIO_IN, USART2_FRMP)
970 
971 /* USART2_TX */
972 #define USART2_TX_PD8_FRMP \
973 	GD32_PINMUX_AFIO('D', 8, ALTERNATE, USART2_FRMP)
974 
975 /* USBFS_DM */
976 #define USBFS_DM_PA11_INP \
977 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
978 #define USBFS_DM_PA11_OUT \
979 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP)
980 
981 /* USBFS_DP */
982 #define USBFS_DP_PA12_INP \
983 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP)
984 #define USBFS_DP_PA12_OUT \
985 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
986 
987 /* USBFS_ID */
988 #define USBFS_ID_PA10_INP \
989 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP)
990 #define USBFS_ID_PA10_OUT \
991 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP)
992 
993 /* USBFS_SOF */
994 #define USBFS_SOF_PA8 \
995 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
996 
997 /* USBFS_VBUS */
998 #define USBFS_VBUS_PA9 \
999 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP)
1000 
1001 /* WKUP */
1002 #define WKUP_PA0 \
1003 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
1004