1 /*
2  * Autogenerated file
3  *
4  * SPDX-License-Identifier: Apache 2.0
5  */
6 
7 #include "gd32f403xx-afio.h"
8 
9 /* ADC012_IN0 */
10 #define ADC012_IN0_PA0 \
11 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
12 
13 /* ADC012_IN1 */
14 #define ADC012_IN1_PA1 \
15 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
16 
17 /* ADC012_IN10 */
18 #define ADC012_IN10_PC0 \
19 	GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP)
20 
21 /* ADC012_IN11 */
22 #define ADC012_IN11_PC1 \
23 	GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP)
24 
25 /* ADC012_IN12 */
26 #define ADC012_IN12_PC2 \
27 	GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP)
28 
29 /* ADC012_IN13 */
30 #define ADC012_IN13_PC3 \
31 	GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP)
32 
33 /* ADC012_IN2 */
34 #define ADC012_IN2_PA2 \
35 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
36 
37 /* ADC012_IN3 */
38 #define ADC012_IN3_PA3 \
39 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
40 
41 /* ADC01_IN14 */
42 #define ADC01_IN14_PC4 \
43 	GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP)
44 
45 /* ADC01_IN15 */
46 #define ADC01_IN15_PC5 \
47 	GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP)
48 
49 /* ADC01_IN4 */
50 #define ADC01_IN4_PA4 \
51 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
52 
53 /* ADC01_IN5 */
54 #define ADC01_IN5_PA5 \
55 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
56 
57 /* ADC01_IN6 */
58 #define ADC01_IN6_PA6 \
59 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
60 
61 /* ADC01_IN7 */
62 #define ADC01_IN7_PA7 \
63 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
64 
65 /* ADC01_IN8 */
66 #define ADC01_IN8_PB0 \
67 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
68 
69 /* ADC01_IN9 */
70 #define ADC01_IN9_PB1 \
71 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
72 
73 /* ANALOG */
74 #define ANALOG_PA0 \
75 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
76 #define ANALOG_PA1 \
77 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
78 #define ANALOG_PA2 \
79 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
80 #define ANALOG_PA3 \
81 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
82 #define ANALOG_PA4 \
83 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
84 #define ANALOG_PA5 \
85 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
86 #define ANALOG_PA6 \
87 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
88 #define ANALOG_PA7 \
89 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
90 #define ANALOG_PA8 \
91 	GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP)
92 #define ANALOG_PA9 \
93 	GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP)
94 #define ANALOG_PA10 \
95 	GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP)
96 #define ANALOG_PA11 \
97 	GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP)
98 #define ANALOG_PA12 \
99 	GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP)
100 #define ANALOG_PA13 \
101 	GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP)
102 #define ANALOG_PA14 \
103 	GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP)
104 #define ANALOG_PA15 \
105 	GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP)
106 #define ANALOG_PB0 \
107 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
108 #define ANALOG_PB1 \
109 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
110 #define ANALOG_PB2 \
111 	GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP)
112 #define ANALOG_PB3 \
113 	GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP)
114 #define ANALOG_PB4 \
115 	GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP)
116 #define ANALOG_PB5 \
117 	GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP)
118 #define ANALOG_PB6 \
119 	GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP)
120 #define ANALOG_PB7 \
121 	GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP)
122 #define ANALOG_PB8 \
123 	GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP)
124 #define ANALOG_PB9 \
125 	GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP)
126 #define ANALOG_PB10 \
127 	GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP)
128 #define ANALOG_PB11 \
129 	GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP)
130 #define ANALOG_PB12 \
131 	GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP)
132 #define ANALOG_PB13 \
133 	GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP)
134 #define ANALOG_PB14 \
135 	GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP)
136 #define ANALOG_PB15 \
137 	GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP)
138 #define ANALOG_PC0 \
139 	GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP)
140 #define ANALOG_PC1 \
141 	GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP)
142 #define ANALOG_PC2 \
143 	GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP)
144 #define ANALOG_PC3 \
145 	GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP)
146 #define ANALOG_PC4 \
147 	GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP)
148 #define ANALOG_PC5 \
149 	GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP)
150 #define ANALOG_PC6 \
151 	GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP)
152 #define ANALOG_PC7 \
153 	GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP)
154 #define ANALOG_PC8 \
155 	GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP)
156 #define ANALOG_PC9 \
157 	GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP)
158 #define ANALOG_PC10 \
159 	GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP)
160 #define ANALOG_PC11 \
161 	GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP)
162 #define ANALOG_PC12 \
163 	GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP)
164 #define ANALOG_PC13 \
165 	GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP)
166 #define ANALOG_PC14 \
167 	GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP)
168 #define ANALOG_PC15 \
169 	GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP)
170 #define ANALOG_PD0 \
171 	GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP)
172 #define ANALOG_PD1 \
173 	GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP)
174 #define ANALOG_PD2 \
175 	GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP)
176 
177 /* CAN0_RX */
178 #define CAN0_RX_PA11_NORMP \
179 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, CAN0_NORMP)
180 #define CAN0_RX_PB8_PRMP \
181 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, CAN0_PRMP)
182 #define CAN0_RX_PD0_FRMP \
183 	GD32_PINMUX_AFIO('D', 0, GPIO_IN, CAN0_FRMP)
184 
185 /* CAN0_TX */
186 #define CAN0_TX_PA12_NORMP \
187 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, CAN0_NORMP)
188 #define CAN0_TX_PB9_PRMP \
189 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, CAN0_PRMP)
190 #define CAN0_TX_PD1_FRMP \
191 	GD32_PINMUX_AFIO('D', 1, ALTERNATE, CAN0_FRMP)
192 
193 /* CAN1_RX */
194 #define CAN1_RX_PB12_NORMP \
195 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, CAN1_NORMP)
196 #define CAN1_RX_PB5_RMP \
197 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, CAN1_RMP)
198 
199 /* CAN1_TX */
200 #define CAN1_TX_PB13_NORMP \
201 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, CAN1_NORMP)
202 #define CAN1_TX_PB6_RMP \
203 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, CAN1_RMP)
204 
205 /* CK_OUT0 */
206 #define CK_OUT0_PA8 \
207 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
208 
209 /* CTC_SYNC */
210 #define CTC_SYNC_PA8_NORMP \
211 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, CTC_NORMP)
212 
213 /* DAC_OUT0 */
214 #define DAC_OUT0_PA4 \
215 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
216 
217 /* DAC_OUT1 */
218 #define DAC_OUT1_PA5 \
219 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
220 
221 /* I2C0_SCL */
222 #define I2C0_SCL_PB6_NORMP \
223 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP)
224 #define I2C0_SCL_PB8_RMP \
225 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP)
226 
227 /* I2C0_SDA */
228 #define I2C0_SDA_PB7_NORMP \
229 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP)
230 #define I2C0_SDA_PB9_RMP \
231 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP)
232 
233 /* I2C0_SMBA */
234 #define I2C0_SMBA_PB5 \
235 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP)
236 
237 /* I2C1_SCL */
238 #define I2C1_SCL_PB10 \
239 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP)
240 
241 /* I2C1_SDA */
242 #define I2C1_SDA_PB11 \
243 	GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP)
244 
245 /* I2C1_SMBA */
246 #define I2C1_SMBA_PB12 \
247 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
248 
249 /* I2S1_CK */
250 #define I2S1_CK_PB13_INP \
251 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP)
252 #define I2S1_CK_PB13_OUT \
253 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
254 
255 /* I2S1_MCK */
256 #define I2S1_MCK_PC6 \
257 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP)
258 
259 /* I2S1_SD */
260 #define I2S1_SD_PB15_INP \
261 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
262 #define I2S1_SD_PB15_OUT \
263 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
264 
265 /* I2S1_WS */
266 #define I2S1_WS_PB12_INP \
267 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
268 #define I2S1_WS_PB12_OUT \
269 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
270 
271 /* I2S2_CK */
272 #define I2S2_CK_PB3_INP_NORMP \
273 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, I2S2_NORMP)
274 #define I2S2_CK_PB3_OUT_NORMP \
275 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP)
276 #define I2S2_CK_PC10_INP_RMP \
277 	GD32_PINMUX_AFIO('C', 10, GPIO_IN, I2S2_RMP)
278 #define I2S2_CK_PC10_OUT_RMP \
279 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP)
280 
281 /* I2S2_MCK */
282 #define I2S2_MCK_PC7 \
283 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP)
284 
285 /* I2S2_SD */
286 #define I2S2_SD_PB5_INP_NORMP \
287 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP)
288 #define I2S2_SD_PB5_OUT_NORMP \
289 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP)
290 #define I2S2_SD_PC12_INP_RMP \
291 	GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP)
292 #define I2S2_SD_PC12_OUT_RMP \
293 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP)
294 
295 /* I2S2_WS */
296 #define I2S2_WS_PA15_INP_NORMP \
297 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP)
298 #define I2S2_WS_PA15_OUT_NORMP \
299 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP)
300 #define I2S2_WS_PA4_INP_RMP \
301 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP)
302 #define I2S2_WS_PA4_OUT_RMP \
303 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP)
304 
305 /* SDIO_CK */
306 #define SDIO_CK_PC12 \
307 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP)
308 
309 /* SDIO_D0 */
310 #define SDIO_D0_PC8 \
311 	GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP)
312 
313 /* SDIO_D1 */
314 #define SDIO_D1_PC9 \
315 	GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP)
316 
317 /* SDIO_D2 */
318 #define SDIO_D2_PC10 \
319 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP)
320 
321 /* SDIO_D3 */
322 #define SDIO_D3_PC11 \
323 	GD32_PINMUX_AFIO('C', 11, ALTERNATE, NORMP)
324 
325 /* SDIO_D4 */
326 #define SDIO_D4_PB8 \
327 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP)
328 
329 /* SDIO_D5 */
330 #define SDIO_D5_PB9 \
331 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP)
332 
333 /* SDIO_D6 */
334 #define SDIO_D6_PC6 \
335 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP)
336 
337 /* SDIO_D7 */
338 #define SDIO_D7_PC7 \
339 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP)
340 
341 /* SPI0_IO2 */
342 #define SPI0_IO2_PA2 \
343 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP)
344 
345 /* SPI0_IO3 */
346 #define SPI0_IO3_PA3 \
347 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP)
348 
349 /* SPI0_MISO */
350 #define SPI0_MISO_PA6_INP_NORMP \
351 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP)
352 #define SPI0_MISO_PA6_OUT_NORMP \
353 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP)
354 #define SPI0_MISO_PB4_INP_RMP \
355 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP)
356 #define SPI0_MISO_PB4_OUT_RMP \
357 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP)
358 
359 /* SPI0_MOSI */
360 #define SPI0_MOSI_PA7_INP_NORMP \
361 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP)
362 #define SPI0_MOSI_PA7_OUT_NORMP \
363 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP)
364 #define SPI0_MOSI_PB5_INP_RMP \
365 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP)
366 #define SPI0_MOSI_PB5_OUT_RMP \
367 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP)
368 
369 /* SPI0_NSS */
370 #define SPI0_NSS_PA4_INP_NORMP \
371 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP)
372 #define SPI0_NSS_PA4_OUT_NORMP \
373 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP)
374 #define SPI0_NSS_PA15_INP_RMP \
375 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP)
376 #define SPI0_NSS_PA15_OUT_RMP \
377 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP)
378 
379 /* SPI0_SCK */
380 #define SPI0_SCK_PA5_INP_NORMP \
381 	GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP)
382 #define SPI0_SCK_PA5_OUT_NORMP \
383 	GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP)
384 #define SPI0_SCK_PB3_INP_RMP \
385 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP)
386 #define SPI0_SCK_PB3_OUT_RMP \
387 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP)
388 
389 /* SPI1_MISO */
390 #define SPI1_MISO_PB14_INP \
391 	GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP)
392 #define SPI1_MISO_PB14_OUT \
393 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP)
394 
395 /* SPI1_MOSI */
396 #define SPI1_MOSI_PB15_INP \
397 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
398 #define SPI1_MOSI_PB15_OUT \
399 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
400 
401 /* SPI1_NSS */
402 #define SPI1_NSS_PB12_INP \
403 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
404 #define SPI1_NSS_PB12_OUT \
405 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
406 
407 /* SPI1_SCK */
408 #define SPI1_SCK_PB13_INP \
409 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP)
410 #define SPI1_SCK_PB13_OUT \
411 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
412 
413 /* SPI2_MISO */
414 #define SPI2_MISO_PB4_INP_NORMP \
415 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP)
416 #define SPI2_MISO_PB4_OUT_NORMP \
417 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP)
418 #define SPI2_MISO_PC11_INP_RMP \
419 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP)
420 #define SPI2_MISO_PC11_OUT_RMP \
421 	GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP)
422 
423 /* SPI2_MOSI */
424 #define SPI2_MOSI_PB5_INP_NORMP \
425 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP)
426 #define SPI2_MOSI_PB5_OUT_NORMP \
427 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP)
428 #define SPI2_MOSI_PC12_INP_RMP \
429 	GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP)
430 #define SPI2_MOSI_PC12_OUT_RMP \
431 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP)
432 
433 /* SPI2_NSS */
434 #define SPI2_NSS_PA15_INP_NORMP \
435 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP)
436 #define SPI2_NSS_PA15_OUT_NORMP \
437 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP)
438 #define SPI2_NSS_PA4_INP_RMP \
439 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP)
440 #define SPI2_NSS_PA4_OUT_RMP \
441 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP)
442 
443 /* SPI2_SCK */
444 #define SPI2_SCK_PB3_INP_NORMP \
445 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP)
446 #define SPI2_SCK_PB3_OUT_NORMP \
447 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP)
448 #define SPI2_SCK_PC10_INP_RMP \
449 	GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP)
450 #define SPI2_SCK_PC10_OUT_RMP \
451 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP)
452 
453 /* TAMPER_RTC */
454 #define TAMPER_RTC_PC13 \
455 	GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP)
456 
457 /* TIMER0_BRKIN */
458 #define TIMER0_BRKIN_PB12 \
459 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
460 
461 /* TIMER0_CH0 */
462 #define TIMER0_CH0_PA8_INP_NORMP \
463 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP)
464 #define TIMER0_CH0_PA8_OUT_NORMP \
465 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP)
466 #define TIMER0_CH0_PA8_INP_PRMP \
467 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP)
468 #define TIMER0_CH0_PA8_OUT_PRMP \
469 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP)
470 
471 /* TIMER0_CH0_ON */
472 #define TIMER0_CH0_ON_PB13_NORMP \
473 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP)
474 #define TIMER0_CH0_ON_PA7_PRMP \
475 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP)
476 
477 /* TIMER0_CH1 */
478 #define TIMER0_CH1_PA9_INP_NORMP \
479 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP)
480 #define TIMER0_CH1_PA9_OUT_NORMP \
481 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP)
482 #define TIMER0_CH1_PA9_INP_PRMP \
483 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP)
484 #define TIMER0_CH1_PA9_OUT_PRMP \
485 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP)
486 
487 /* TIMER0_CH1_ON */
488 #define TIMER0_CH1_ON_PB14_NORMP \
489 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP)
490 #define TIMER0_CH1_ON_PB0_PRMP \
491 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP)
492 
493 /* TIMER0_CH2 */
494 #define TIMER0_CH2_PA10_INP_NORMP \
495 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP)
496 #define TIMER0_CH2_PA10_OUT_NORMP \
497 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP)
498 #define TIMER0_CH2_PA10_INP_PRMP \
499 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP)
500 #define TIMER0_CH2_PA10_OUT_PRMP \
501 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP)
502 
503 /* TIMER0_CH2_ON */
504 #define TIMER0_CH2_ON_PB15_NORMP \
505 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP)
506 #define TIMER0_CH2_ON_PB1_PRMP \
507 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP)
508 
509 /* TIMER0_CH3 */
510 #define TIMER0_CH3_PA11_INP_NORMP \
511 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP)
512 #define TIMER0_CH3_PA11_OUT_NORMP \
513 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP)
514 #define TIMER0_CH3_PA11_INP_PRMP \
515 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP)
516 #define TIMER0_CH3_PA11_OUT_PRMP \
517 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP)
518 
519 /* TIMER0_ETI */
520 #define TIMER0_ETI_PA12_NORMP \
521 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP)
522 #define TIMER0_ETI_PA12_PRMP \
523 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP)
524 
525 /* TIMER10_CH0 */
526 #define TIMER10_CH0_PB9_INP_NORMP \
527 	GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER10_NORMP)
528 #define TIMER10_CH0_PB9_OUT_NORMP \
529 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER10_NORMP)
530 
531 /* TIMER11_CH0 */
532 #define TIMER11_CH0_PB14_INP \
533 	GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP)
534 #define TIMER11_CH0_PB14_OUT \
535 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP)
536 
537 /* TIMER11_CH1 */
538 #define TIMER11_CH1_PB15_INP \
539 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
540 #define TIMER11_CH1_PB15_OUT \
541 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
542 
543 /* TIMER12_CH0 */
544 #define TIMER12_CH0_PA6_INP_NORMP \
545 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER12_NORMP)
546 #define TIMER12_CH0_PA6_OUT_NORMP \
547 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER12_NORMP)
548 
549 /* TIMER13_CH0 */
550 #define TIMER13_CH0_PA7_INP_NORMP \
551 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER13_NORMP)
552 #define TIMER13_CH0_PA7_OUT_NORMP \
553 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER13_NORMP)
554 
555 /* TIMER2_CH0 */
556 #define TIMER2_CH0_PA6_INP_NORMP \
557 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP)
558 #define TIMER2_CH0_PA6_OUT_NORMP \
559 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP)
560 #define TIMER2_CH0_PB4_INP_PRMP \
561 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP)
562 #define TIMER2_CH0_PB4_OUT_PRMP \
563 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP)
564 #define TIMER2_CH0_PC6_INP_FRMP \
565 	GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP)
566 #define TIMER2_CH0_PC6_OUT_FRMP \
567 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP)
568 
569 /* TIMER2_CH1 */
570 #define TIMER2_CH1_PA7_INP_NORMP \
571 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP)
572 #define TIMER2_CH1_PA7_OUT_NORMP \
573 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP)
574 #define TIMER2_CH1_PB5_INP_PRMP \
575 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP)
576 #define TIMER2_CH1_PB5_OUT_PRMP \
577 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP)
578 #define TIMER2_CH1_PC7_INP_FRMP \
579 	GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP)
580 #define TIMER2_CH1_PC7_OUT_FRMP \
581 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP)
582 
583 /* TIMER2_CH2 */
584 #define TIMER2_CH2_PB0_INP_NORMP \
585 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP)
586 #define TIMER2_CH2_PB0_OUT_NORMP \
587 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP)
588 #define TIMER2_CH2_PB0_INP_PRMP \
589 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP)
590 #define TIMER2_CH2_PB0_OUT_PRMP \
591 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP)
592 #define TIMER2_CH2_PC8_INP_FRMP \
593 	GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP)
594 #define TIMER2_CH2_PC8_OUT_FRMP \
595 	GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP)
596 
597 /* TIMER2_CH3 */
598 #define TIMER2_CH3_PB1_INP_NORMP \
599 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP)
600 #define TIMER2_CH3_PB1_OUT_NORMP \
601 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP)
602 #define TIMER2_CH3_PB1_INP_PRMP \
603 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP)
604 #define TIMER2_CH3_PB1_OUT_PRMP \
605 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP)
606 #define TIMER2_CH3_PC9_INP_FRMP \
607 	GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP)
608 #define TIMER2_CH3_PC9_OUT_FRMP \
609 	GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP)
610 
611 /* TIMER2_ETI */
612 #define TIMER2_ETI_PD2 \
613 	GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP)
614 
615 /* TIMER3_CH0 */
616 #define TIMER3_CH0_PB6_INP_NORMP \
617 	GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP)
618 #define TIMER3_CH0_PB6_OUT_NORMP \
619 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP)
620 
621 /* TIMER3_CH1 */
622 #define TIMER3_CH1_PB7_INP_NORMP \
623 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP)
624 #define TIMER3_CH1_PB7_OUT_NORMP \
625 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP)
626 
627 /* TIMER3_CH2 */
628 #define TIMER3_CH2_PB8_INP_NORMP \
629 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP)
630 #define TIMER3_CH2_PB8_OUT_NORMP \
631 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP)
632 
633 /* TIMER3_CH3 */
634 #define TIMER3_CH3_PB9_INP_NORMP \
635 	GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP)
636 #define TIMER3_CH3_PB9_OUT_NORMP \
637 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP)
638 
639 /* TIMER7_BRKIN */
640 #define TIMER7_BRKIN_PA6 \
641 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP)
642 
643 /* TIMER7_CH0 */
644 #define TIMER7_CH0_PC6_INP \
645 	GD32_PINMUX_AFIO('C', 6, GPIO_IN, NORMP)
646 #define TIMER7_CH0_PC6_OUT \
647 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP)
648 
649 /* TIMER7_CH0_ON */
650 #define TIMER7_CH0_ON_PA7 \
651 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP)
652 
653 /* TIMER7_CH1 */
654 #define TIMER7_CH1_PC7_INP \
655 	GD32_PINMUX_AFIO('C', 7, GPIO_IN, NORMP)
656 #define TIMER7_CH1_PC7_OUT \
657 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP)
658 
659 /* TIMER7_CH1_ON */
660 #define TIMER7_CH1_ON_PB0 \
661 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, NORMP)
662 
663 /* TIMER7_CH2 */
664 #define TIMER7_CH2_PC8_INP \
665 	GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP)
666 #define TIMER7_CH2_PC8_OUT \
667 	GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP)
668 
669 /* TIMER7_CH2_ON */
670 #define TIMER7_CH2_ON_PB1 \
671 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP)
672 
673 /* TIMER7_CH3 */
674 #define TIMER7_CH3_PC9_INP \
675 	GD32_PINMUX_AFIO('C', 9, GPIO_IN, NORMP)
676 #define TIMER7_CH3_PC9_OUT \
677 	GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP)
678 
679 /* TIMER7_ETI */
680 #define TIMER7_ETI_PA0 \
681 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
682 
683 /* TIMER8_CH0 */
684 #define TIMER8_CH0_PA2_INP_NORMP \
685 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER8_NORMP)
686 #define TIMER8_CH0_PA2_OUT_NORMP \
687 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER8_NORMP)
688 
689 /* TIMER8_CH1 */
690 #define TIMER8_CH1_PA3_INP_NORMP \
691 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER8_NORMP)
692 #define TIMER8_CH1_PA3_OUT_NORMP \
693 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER8_NORMP)
694 
695 /* TIMER9_CH0 */
696 #define TIMER9_CH0_PB8_INP_NORMP \
697 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER9_NORMP)
698 #define TIMER9_CH0_PB8_OUT_NORMP \
699 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER9_NORMP)
700 
701 /* UART3_RX */
702 #define UART3_RX_PC11 \
703 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP)
704 
705 /* UART3_TX */
706 #define UART3_TX_PC10 \
707 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP)
708 
709 /* UART4_RX */
710 #define UART4_RX_PD2 \
711 	GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP)
712 
713 /* UART4_TX */
714 #define UART4_TX_PC12 \
715 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP)
716 
717 /* USART0_CK */
718 #define USART0_CK_PA8 \
719 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
720 
721 /* USART0_CTS */
722 #define USART0_CTS_PA11 \
723 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
724 
725 /* USART0_RTS */
726 #define USART0_RTS_PA12 \
727 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
728 
729 /* USART0_RX */
730 #define USART0_RX_PA10_NORMP \
731 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP)
732 #define USART0_RX_PB7_RMP \
733 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP)
734 
735 /* USART0_TX */
736 #define USART0_TX_PA9_NORMP \
737 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP)
738 #define USART0_TX_PB6_RMP \
739 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP)
740 
741 /* USART1_CK */
742 #define USART1_CK_PA4_NORMP \
743 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP)
744 
745 /* USART1_CTS */
746 #define USART1_CTS_PA0_NORMP \
747 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP)
748 
749 /* USART1_RTS */
750 #define USART1_RTS_PA1_NORMP \
751 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP)
752 
753 /* USART1_RX */
754 #define USART1_RX_PA3_NORMP \
755 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP)
756 
757 /* USART1_TX */
758 #define USART1_TX_PA2_NORMP \
759 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP)
760 
761 /* USART2_CK */
762 #define USART2_CK_PB12_NORMP \
763 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP)
764 #define USART2_CK_PC12_PRMP \
765 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP)
766 
767 /* USART2_CTS */
768 #define USART2_CTS_PB13_NORMP \
769 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP)
770 #define USART2_CTS_PB13_PRMP \
771 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP)
772 
773 /* USART2_RTS */
774 #define USART2_RTS_PB14_NORMP \
775 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP)
776 #define USART2_RTS_PB14_PRMP \
777 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP)
778 
779 /* USART2_RX */
780 #define USART2_RX_PB11_NORMP \
781 	GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP)
782 #define USART2_RX_PC11_PRMP \
783 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP)
784 
785 /* USART2_TX */
786 #define USART2_TX_PB10_NORMP \
787 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP)
788 #define USART2_TX_PC10_PRMP \
789 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP)
790 
791 /* USBFS_DM */
792 #define USBFS_DM_PA11_INP \
793 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
794 #define USBFS_DM_PA11_OUT \
795 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP)
796 
797 /* USBFS_DP */
798 #define USBFS_DP_PA12_INP \
799 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP)
800 #define USBFS_DP_PA12_OUT \
801 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
802 
803 /* USBFS_ID */
804 #define USBFS_ID_PA10_INP \
805 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP)
806 #define USBFS_ID_PA10_OUT \
807 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP)
808 
809 /* USBFS_SOF */
810 #define USBFS_SOF_PA8 \
811 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
812 
813 /* USBFS_VBUS */
814 #define USBFS_VBUS_PA9 \
815 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP)
816 
817 /* WKUP */
818 #define WKUP_PA0 \
819 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
820