1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32-af.h" 8 9 /* ADC_IN0 */ 10 #define ADC_IN0_PA0 \ 11 GD32_PINMUX_AF('A', 0, ANALOG) 12 13 /* ADC_IN1 */ 14 #define ADC_IN1_PA1 \ 15 GD32_PINMUX_AF('A', 1, ANALOG) 16 17 /* ADC_IN10 */ 18 #define ADC_IN10_PC0 \ 19 GD32_PINMUX_AF('C', 0, ANALOG) 20 21 /* ADC_IN11 */ 22 #define ADC_IN11_PC1 \ 23 GD32_PINMUX_AF('C', 1, ANALOG) 24 25 /* ADC_IN12 */ 26 #define ADC_IN12_PC2 \ 27 GD32_PINMUX_AF('C', 2, ANALOG) 28 29 /* ADC_IN13 */ 30 #define ADC_IN13_PC3 \ 31 GD32_PINMUX_AF('C', 3, ANALOG) 32 33 /* ADC_IN14 */ 34 #define ADC_IN14_PC4 \ 35 GD32_PINMUX_AF('C', 4, ANALOG) 36 37 /* ADC_IN15 */ 38 #define ADC_IN15_PC5 \ 39 GD32_PINMUX_AF('C', 5, ANALOG) 40 41 /* ADC_IN2 */ 42 #define ADC_IN2_PA2 \ 43 GD32_PINMUX_AF('A', 2, ANALOG) 44 45 /* ADC_IN3 */ 46 #define ADC_IN3_PA3 \ 47 GD32_PINMUX_AF('A', 3, ANALOG) 48 49 /* ADC_IN4 */ 50 #define ADC_IN4_PA4 \ 51 GD32_PINMUX_AF('A', 4, ANALOG) 52 53 /* ADC_IN5 */ 54 #define ADC_IN5_PA5 \ 55 GD32_PINMUX_AF('A', 5, ANALOG) 56 57 /* ADC_IN6 */ 58 #define ADC_IN6_PA6 \ 59 GD32_PINMUX_AF('A', 6, ANALOG) 60 61 /* ADC_IN7 */ 62 #define ADC_IN7_PA7 \ 63 GD32_PINMUX_AF('A', 7, ANALOG) 64 65 /* ADC_IN8 */ 66 #define ADC_IN8_PB0 \ 67 GD32_PINMUX_AF('B', 0, ANALOG) 68 69 /* ADC_IN9 */ 70 #define ADC_IN9_PB1 \ 71 GD32_PINMUX_AF('B', 1, ANALOG) 72 73 /* ANALOG */ 74 #define ANALOG_PA0 \ 75 GD32_PINMUX_AF('A', 0, ANALOG) 76 #define ANALOG_PA1 \ 77 GD32_PINMUX_AF('A', 1, ANALOG) 78 #define ANALOG_PA2 \ 79 GD32_PINMUX_AF('A', 2, ANALOG) 80 #define ANALOG_PA3 \ 81 GD32_PINMUX_AF('A', 3, ANALOG) 82 #define ANALOG_PA4 \ 83 GD32_PINMUX_AF('A', 4, ANALOG) 84 #define ANALOG_PA5 \ 85 GD32_PINMUX_AF('A', 5, ANALOG) 86 #define ANALOG_PA6 \ 87 GD32_PINMUX_AF('A', 6, ANALOG) 88 #define ANALOG_PA7 \ 89 GD32_PINMUX_AF('A', 7, ANALOG) 90 #define ANALOG_PA8 \ 91 GD32_PINMUX_AF('A', 8, ANALOG) 92 #define ANALOG_PA9 \ 93 GD32_PINMUX_AF('A', 9, ANALOG) 94 #define ANALOG_PA10 \ 95 GD32_PINMUX_AF('A', 10, ANALOG) 96 #define ANALOG_PA11 \ 97 GD32_PINMUX_AF('A', 11, ANALOG) 98 #define ANALOG_PA12 \ 99 GD32_PINMUX_AF('A', 12, ANALOG) 100 #define ANALOG_PA13 \ 101 GD32_PINMUX_AF('A', 13, ANALOG) 102 #define ANALOG_PA14 \ 103 GD32_PINMUX_AF('A', 14, ANALOG) 104 #define ANALOG_PA15 \ 105 GD32_PINMUX_AF('A', 15, ANALOG) 106 #define ANALOG_PB0 \ 107 GD32_PINMUX_AF('B', 0, ANALOG) 108 #define ANALOG_PB1 \ 109 GD32_PINMUX_AF('B', 1, ANALOG) 110 #define ANALOG_PB2 \ 111 GD32_PINMUX_AF('B', 2, ANALOG) 112 #define ANALOG_PB3 \ 113 GD32_PINMUX_AF('B', 3, ANALOG) 114 #define ANALOG_PB4 \ 115 GD32_PINMUX_AF('B', 4, ANALOG) 116 #define ANALOG_PB5 \ 117 GD32_PINMUX_AF('B', 5, ANALOG) 118 #define ANALOG_PB6 \ 119 GD32_PINMUX_AF('B', 6, ANALOG) 120 #define ANALOG_PB7 \ 121 GD32_PINMUX_AF('B', 7, ANALOG) 122 #define ANALOG_PB8 \ 123 GD32_PINMUX_AF('B', 8, ANALOG) 124 #define ANALOG_PB9 \ 125 GD32_PINMUX_AF('B', 9, ANALOG) 126 #define ANALOG_PB10 \ 127 GD32_PINMUX_AF('B', 10, ANALOG) 128 #define ANALOG_PB11 \ 129 GD32_PINMUX_AF('B', 11, ANALOG) 130 #define ANALOG_PB12 \ 131 GD32_PINMUX_AF('B', 12, ANALOG) 132 #define ANALOG_PB13 \ 133 GD32_PINMUX_AF('B', 13, ANALOG) 134 #define ANALOG_PB14 \ 135 GD32_PINMUX_AF('B', 14, ANALOG) 136 #define ANALOG_PB15 \ 137 GD32_PINMUX_AF('B', 15, ANALOG) 138 #define ANALOG_PC0 \ 139 GD32_PINMUX_AF('C', 0, ANALOG) 140 #define ANALOG_PC1 \ 141 GD32_PINMUX_AF('C', 1, ANALOG) 142 #define ANALOG_PC2 \ 143 GD32_PINMUX_AF('C', 2, ANALOG) 144 #define ANALOG_PC3 \ 145 GD32_PINMUX_AF('C', 3, ANALOG) 146 #define ANALOG_PC4 \ 147 GD32_PINMUX_AF('C', 4, ANALOG) 148 #define ANALOG_PC5 \ 149 GD32_PINMUX_AF('C', 5, ANALOG) 150 #define ANALOG_PC6 \ 151 GD32_PINMUX_AF('C', 6, ANALOG) 152 #define ANALOG_PC7 \ 153 GD32_PINMUX_AF('C', 7, ANALOG) 154 #define ANALOG_PC8 \ 155 GD32_PINMUX_AF('C', 8, ANALOG) 156 #define ANALOG_PC9 \ 157 GD32_PINMUX_AF('C', 9, ANALOG) 158 #define ANALOG_PD2 \ 159 GD32_PINMUX_AF('D', 2, ANALOG) 160 #define ANALOG_PF0 \ 161 GD32_PINMUX_AF('F', 0, ANALOG) 162 #define ANALOG_PF4 \ 163 GD32_PINMUX_AF('F', 4, ANALOG) 164 #define ANALOG_PF5 \ 165 GD32_PINMUX_AF('F', 5, ANALOG) 166 #define ANALOG_PF6 \ 167 GD32_PINMUX_AF('F', 6, ANALOG) 168 #define ANALOG_PF7 \ 169 GD32_PINMUX_AF('F', 7, ANALOG) 170 171 /* CEC */ 172 #define CEC_PA5 \ 173 GD32_PINMUX_AF('A', 5, AF1) 174 #define CEC_PB8 \ 175 GD32_PINMUX_AF('B', 8, AF0) 176 #define CEC_PB10 \ 177 GD32_PINMUX_AF('B', 10, AF0) 178 179 /* CK_OUT */ 180 #define CK_OUT_PA8 \ 181 GD32_PINMUX_AF('A', 8, AF0) 182 183 /* CMP0_OUT */ 184 #define CMP0_OUT_PA0 \ 185 GD32_PINMUX_AF('A', 0, AF7) 186 #define CMP0_OUT_PA6 \ 187 GD32_PINMUX_AF('A', 6, AF7) 188 #define CMP0_OUT_PA11 \ 189 GD32_PINMUX_AF('A', 11, AF7) 190 191 /* CMP1_OUT */ 192 #define CMP1_OUT_PA2 \ 193 GD32_PINMUX_AF('A', 2, AF7) 194 #define CMP1_OUT_PA7 \ 195 GD32_PINMUX_AF('A', 7, AF7) 196 #define CMP1_OUT_PA12 \ 197 GD32_PINMUX_AF('A', 12, AF7) 198 199 /* CTC_SYNC */ 200 #define CTC_SYNC_PA8 \ 201 GD32_PINMUX_AF('A', 8, AF6) 202 #define CTC_SYNC_PF0 \ 203 GD32_PINMUX_AF('F', 0, AF0) 204 205 /* DAC0_OUT */ 206 #define DAC0_OUT_PA4 \ 207 GD32_PINMUX_AF('A', 4, ANALOG) 208 209 /* EVENTOUT */ 210 #define EVENTOUT_PA1 \ 211 GD32_PINMUX_AF('A', 1, AF0) 212 #define EVENTOUT_PA6 \ 213 GD32_PINMUX_AF('A', 6, AF6) 214 #define EVENTOUT_PA7 \ 215 GD32_PINMUX_AF('A', 7, AF6) 216 #define EVENTOUT_PA8 \ 217 GD32_PINMUX_AF('A', 8, AF3) 218 #define EVENTOUT_PA11 \ 219 GD32_PINMUX_AF('A', 11, AF0) 220 #define EVENTOUT_PA12 \ 221 GD32_PINMUX_AF('A', 12, AF0) 222 #define EVENTOUT_PA15 \ 223 GD32_PINMUX_AF('A', 15, AF3) 224 #define EVENTOUT_PB0 \ 225 GD32_PINMUX_AF('B', 0, AF0) 226 #define EVENTOUT_PB3 \ 227 GD32_PINMUX_AF('B', 3, AF1) 228 #define EVENTOUT_PB4 \ 229 GD32_PINMUX_AF('B', 4, AF2) 230 #define EVENTOUT_PB9 \ 231 GD32_PINMUX_AF('B', 9, AF3) 232 #define EVENTOUT_PB11 \ 233 GD32_PINMUX_AF('B', 11, AF0) 234 #define EVENTOUT_PB12 \ 235 GD32_PINMUX_AF('B', 12, AF1) 236 #define EVENTOUT_PC0 \ 237 GD32_PINMUX_AF('C', 0, AF0) 238 #define EVENTOUT_PC1 \ 239 GD32_PINMUX_AF('C', 1, AF0) 240 #define EVENTOUT_PC2 \ 241 GD32_PINMUX_AF('C', 2, AF0) 242 #define EVENTOUT_PC3 \ 243 GD32_PINMUX_AF('C', 3, AF0) 244 #define EVENTOUT_PC4 \ 245 GD32_PINMUX_AF('C', 4, AF0) 246 #define EVENTOUT_PF4 \ 247 GD32_PINMUX_AF('F', 4, AF0) 248 #define EVENTOUT_PF5 \ 249 GD32_PINMUX_AF('F', 5, AF0) 250 251 /* I2C0_SCL */ 252 #define I2C0_SCL_PA9 \ 253 GD32_PINMUX_AF('A', 9, AF4) 254 #define I2C0_SCL_PB6 \ 255 GD32_PINMUX_AF('B', 6, AF1) 256 #define I2C0_SCL_PB8 \ 257 GD32_PINMUX_AF('B', 8, AF1) 258 #define I2C0_SCL_PB10 \ 259 GD32_PINMUX_AF('B', 10, AF1) 260 #define I2C0_SCL_PF6 \ 261 GD32_PINMUX_AF('F', 6, AF0) 262 263 /* I2C0_SDA */ 264 #define I2C0_SDA_PA10 \ 265 GD32_PINMUX_AF('A', 10, AF4) 266 #define I2C0_SDA_PB7 \ 267 GD32_PINMUX_AF('B', 7, AF1) 268 #define I2C0_SDA_PB9 \ 269 GD32_PINMUX_AF('B', 9, AF1) 270 #define I2C0_SDA_PB11 \ 271 GD32_PINMUX_AF('B', 11, AF1) 272 #define I2C0_SDA_PF7 \ 273 GD32_PINMUX_AF('F', 7, AF0) 274 275 /* I2C0_SMBA */ 276 #define I2C0_SMBA_PB5 \ 277 GD32_PINMUX_AF('B', 5, AF3) 278 279 /* I2S0_CK */ 280 #define I2S0_CK_PA5 \ 281 GD32_PINMUX_AF('A', 5, AF0) 282 #define I2S0_CK_PB3 \ 283 GD32_PINMUX_AF('B', 3, AF0) 284 285 /* I2S0_MCK */ 286 #define I2S0_MCK_PA6 \ 287 GD32_PINMUX_AF('A', 6, AF0) 288 #define I2S0_MCK_PB4 \ 289 GD32_PINMUX_AF('B', 4, AF0) 290 #define I2S0_MCK_PB9 \ 291 GD32_PINMUX_AF('B', 9, AF5) 292 #define I2S0_MCK_PC6 \ 293 GD32_PINMUX_AF('C', 6, AF2) 294 295 /* I2S0_SD */ 296 #define I2S0_SD_PA7 \ 297 GD32_PINMUX_AF('A', 7, AF0) 298 #define I2S0_SD_PB5 \ 299 GD32_PINMUX_AF('B', 5, AF0) 300 301 /* I2S0_WS */ 302 #define I2S0_WS_PA4 \ 303 GD32_PINMUX_AF('A', 4, AF0) 304 #define I2S0_WS_PA15 \ 305 GD32_PINMUX_AF('A', 15, AF0) 306 307 /* IFRP_OUT */ 308 #define IFRP_OUT_PA13 \ 309 GD32_PINMUX_AF('A', 13, AF1) 310 #define IFRP_OUT_PB9 \ 311 GD32_PINMUX_AF('B', 9, AF0) 312 313 /* SPI0_MISO */ 314 #define SPI0_MISO_PA6 \ 315 GD32_PINMUX_AF('A', 6, AF0) 316 #define SPI0_MISO_PB4 \ 317 GD32_PINMUX_AF('B', 4, AF0) 318 #define SPI0_MISO_PB14 \ 319 GD32_PINMUX_AF('B', 14, AF0) 320 321 /* SPI0_MOSI */ 322 #define SPI0_MOSI_PA7 \ 323 GD32_PINMUX_AF('A', 7, AF0) 324 #define SPI0_MOSI_PB5 \ 325 GD32_PINMUX_AF('B', 5, AF0) 326 #define SPI0_MOSI_PB15 \ 327 GD32_PINMUX_AF('B', 15, AF0) 328 329 /* SPI0_NSS */ 330 #define SPI0_NSS_PA4 \ 331 GD32_PINMUX_AF('A', 4, AF0) 332 #define SPI0_NSS_PA15 \ 333 GD32_PINMUX_AF('A', 15, AF0) 334 #define SPI0_NSS_PB12 \ 335 GD32_PINMUX_AF('B', 12, AF0) 336 337 /* SPI0_SCK */ 338 #define SPI0_SCK_PA5 \ 339 GD32_PINMUX_AF('A', 5, AF0) 340 #define SPI0_SCK_PB3 \ 341 GD32_PINMUX_AF('B', 3, AF0) 342 #define SPI0_SCK_PB13 \ 343 GD32_PINMUX_AF('B', 13, AF0) 344 345 /* SWCLK */ 346 #define SWCLK_PA14 \ 347 GD32_PINMUX_AF('A', 14, AF0) 348 349 /* SWDIO */ 350 #define SWDIO_PA13 \ 351 GD32_PINMUX_AF('A', 13, AF0) 352 353 /* TIMER0_BKIN */ 354 #define TIMER0_BKIN_PA6 \ 355 GD32_PINMUX_AF('A', 6, AF2) 356 #define TIMER0_BKIN_PB12 \ 357 GD32_PINMUX_AF('B', 12, AF2) 358 359 /* TIMER0_CH0 */ 360 #define TIMER0_CH0_PA8 \ 361 GD32_PINMUX_AF('A', 8, AF2) 362 363 /* TIMER0_CH0_ON */ 364 #define TIMER0_CH0_ON_PA7 \ 365 GD32_PINMUX_AF('A', 7, AF2) 366 #define TIMER0_CH0_ON_PB13 \ 367 GD32_PINMUX_AF('B', 13, AF2) 368 369 /* TIMER0_CH1 */ 370 #define TIMER0_CH1_PA9 \ 371 GD32_PINMUX_AF('A', 9, AF2) 372 373 /* TIMER0_CH1_ON */ 374 #define TIMER0_CH1_ON_PB0 \ 375 GD32_PINMUX_AF('B', 0, AF2) 376 #define TIMER0_CH1_ON_PB14 \ 377 GD32_PINMUX_AF('B', 14, AF2) 378 379 /* TIMER0_CH2 */ 380 #define TIMER0_CH2_PA10 \ 381 GD32_PINMUX_AF('A', 10, AF2) 382 383 /* TIMER0_CH2_ON */ 384 #define TIMER0_CH2_ON_PB1 \ 385 GD32_PINMUX_AF('B', 1, AF2) 386 #define TIMER0_CH2_ON_PB15 \ 387 GD32_PINMUX_AF('B', 15, AF2) 388 389 /* TIMER0_CH3 */ 390 #define TIMER0_CH3_PA11 \ 391 GD32_PINMUX_AF('A', 11, AF2) 392 393 /* TIMER0_ETI */ 394 #define TIMER0_ETI_PA12 \ 395 GD32_PINMUX_AF('A', 12, AF2) 396 397 /* TIMER13_CH0 */ 398 #define TIMER13_CH0_PA4 \ 399 GD32_PINMUX_AF('A', 4, AF4) 400 #define TIMER13_CH0_PA7 \ 401 GD32_PINMUX_AF('A', 7, AF4) 402 #define TIMER13_CH0_PB1 \ 403 GD32_PINMUX_AF('B', 1, AF0) 404 405 /* TIMER14_BKIN */ 406 #define TIMER14_BKIN_PA9 \ 407 GD32_PINMUX_AF('A', 9, AF0) 408 409 /* TIMER14_CH0 */ 410 #define TIMER14_CH0_PA2 \ 411 GD32_PINMUX_AF('A', 2, AF0) 412 #define TIMER14_CH0_PB14 \ 413 GD32_PINMUX_AF('B', 14, AF1) 414 415 /* TIMER14_CH0_ON */ 416 #define TIMER14_CH0_ON_PB15 \ 417 GD32_PINMUX_AF('B', 15, AF3) 418 419 /* TIMER14_CH1 */ 420 #define TIMER14_CH1_PA3 \ 421 GD32_PINMUX_AF('A', 3, AF0) 422 #define TIMER14_CH1_PB15 \ 423 GD32_PINMUX_AF('B', 15, AF1) 424 425 /* TIMER15_BKIN */ 426 #define TIMER15_BKIN_PB5 \ 427 GD32_PINMUX_AF('B', 5, AF2) 428 429 /* TIMER15_CH0 */ 430 #define TIMER15_CH0_PA6 \ 431 GD32_PINMUX_AF('A', 6, AF5) 432 #define TIMER15_CH0_PB8 \ 433 GD32_PINMUX_AF('B', 8, AF2) 434 435 /* TIMER15_CH0_ON */ 436 #define TIMER15_CH0_ON_PB6 \ 437 GD32_PINMUX_AF('B', 6, AF2) 438 439 /* TIMER16_BKIN */ 440 #define TIMER16_BKIN_PA10 \ 441 GD32_PINMUX_AF('A', 10, AF0) 442 443 /* TIMER16_CH0 */ 444 #define TIMER16_CH0_PA7 \ 445 GD32_PINMUX_AF('A', 7, AF5) 446 #define TIMER16_CH0_PB9 \ 447 GD32_PINMUX_AF('B', 9, AF2) 448 449 /* TIMER16_CH0_ON */ 450 #define TIMER16_CH0_ON_PB7 \ 451 GD32_PINMUX_AF('B', 7, AF2) 452 453 /* TIMER1_CH0 */ 454 #define TIMER1_CH0_PA0 \ 455 GD32_PINMUX_AF('A', 0, AF2) 456 #define TIMER1_CH0_PA5 \ 457 GD32_PINMUX_AF('A', 5, AF2) 458 #define TIMER1_CH0_PA15 \ 459 GD32_PINMUX_AF('A', 15, AF2) 460 461 /* TIMER1_CH1 */ 462 #define TIMER1_CH1_PA1 \ 463 GD32_PINMUX_AF('A', 1, AF2) 464 #define TIMER1_CH1_PB3 \ 465 GD32_PINMUX_AF('B', 3, AF2) 466 467 /* TIMER1_CH2 */ 468 #define TIMER1_CH2_PA2 \ 469 GD32_PINMUX_AF('A', 2, AF2) 470 #define TIMER1_CH2_PB10 \ 471 GD32_PINMUX_AF('B', 10, AF2) 472 473 /* TIMER1_CH3 */ 474 #define TIMER1_CH3_PA3 \ 475 GD32_PINMUX_AF('A', 3, AF2) 476 #define TIMER1_CH3_PB11 \ 477 GD32_PINMUX_AF('B', 11, AF2) 478 479 /* TIMER1_ETI */ 480 #define TIMER1_ETI_PA0 \ 481 GD32_PINMUX_AF('A', 0, AF2) 482 #define TIMER1_ETI_PA5 \ 483 GD32_PINMUX_AF('A', 5, AF2) 484 #define TIMER1_ETI_PA15 \ 485 GD32_PINMUX_AF('A', 15, AF2) 486 487 /* TIMER2_CH0 */ 488 #define TIMER2_CH0_PA6 \ 489 GD32_PINMUX_AF('A', 6, AF1) 490 #define TIMER2_CH0_PB4 \ 491 GD32_PINMUX_AF('B', 4, AF1) 492 #define TIMER2_CH0_PC6 \ 493 GD32_PINMUX_AF('C', 6, AF0) 494 495 /* TIMER2_CH1 */ 496 #define TIMER2_CH1_PA7 \ 497 GD32_PINMUX_AF('A', 7, AF1) 498 #define TIMER2_CH1_PB5 \ 499 GD32_PINMUX_AF('B', 5, AF1) 500 #define TIMER2_CH1_PC7 \ 501 GD32_PINMUX_AF('C', 7, AF0) 502 503 /* TIMER2_CH2 */ 504 #define TIMER2_CH2_PB0 \ 505 GD32_PINMUX_AF('B', 0, AF1) 506 #define TIMER2_CH2_PC8 \ 507 GD32_PINMUX_AF('C', 8, AF0) 508 509 /* TIMER2_CH3 */ 510 #define TIMER2_CH3_PB1 \ 511 GD32_PINMUX_AF('B', 1, AF1) 512 #define TIMER2_CH3_PC9 \ 513 GD32_PINMUX_AF('C', 9, AF0) 514 515 /* TIMER2_ETI */ 516 #define TIMER2_ETI_PD2 \ 517 GD32_PINMUX_AF('D', 2, AF0) 518 519 /* TSITG */ 520 #define TSITG_PB8 \ 521 GD32_PINMUX_AF('B', 8, AF3) 522 #define TSITG_PB10 \ 523 GD32_PINMUX_AF('B', 10, AF3) 524 525 /* TSI_G0_IO0 */ 526 #define TSI_G0_IO0_PA0 \ 527 GD32_PINMUX_AF('A', 0, AF3) 528 529 /* TSI_G0_IO1 */ 530 #define TSI_G0_IO1_PA1 \ 531 GD32_PINMUX_AF('A', 1, AF3) 532 533 /* TSI_G0_IO2 */ 534 #define TSI_G0_IO2_PA2 \ 535 GD32_PINMUX_AF('A', 2, AF3) 536 537 /* TSI_G0_IO3 */ 538 #define TSI_G0_IO3_PA3 \ 539 GD32_PINMUX_AF('A', 3, AF3) 540 541 /* TSI_G1_IO0 */ 542 #define TSI_G1_IO0_PA4 \ 543 GD32_PINMUX_AF('A', 4, AF3) 544 545 /* TSI_G1_IO1 */ 546 #define TSI_G1_IO1_PA5 \ 547 GD32_PINMUX_AF('A', 5, AF3) 548 549 /* TSI_G1_IO2 */ 550 #define TSI_G1_IO2_PA6 \ 551 GD32_PINMUX_AF('A', 6, AF3) 552 553 /* TSI_G1_IO3 */ 554 #define TSI_G1_IO3_PA7 \ 555 GD32_PINMUX_AF('A', 7, AF3) 556 557 /* TSI_G2_IO0 */ 558 #define TSI_G2_IO0_PC5 \ 559 GD32_PINMUX_AF('C', 5, AF0) 560 561 /* TSI_G2_IO1 */ 562 #define TSI_G2_IO1_PB0 \ 563 GD32_PINMUX_AF('B', 0, AF3) 564 565 /* TSI_G2_IO2 */ 566 #define TSI_G2_IO2_PB1 \ 567 GD32_PINMUX_AF('B', 1, AF3) 568 569 /* TSI_G2_IO3 */ 570 #define TSI_G2_IO3_PB2 \ 571 GD32_PINMUX_AF('B', 2, AF3) 572 573 /* TSI_G3_IO0 */ 574 #define TSI_G3_IO0_PA9 \ 575 GD32_PINMUX_AF('A', 9, AF3) 576 577 /* TSI_G3_IO1 */ 578 #define TSI_G3_IO1_PA10 \ 579 GD32_PINMUX_AF('A', 10, AF3) 580 581 /* TSI_G3_IO2 */ 582 #define TSI_G3_IO2_PA11 \ 583 GD32_PINMUX_AF('A', 11, AF3) 584 585 /* TSI_G3_IO3 */ 586 #define TSI_G3_IO3_PA12 \ 587 GD32_PINMUX_AF('A', 12, AF3) 588 589 /* TSI_G4_IO0 */ 590 #define TSI_G4_IO0_PB3 \ 591 GD32_PINMUX_AF('B', 3, AF3) 592 593 /* TSI_G4_IO1 */ 594 #define TSI_G4_IO1_PB4 \ 595 GD32_PINMUX_AF('B', 4, AF3) 596 597 /* TSI_G4_IO2 */ 598 #define TSI_G4_IO2_PB6 \ 599 GD32_PINMUX_AF('B', 6, AF3) 600 601 /* TSI_G4_IO3 */ 602 #define TSI_G4_IO3_PB7 \ 603 GD32_PINMUX_AF('B', 7, AF3) 604 605 /* TSI_G5_IO0 */ 606 #define TSI_G5_IO0_PB11 \ 607 GD32_PINMUX_AF('B', 11, AF3) 608 609 /* TSI_G5_IO1 */ 610 #define TSI_G5_IO1_PB12 \ 611 GD32_PINMUX_AF('B', 12, AF3) 612 613 /* TSI_G5_IO2 */ 614 #define TSI_G5_IO2_PB13 \ 615 GD32_PINMUX_AF('B', 13, AF3) 616 617 /* TSI_G5_IO3 */ 618 #define TSI_G5_IO3_PB14 \ 619 GD32_PINMUX_AF('B', 14, AF3) 620 621 /* USART0_CK */ 622 #define USART0_CK_PA4 \ 623 GD32_PINMUX_AF('A', 4, AF1) 624 #define USART0_CK_PA8 \ 625 GD32_PINMUX_AF('A', 8, AF1) 626 627 /* USART0_CTS */ 628 #define USART0_CTS_PA0 \ 629 GD32_PINMUX_AF('A', 0, AF1) 630 #define USART0_CTS_PA11 \ 631 GD32_PINMUX_AF('A', 11, AF1) 632 633 /* USART0_RTS */ 634 #define USART0_RTS_PA1 \ 635 GD32_PINMUX_AF('A', 1, AF1) 636 #define USART0_RTS_PA12 \ 637 GD32_PINMUX_AF('A', 12, AF1) 638 639 /* USART0_RX */ 640 #define USART0_RX_PA3 \ 641 GD32_PINMUX_AF('A', 3, AF1) 642 #define USART0_RX_PA10 \ 643 GD32_PINMUX_AF('A', 10, AF1) 644 #define USART0_RX_PA15 \ 645 GD32_PINMUX_AF('A', 15, AF1) 646 #define USART0_RX_PB7 \ 647 GD32_PINMUX_AF('B', 7, AF0) 648 649 /* USART0_TX */ 650 #define USART0_TX_PA2 \ 651 GD32_PINMUX_AF('A', 2, AF1) 652 #define USART0_TX_PA9 \ 653 GD32_PINMUX_AF('A', 9, AF1) 654 #define USART0_TX_PA14 \ 655 GD32_PINMUX_AF('A', 14, AF1) 656 #define USART0_TX_PB6 \ 657 GD32_PINMUX_AF('B', 6, AF0) 658 659 /* USART1_CK */ 660 #define USART1_CK_PA4 \ 661 GD32_PINMUX_AF('A', 4, AF1) 662 663 /* USART1_CTS */ 664 #define USART1_CTS_PA0 \ 665 GD32_PINMUX_AF('A', 0, AF1) 666 667 /* USART1_RTS */ 668 #define USART1_RTS_PA1 \ 669 GD32_PINMUX_AF('A', 1, AF1) 670 671 /* USART1_RX */ 672 #define USART1_RX_PA3 \ 673 GD32_PINMUX_AF('A', 3, AF1) 674 #define USART1_RX_PA15 \ 675 GD32_PINMUX_AF('A', 15, AF1) 676 #define USART1_RX_PB0 \ 677 GD32_PINMUX_AF('B', 0, AF4) 678 679 /* USART1_TX */ 680 #define USART1_TX_PA2 \ 681 GD32_PINMUX_AF('A', 2, AF1) 682 #define USART1_TX_PA8 \ 683 GD32_PINMUX_AF('A', 8, AF4) 684 #define USART1_TX_PA14 \ 685 GD32_PINMUX_AF('A', 14, AF1) 686 687 /* USBFS_ID */ 688 #define USBFS_ID_PA10 \ 689 GD32_PINMUX_AF('A', 10, AF5) 690 691 /* USBFS_SOF */ 692 #define USBFS_SOF_PA8 \ 693 GD32_PINMUX_AF('A', 8, AF5) 694 695 /* USBFS_VBUS */ 696 #define USBFS_VBUS_PA9 \ 697 GD32_PINMUX_AF('A', 9, AF5) 698
