1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32-af.h" 8 9 /* ADC_IN0 */ 10 #define ADC_IN0_PA0 \ 11 GD32_PINMUX_AF('A', 0, ANALOG) 12 13 /* ADC_IN1 */ 14 #define ADC_IN1_PA1 \ 15 GD32_PINMUX_AF('A', 1, ANALOG) 16 17 /* ADC_IN2 */ 18 #define ADC_IN2_PA2 \ 19 GD32_PINMUX_AF('A', 2, ANALOG) 20 21 /* ADC_IN3 */ 22 #define ADC_IN3_PA3 \ 23 GD32_PINMUX_AF('A', 3, ANALOG) 24 25 /* ADC_IN4 */ 26 #define ADC_IN4_PA4 \ 27 GD32_PINMUX_AF('A', 4, ANALOG) 28 29 /* ADC_IN5 */ 30 #define ADC_IN5_PA5 \ 31 GD32_PINMUX_AF('A', 5, ANALOG) 32 33 /* ADC_IN6 */ 34 #define ADC_IN6_PA6 \ 35 GD32_PINMUX_AF('A', 6, ANALOG) 36 37 /* ADC_IN7 */ 38 #define ADC_IN7_PA7 \ 39 GD32_PINMUX_AF('A', 7, ANALOG) 40 41 /* ADC_IN8 */ 42 #define ADC_IN8_PB0 \ 43 GD32_PINMUX_AF('B', 0, ANALOG) 44 45 /* ADC_IN9 */ 46 #define ADC_IN9_PB1 \ 47 GD32_PINMUX_AF('B', 1, ANALOG) 48 49 /* ANALOG */ 50 #define ANALOG_PA0 \ 51 GD32_PINMUX_AF('A', 0, ANALOG) 52 #define ANALOG_PA1 \ 53 GD32_PINMUX_AF('A', 1, ANALOG) 54 #define ANALOG_PA2 \ 55 GD32_PINMUX_AF('A', 2, ANALOG) 56 #define ANALOG_PA3 \ 57 GD32_PINMUX_AF('A', 3, ANALOG) 58 #define ANALOG_PA4 \ 59 GD32_PINMUX_AF('A', 4, ANALOG) 60 #define ANALOG_PA5 \ 61 GD32_PINMUX_AF('A', 5, ANALOG) 62 #define ANALOG_PA6 \ 63 GD32_PINMUX_AF('A', 6, ANALOG) 64 #define ANALOG_PA7 \ 65 GD32_PINMUX_AF('A', 7, ANALOG) 66 #define ANALOG_PA9 \ 67 GD32_PINMUX_AF('A', 9, ANALOG) 68 #define ANALOG_PA10 \ 69 GD32_PINMUX_AF('A', 10, ANALOG) 70 #define ANALOG_PA11 \ 71 GD32_PINMUX_AF('A', 11, ANALOG) 72 #define ANALOG_PA12 \ 73 GD32_PINMUX_AF('A', 12, ANALOG) 74 #define ANALOG_PA13 \ 75 GD32_PINMUX_AF('A', 13, ANALOG) 76 #define ANALOG_PA14 \ 77 GD32_PINMUX_AF('A', 14, ANALOG) 78 #define ANALOG_PA15 \ 79 GD32_PINMUX_AF('A', 15, ANALOG) 80 #define ANALOG_PB0 \ 81 GD32_PINMUX_AF('B', 0, ANALOG) 82 #define ANALOG_PB1 \ 83 GD32_PINMUX_AF('B', 1, ANALOG) 84 #define ANALOG_PB3 \ 85 GD32_PINMUX_AF('B', 3, ANALOG) 86 #define ANALOG_PB4 \ 87 GD32_PINMUX_AF('B', 4, ANALOG) 88 #define ANALOG_PB5 \ 89 GD32_PINMUX_AF('B', 5, ANALOG) 90 #define ANALOG_PB6 \ 91 GD32_PINMUX_AF('B', 6, ANALOG) 92 #define ANALOG_PB7 \ 93 GD32_PINMUX_AF('B', 7, ANALOG) 94 #define ANALOG_PF0 \ 95 GD32_PINMUX_AF('F', 0, ANALOG) 96 97 /* CEC */ 98 #define CEC_PA5 \ 99 GD32_PINMUX_AF('A', 5, AF1) 100 101 /* CMP0_OUT */ 102 #define CMP0_OUT_PA0 \ 103 GD32_PINMUX_AF('A', 0, AF7) 104 #define CMP0_OUT_PA6 \ 105 GD32_PINMUX_AF('A', 6, AF7) 106 #define CMP0_OUT_PA11 \ 107 GD32_PINMUX_AF('A', 11, AF7) 108 109 /* CMP1_OUT */ 110 #define CMP1_OUT_PA2 \ 111 GD32_PINMUX_AF('A', 2, AF7) 112 #define CMP1_OUT_PA7 \ 113 GD32_PINMUX_AF('A', 7, AF7) 114 #define CMP1_OUT_PA12 \ 115 GD32_PINMUX_AF('A', 12, AF7) 116 117 /* CTC_SYNC */ 118 #define CTC_SYNC_PF0 \ 119 GD32_PINMUX_AF('F', 0, AF0) 120 121 /* DAC0_OUT */ 122 #define DAC0_OUT_PA4 \ 123 GD32_PINMUX_AF('A', 4, ANALOG) 124 125 /* EVENTOUT */ 126 #define EVENTOUT_PA1 \ 127 GD32_PINMUX_AF('A', 1, AF0) 128 #define EVENTOUT_PA6 \ 129 GD32_PINMUX_AF('A', 6, AF6) 130 #define EVENTOUT_PA7 \ 131 GD32_PINMUX_AF('A', 7, AF6) 132 #define EVENTOUT_PA11 \ 133 GD32_PINMUX_AF('A', 11, AF0) 134 #define EVENTOUT_PA12 \ 135 GD32_PINMUX_AF('A', 12, AF0) 136 #define EVENTOUT_PA15 \ 137 GD32_PINMUX_AF('A', 15, AF3) 138 #define EVENTOUT_PB0 \ 139 GD32_PINMUX_AF('B', 0, AF0) 140 #define EVENTOUT_PB3 \ 141 GD32_PINMUX_AF('B', 3, AF1) 142 #define EVENTOUT_PB4 \ 143 GD32_PINMUX_AF('B', 4, AF2) 144 145 /* I2C0_SCL */ 146 #define I2C0_SCL_PA9 \ 147 GD32_PINMUX_AF('A', 9, AF4) 148 #define I2C0_SCL_PB6 \ 149 GD32_PINMUX_AF('B', 6, AF1) 150 151 /* I2C0_SDA */ 152 #define I2C0_SDA_PA10 \ 153 GD32_PINMUX_AF('A', 10, AF4) 154 #define I2C0_SDA_PB7 \ 155 GD32_PINMUX_AF('B', 7, AF1) 156 157 /* I2C0_SMBA */ 158 #define I2C0_SMBA_PB5 \ 159 GD32_PINMUX_AF('B', 5, AF3) 160 161 /* I2C1_SCL */ 162 #define I2C1_SCL_PA0 \ 163 GD32_PINMUX_AF('A', 0, AF4) 164 165 /* I2C1_SDA */ 166 #define I2C1_SDA_PA1 \ 167 GD32_PINMUX_AF('A', 1, AF4) 168 169 /* I2S0_CK */ 170 #define I2S0_CK_PA5 \ 171 GD32_PINMUX_AF('A', 5, AF0) 172 #define I2S0_CK_PB3 \ 173 GD32_PINMUX_AF('B', 3, AF0) 174 175 /* I2S0_MCK */ 176 #define I2S0_MCK_PA6 \ 177 GD32_PINMUX_AF('A', 6, AF0) 178 #define I2S0_MCK_PB4 \ 179 GD32_PINMUX_AF('B', 4, AF0) 180 181 /* I2S0_SD */ 182 #define I2S0_SD_PA7 \ 183 GD32_PINMUX_AF('A', 7, AF0) 184 #define I2S0_SD_PB5 \ 185 GD32_PINMUX_AF('B', 5, AF0) 186 187 /* I2S0_WS */ 188 #define I2S0_WS_PA4 \ 189 GD32_PINMUX_AF('A', 4, AF0) 190 #define I2S0_WS_PA15 \ 191 GD32_PINMUX_AF('A', 15, AF0) 192 193 /* IFRP_OUT */ 194 #define IFRP_OUT_PA13 \ 195 GD32_PINMUX_AF('A', 13, AF1) 196 197 /* SPI0_MISO */ 198 #define SPI0_MISO_PA6 \ 199 GD32_PINMUX_AF('A', 6, AF0) 200 #define SPI0_MISO_PB4 \ 201 GD32_PINMUX_AF('B', 4, AF0) 202 203 /* SPI0_MOSI */ 204 #define SPI0_MOSI_PA7 \ 205 GD32_PINMUX_AF('A', 7, AF0) 206 #define SPI0_MOSI_PB5 \ 207 GD32_PINMUX_AF('B', 5, AF0) 208 209 /* SPI0_NSS */ 210 #define SPI0_NSS_PA4 \ 211 GD32_PINMUX_AF('A', 4, AF0) 212 #define SPI0_NSS_PA15 \ 213 GD32_PINMUX_AF('A', 15, AF0) 214 215 /* SPI0_SCK */ 216 #define SPI0_SCK_PA5 \ 217 GD32_PINMUX_AF('A', 5, AF0) 218 #define SPI0_SCK_PB3 \ 219 GD32_PINMUX_AF('B', 3, AF0) 220 221 /* SPI1_IO2 */ 222 #define SPI1_IO2_PA11 \ 223 GD32_PINMUX_AF('A', 11, AF6) 224 225 /* SPI1_IO3 */ 226 #define SPI1_IO3_PA12 \ 227 GD32_PINMUX_AF('A', 12, AF6) 228 229 /* SPI1_MISO */ 230 #define SPI1_MISO_PA13 \ 231 GD32_PINMUX_AF('A', 13, AF6) 232 233 /* SPI1_MOSI */ 234 #define SPI1_MOSI_PA14 \ 235 GD32_PINMUX_AF('A', 14, AF6) 236 237 /* SPI1_NSS */ 238 #define SPI1_NSS_PA4 \ 239 GD32_PINMUX_AF('A', 4, AF6) 240 #define SPI1_NSS_PA15 \ 241 GD32_PINMUX_AF('A', 15, AF6) 242 243 /* SPI1_SCK */ 244 #define SPI1_SCK_PB1 \ 245 GD32_PINMUX_AF('B', 1, AF6) 246 247 /* SWCLK */ 248 #define SWCLK_PA14 \ 249 GD32_PINMUX_AF('A', 14, AF0) 250 251 /* SWDIO */ 252 #define SWDIO_PA13 \ 253 GD32_PINMUX_AF('A', 13, AF0) 254 255 /* TIMER0_BKIN */ 256 #define TIMER0_BKIN_PA6 \ 257 GD32_PINMUX_AF('A', 6, AF2) 258 259 /* TIMER0_CH0_ON */ 260 #define TIMER0_CH0_ON_PA7 \ 261 GD32_PINMUX_AF('A', 7, AF2) 262 263 /* TIMER0_CH1 */ 264 #define TIMER0_CH1_PA9 \ 265 GD32_PINMUX_AF('A', 9, AF2) 266 267 /* TIMER0_CH1_ON */ 268 #define TIMER0_CH1_ON_PB0 \ 269 GD32_PINMUX_AF('B', 0, AF2) 270 271 /* TIMER0_CH2 */ 272 #define TIMER0_CH2_PA10 \ 273 GD32_PINMUX_AF('A', 10, AF2) 274 275 /* TIMER0_CH2_ON */ 276 #define TIMER0_CH2_ON_PB1 \ 277 GD32_PINMUX_AF('B', 1, AF2) 278 279 /* TIMER0_CH3 */ 280 #define TIMER0_CH3_PA11 \ 281 GD32_PINMUX_AF('A', 11, AF2) 282 283 /* TIMER0_ETI */ 284 #define TIMER0_ETI_PA12 \ 285 GD32_PINMUX_AF('A', 12, AF2) 286 287 /* TIMER13_CH0 */ 288 #define TIMER13_CH0_PA4 \ 289 GD32_PINMUX_AF('A', 4, AF4) 290 #define TIMER13_CH0_PA7 \ 291 GD32_PINMUX_AF('A', 7, AF4) 292 #define TIMER13_CH0_PB1 \ 293 GD32_PINMUX_AF('B', 1, AF0) 294 295 /* TIMER14_BKIN */ 296 #define TIMER14_BKIN_PA9 \ 297 GD32_PINMUX_AF('A', 9, AF0) 298 299 /* TIMER14_CH0 */ 300 #define TIMER14_CH0_PA2 \ 301 GD32_PINMUX_AF('A', 2, AF0) 302 303 /* TIMER14_CH1 */ 304 #define TIMER14_CH1_PA3 \ 305 GD32_PINMUX_AF('A', 3, AF0) 306 307 /* TIMER15_BKIN */ 308 #define TIMER15_BKIN_PB5 \ 309 GD32_PINMUX_AF('B', 5, AF2) 310 311 /* TIMER15_CH0 */ 312 #define TIMER15_CH0_PA6 \ 313 GD32_PINMUX_AF('A', 6, AF5) 314 315 /* TIMER15_CH0_ON */ 316 #define TIMER15_CH0_ON_PB6 \ 317 GD32_PINMUX_AF('B', 6, AF2) 318 319 /* TIMER16_BKIN */ 320 #define TIMER16_BKIN_PA10 \ 321 GD32_PINMUX_AF('A', 10, AF0) 322 323 /* TIMER16_CH0 */ 324 #define TIMER16_CH0_PA7 \ 325 GD32_PINMUX_AF('A', 7, AF5) 326 327 /* TIMER16_CH0_ON */ 328 #define TIMER16_CH0_ON_PB7 \ 329 GD32_PINMUX_AF('B', 7, AF2) 330 331 /* TIMER1_CH0 */ 332 #define TIMER1_CH0_PA0 \ 333 GD32_PINMUX_AF('A', 0, AF2) 334 #define TIMER1_CH0_PA5 \ 335 GD32_PINMUX_AF('A', 5, AF2) 336 #define TIMER1_CH0_PA15 \ 337 GD32_PINMUX_AF('A', 15, AF2) 338 339 /* TIMER1_CH1 */ 340 #define TIMER1_CH1_PA1 \ 341 GD32_PINMUX_AF('A', 1, AF2) 342 #define TIMER1_CH1_PB3 \ 343 GD32_PINMUX_AF('B', 3, AF2) 344 345 /* TIMER1_CH2 */ 346 #define TIMER1_CH2_PA2 \ 347 GD32_PINMUX_AF('A', 2, AF2) 348 349 /* TIMER1_CH3 */ 350 #define TIMER1_CH3_PA3 \ 351 GD32_PINMUX_AF('A', 3, AF2) 352 353 /* TIMER1_ETI */ 354 #define TIMER1_ETI_PA0 \ 355 GD32_PINMUX_AF('A', 0, AF2) 356 #define TIMER1_ETI_PA5 \ 357 GD32_PINMUX_AF('A', 5, AF2) 358 #define TIMER1_ETI_PA15 \ 359 GD32_PINMUX_AF('A', 15, AF2) 360 361 /* TIMER2_CH0 */ 362 #define TIMER2_CH0_PA6 \ 363 GD32_PINMUX_AF('A', 6, AF1) 364 #define TIMER2_CH0_PB4 \ 365 GD32_PINMUX_AF('B', 4, AF1) 366 367 /* TIMER2_CH1 */ 368 #define TIMER2_CH1_PA7 \ 369 GD32_PINMUX_AF('A', 7, AF1) 370 #define TIMER2_CH1_PB5 \ 371 GD32_PINMUX_AF('B', 5, AF1) 372 373 /* TIMER2_CH2 */ 374 #define TIMER2_CH2_PB0 \ 375 GD32_PINMUX_AF('B', 0, AF1) 376 377 /* TIMER2_CH3 */ 378 #define TIMER2_CH3_PB1 \ 379 GD32_PINMUX_AF('B', 1, AF1) 380 381 /* TSI_G0_IO0 */ 382 #define TSI_G0_IO0_PA0 \ 383 GD32_PINMUX_AF('A', 0, AF3) 384 385 /* TSI_G0_IO1 */ 386 #define TSI_G0_IO1_PA1 \ 387 GD32_PINMUX_AF('A', 1, AF3) 388 389 /* TSI_G0_IO2 */ 390 #define TSI_G0_IO2_PA2 \ 391 GD32_PINMUX_AF('A', 2, AF3) 392 393 /* TSI_G0_IO3 */ 394 #define TSI_G0_IO3_PA3 \ 395 GD32_PINMUX_AF('A', 3, AF3) 396 397 /* TSI_G1_IO0 */ 398 #define TSI_G1_IO0_PA4 \ 399 GD32_PINMUX_AF('A', 4, AF3) 400 401 /* TSI_G1_IO1 */ 402 #define TSI_G1_IO1_PA5 \ 403 GD32_PINMUX_AF('A', 5, AF3) 404 405 /* TSI_G1_IO2 */ 406 #define TSI_G1_IO2_PA6 \ 407 GD32_PINMUX_AF('A', 6, AF3) 408 409 /* TSI_G1_IO3 */ 410 #define TSI_G1_IO3_PA7 \ 411 GD32_PINMUX_AF('A', 7, AF3) 412 413 /* TSI_G2_IO1 */ 414 #define TSI_G2_IO1_PB0 \ 415 GD32_PINMUX_AF('B', 0, AF3) 416 417 /* TSI_G2_IO2 */ 418 #define TSI_G2_IO2_PB1 \ 419 GD32_PINMUX_AF('B', 1, AF3) 420 421 /* TSI_G3_IO0 */ 422 #define TSI_G3_IO0_PA9 \ 423 GD32_PINMUX_AF('A', 9, AF3) 424 425 /* TSI_G3_IO1 */ 426 #define TSI_G3_IO1_PA10 \ 427 GD32_PINMUX_AF('A', 10, AF3) 428 429 /* TSI_G3_IO2 */ 430 #define TSI_G3_IO2_PA11 \ 431 GD32_PINMUX_AF('A', 11, AF3) 432 433 /* TSI_G3_IO3 */ 434 #define TSI_G3_IO3_PA12 \ 435 GD32_PINMUX_AF('A', 12, AF3) 436 437 /* TSI_G4_IO0 */ 438 #define TSI_G4_IO0_PB3 \ 439 GD32_PINMUX_AF('B', 3, AF3) 440 441 /* TSI_G4_IO1 */ 442 #define TSI_G4_IO1_PB4 \ 443 GD32_PINMUX_AF('B', 4, AF3) 444 445 /* TSI_G4_IO2 */ 446 #define TSI_G4_IO2_PB6 \ 447 GD32_PINMUX_AF('B', 6, AF3) 448 449 /* TSI_G4_IO3 */ 450 #define TSI_G4_IO3_PB7 \ 451 GD32_PINMUX_AF('B', 7, AF3) 452 453 /* USART0_CK */ 454 #define USART0_CK_PA4 \ 455 GD32_PINMUX_AF('A', 4, AF1) 456 457 /* USART0_CTS */ 458 #define USART0_CTS_PA0 \ 459 GD32_PINMUX_AF('A', 0, AF1) 460 #define USART0_CTS_PA11 \ 461 GD32_PINMUX_AF('A', 11, AF1) 462 463 /* USART0_RTS */ 464 #define USART0_RTS_PA1 \ 465 GD32_PINMUX_AF('A', 1, AF1) 466 #define USART0_RTS_PA12 \ 467 GD32_PINMUX_AF('A', 12, AF1) 468 469 /* USART0_RX */ 470 #define USART0_RX_PA3 \ 471 GD32_PINMUX_AF('A', 3, AF1) 472 #define USART0_RX_PA10 \ 473 GD32_PINMUX_AF('A', 10, AF1) 474 #define USART0_RX_PA15 \ 475 GD32_PINMUX_AF('A', 15, AF1) 476 #define USART0_RX_PB7 \ 477 GD32_PINMUX_AF('B', 7, AF0) 478 479 /* USART0_TX */ 480 #define USART0_TX_PA2 \ 481 GD32_PINMUX_AF('A', 2, AF1) 482 #define USART0_TX_PA9 \ 483 GD32_PINMUX_AF('A', 9, AF1) 484 #define USART0_TX_PA14 \ 485 GD32_PINMUX_AF('A', 14, AF1) 486 #define USART0_TX_PB6 \ 487 GD32_PINMUX_AF('B', 6, AF0) 488 489 /* USART1_CK */ 490 #define USART1_CK_PA4 \ 491 GD32_PINMUX_AF('A', 4, AF1) 492 493 /* USART1_CTS */ 494 #define USART1_CTS_PA0 \ 495 GD32_PINMUX_AF('A', 0, AF1) 496 497 /* USART1_RTS */ 498 #define USART1_RTS_PA1 \ 499 GD32_PINMUX_AF('A', 1, AF1) 500 501 /* USART1_RX */ 502 #define USART1_RX_PA3 \ 503 GD32_PINMUX_AF('A', 3, AF1) 504 #define USART1_RX_PA15 \ 505 GD32_PINMUX_AF('A', 15, AF1) 506 #define USART1_RX_PB0 \ 507 GD32_PINMUX_AF('B', 0, AF4) 508 509 /* USART1_TX */ 510 #define USART1_TX_PA2 \ 511 GD32_PINMUX_AF('A', 2, AF1) 512 #define USART1_TX_PA14 \ 513 GD32_PINMUX_AF('A', 14, AF1) 514 515 /* USBFS_ID */ 516 #define USBFS_ID_PA10 \ 517 GD32_PINMUX_AF('A', 10, AF5) 518 519 /* USBFS_VBUS */ 520 #define USBFS_VBUS_PA9 \ 521 GD32_PINMUX_AF('A', 9, AF5) 522
