1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32e103xx-afio.h" 8 9 /* ADC01_IN0 */ 10 #define ADC01_IN0_PA0 \ 11 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 12 13 /* ADC01_IN1 */ 14 #define ADC01_IN1_PA1 \ 15 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 16 17 /* ADC01_IN10 */ 18 #define ADC01_IN10_PC0 \ 19 GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) 20 21 /* ADC01_IN11 */ 22 #define ADC01_IN11_PC1 \ 23 GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) 24 25 /* ADC01_IN12 */ 26 #define ADC01_IN12_PC2 \ 27 GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) 28 29 /* ADC01_IN13 */ 30 #define ADC01_IN13_PC3 \ 31 GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) 32 33 /* ADC01_IN14 */ 34 #define ADC01_IN14_PC4 \ 35 GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) 36 37 /* ADC01_IN15 */ 38 #define ADC01_IN15_PC5 \ 39 GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) 40 41 /* ADC01_IN2 */ 42 #define ADC01_IN2_PA2 \ 43 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 44 45 /* ADC01_IN3 */ 46 #define ADC01_IN3_PA3 \ 47 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 48 49 /* ADC01_IN4 */ 50 #define ADC01_IN4_PA4 \ 51 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 52 53 /* ADC01_IN5 */ 54 #define ADC01_IN5_PA5 \ 55 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 56 57 /* ADC01_IN6 */ 58 #define ADC01_IN6_PA6 \ 59 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 60 61 /* ADC01_IN7 */ 62 #define ADC01_IN7_PA7 \ 63 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 64 65 /* ADC01_IN8 */ 66 #define ADC01_IN8_PB0 \ 67 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 68 69 /* ADC01_IN9 */ 70 #define ADC01_IN9_PB1 \ 71 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 72 73 /* ANALOG */ 74 #define ANALOG_PA0 \ 75 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 76 #define ANALOG_PA1 \ 77 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 78 #define ANALOG_PA2 \ 79 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 80 #define ANALOG_PA3 \ 81 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 82 #define ANALOG_PA4 \ 83 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 84 #define ANALOG_PA5 \ 85 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 86 #define ANALOG_PA6 \ 87 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 88 #define ANALOG_PA7 \ 89 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 90 #define ANALOG_PA8 \ 91 GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) 92 #define ANALOG_PA9 \ 93 GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) 94 #define ANALOG_PA10 \ 95 GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) 96 #define ANALOG_PA11 \ 97 GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) 98 #define ANALOG_PA12 \ 99 GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) 100 #define ANALOG_PA13 \ 101 GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) 102 #define ANALOG_PA14 \ 103 GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) 104 #define ANALOG_PA15 \ 105 GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) 106 #define ANALOG_PB0 \ 107 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 108 #define ANALOG_PB1 \ 109 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 110 #define ANALOG_PB2 \ 111 GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) 112 #define ANALOG_PB3 \ 113 GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) 114 #define ANALOG_PB4 \ 115 GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) 116 #define ANALOG_PB5 \ 117 GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) 118 #define ANALOG_PB6 \ 119 GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) 120 #define ANALOG_PB7 \ 121 GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) 122 #define ANALOG_PB8 \ 123 GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) 124 #define ANALOG_PB9 \ 125 GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) 126 #define ANALOG_PB10 \ 127 GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) 128 #define ANALOG_PB11 \ 129 GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) 130 #define ANALOG_PB12 \ 131 GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) 132 #define ANALOG_PB13 \ 133 GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) 134 #define ANALOG_PB14 \ 135 GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) 136 #define ANALOG_PB15 \ 137 GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) 138 #define ANALOG_PC0 \ 139 GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) 140 #define ANALOG_PC1 \ 141 GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) 142 #define ANALOG_PC2 \ 143 GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) 144 #define ANALOG_PC3 \ 145 GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) 146 #define ANALOG_PC4 \ 147 GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) 148 #define ANALOG_PC5 \ 149 GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) 150 #define ANALOG_PC6 \ 151 GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP) 152 #define ANALOG_PC7 \ 153 GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP) 154 #define ANALOG_PC8 \ 155 GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP) 156 #define ANALOG_PC9 \ 157 GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP) 158 #define ANALOG_PC10 \ 159 GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP) 160 #define ANALOG_PC11 \ 161 GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP) 162 #define ANALOG_PC12 \ 163 GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP) 164 #define ANALOG_PC13 \ 165 GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) 166 #define ANALOG_PC14 \ 167 GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) 168 #define ANALOG_PC15 \ 169 GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) 170 #define ANALOG_PD0 \ 171 GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) 172 #define ANALOG_PD1 \ 173 GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) 174 #define ANALOG_PD2 \ 175 GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP) 176 #define ANALOG_PD3 \ 177 GD32_PINMUX_AFIO('D', 3, ANALOG, NORMP) 178 #define ANALOG_PD4 \ 179 GD32_PINMUX_AFIO('D', 4, ANALOG, NORMP) 180 #define ANALOG_PD5 \ 181 GD32_PINMUX_AFIO('D', 5, ANALOG, NORMP) 182 #define ANALOG_PD6 \ 183 GD32_PINMUX_AFIO('D', 6, ANALOG, NORMP) 184 #define ANALOG_PD7 \ 185 GD32_PINMUX_AFIO('D', 7, ANALOG, NORMP) 186 #define ANALOG_PD8 \ 187 GD32_PINMUX_AFIO('D', 8, ANALOG, NORMP) 188 #define ANALOG_PD9 \ 189 GD32_PINMUX_AFIO('D', 9, ANALOG, NORMP) 190 #define ANALOG_PD10 \ 191 GD32_PINMUX_AFIO('D', 10, ANALOG, NORMP) 192 #define ANALOG_PD11 \ 193 GD32_PINMUX_AFIO('D', 11, ANALOG, NORMP) 194 #define ANALOG_PD12 \ 195 GD32_PINMUX_AFIO('D', 12, ANALOG, NORMP) 196 #define ANALOG_PD13 \ 197 GD32_PINMUX_AFIO('D', 13, ANALOG, NORMP) 198 #define ANALOG_PD14 \ 199 GD32_PINMUX_AFIO('D', 14, ANALOG, NORMP) 200 #define ANALOG_PD15 \ 201 GD32_PINMUX_AFIO('D', 15, ANALOG, NORMP) 202 #define ANALOG_PE0 \ 203 GD32_PINMUX_AFIO('E', 0, ANALOG, NORMP) 204 #define ANALOG_PE1 \ 205 GD32_PINMUX_AFIO('E', 1, ANALOG, NORMP) 206 #define ANALOG_PE2 \ 207 GD32_PINMUX_AFIO('E', 2, ANALOG, NORMP) 208 #define ANALOG_PE3 \ 209 GD32_PINMUX_AFIO('E', 3, ANALOG, NORMP) 210 #define ANALOG_PE4 \ 211 GD32_PINMUX_AFIO('E', 4, ANALOG, NORMP) 212 #define ANALOG_PE5 \ 213 GD32_PINMUX_AFIO('E', 5, ANALOG, NORMP) 214 #define ANALOG_PE6 \ 215 GD32_PINMUX_AFIO('E', 6, ANALOG, NORMP) 216 #define ANALOG_PE7 \ 217 GD32_PINMUX_AFIO('E', 7, ANALOG, NORMP) 218 #define ANALOG_PE8 \ 219 GD32_PINMUX_AFIO('E', 8, ANALOG, NORMP) 220 #define ANALOG_PE9 \ 221 GD32_PINMUX_AFIO('E', 9, ANALOG, NORMP) 222 #define ANALOG_PE10 \ 223 GD32_PINMUX_AFIO('E', 10, ANALOG, NORMP) 224 #define ANALOG_PE11 \ 225 GD32_PINMUX_AFIO('E', 11, ANALOG, NORMP) 226 #define ANALOG_PE12 \ 227 GD32_PINMUX_AFIO('E', 12, ANALOG, NORMP) 228 #define ANALOG_PE13 \ 229 GD32_PINMUX_AFIO('E', 13, ANALOG, NORMP) 230 #define ANALOG_PE14 \ 231 GD32_PINMUX_AFIO('E', 14, ANALOG, NORMP) 232 #define ANALOG_PE15 \ 233 GD32_PINMUX_AFIO('E', 15, ANALOG, NORMP) 234 235 /* CK_OUT0 */ 236 #define CK_OUT0_PA8 \ 237 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 238 239 /* CTC_SYNC */ 240 #define CTC_SYNC_PA8 \ 241 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 242 243 /* DAC_OUT0 */ 244 #define DAC_OUT0_PA4 \ 245 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 246 247 /* DAC_OUT1 */ 248 #define DAC_OUT1_PA5 \ 249 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 250 251 /* EXMC_A16 */ 252 #define EXMC_A16_PD11 \ 253 GD32_PINMUX_AFIO('D', 11, ALTERNATE, NORMP) 254 255 /* EXMC_A17 */ 256 #define EXMC_A17_PD12 \ 257 GD32_PINMUX_AFIO('D', 12, ALTERNATE, NORMP) 258 259 /* EXMC_A18 */ 260 #define EXMC_A18_PD13 \ 261 GD32_PINMUX_AFIO('D', 13, ALTERNATE, NORMP) 262 263 /* EXMC_A19 */ 264 #define EXMC_A19_PE3 \ 265 GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP) 266 267 /* EXMC_A20 */ 268 #define EXMC_A20_PE4 \ 269 GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP) 270 271 /* EXMC_A21 */ 272 #define EXMC_A21_PE5 \ 273 GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP) 274 275 /* EXMC_A22 */ 276 #define EXMC_A22_PE6 \ 277 GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP) 278 279 /* EXMC_A23 */ 280 #define EXMC_A23_PE2 \ 281 GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP) 282 283 /* EXMC_CLK */ 284 #define EXMC_CLK_PD3 \ 285 GD32_PINMUX_AFIO('D', 3, ALTERNATE, NORMP) 286 287 /* EXMC_D0 */ 288 #define EXMC_D0_PD14 \ 289 GD32_PINMUX_AFIO('D', 14, ALTERNATE, NORMP) 290 291 /* EXMC_D1 */ 292 #define EXMC_D1_PD15 \ 293 GD32_PINMUX_AFIO('D', 15, ALTERNATE, NORMP) 294 295 /* EXMC_D10 */ 296 #define EXMC_D10_PE13 \ 297 GD32_PINMUX_AFIO('E', 13, ALTERNATE, NORMP) 298 299 /* EXMC_D11 */ 300 #define EXMC_D11_PE14 \ 301 GD32_PINMUX_AFIO('E', 14, ALTERNATE, NORMP) 302 303 /* EXMC_D12 */ 304 #define EXMC_D12_PE15 \ 305 GD32_PINMUX_AFIO('E', 15, ALTERNATE, NORMP) 306 307 /* EXMC_D13 */ 308 #define EXMC_D13_PD8 \ 309 GD32_PINMUX_AFIO('D', 8, ALTERNATE, NORMP) 310 311 /* EXMC_D14 */ 312 #define EXMC_D14_PD9 \ 313 GD32_PINMUX_AFIO('D', 9, ALTERNATE, NORMP) 314 315 /* EXMC_D15 */ 316 #define EXMC_D15_PD10 \ 317 GD32_PINMUX_AFIO('D', 10, ALTERNATE, NORMP) 318 319 /* EXMC_D2 */ 320 #define EXMC_D2_PD0 \ 321 GD32_PINMUX_AFIO('D', 0, ALTERNATE, NORMP) 322 323 /* EXMC_D3 */ 324 #define EXMC_D3_PD1 \ 325 GD32_PINMUX_AFIO('D', 1, ALTERNATE, NORMP) 326 327 /* EXMC_D4 */ 328 #define EXMC_D4_PE7 \ 329 GD32_PINMUX_AFIO('E', 7, ALTERNATE, NORMP) 330 331 /* EXMC_D5 */ 332 #define EXMC_D5_PE8 \ 333 GD32_PINMUX_AFIO('E', 8, ALTERNATE, NORMP) 334 335 /* EXMC_D6 */ 336 #define EXMC_D6_PE9 \ 337 GD32_PINMUX_AFIO('E', 9, ALTERNATE, NORMP) 338 339 /* EXMC_D7 */ 340 #define EXMC_D7_PE10 \ 341 GD32_PINMUX_AFIO('E', 10, ALTERNATE, NORMP) 342 343 /* EXMC_D8 */ 344 #define EXMC_D8_PE11 \ 345 GD32_PINMUX_AFIO('E', 11, ALTERNATE, NORMP) 346 347 /* EXMC_D9 */ 348 #define EXMC_D9_PE12 \ 349 GD32_PINMUX_AFIO('E', 12, ALTERNATE, NORMP) 350 351 /* EXMC_NBL0 */ 352 #define EXMC_NBL0_PE0 \ 353 GD32_PINMUX_AFIO('E', 0, ALTERNATE, NORMP) 354 355 /* EXMC_NBL1 */ 356 #define EXMC_NBL1_PE1 \ 357 GD32_PINMUX_AFIO('E', 1, ALTERNATE, NORMP) 358 359 /* EXMC_NE0 */ 360 #define EXMC_NE0_PD7 \ 361 GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP) 362 363 /* EXMC_NL(NADV) */ 364 #define EXMC_NL(NADV)_PB7 \ 365 GD32_PINMUX_AFIO('B', 7, ALTERNATE, NORMP) 366 367 /* EXMC_NOE */ 368 #define EXMC_NOE_PD4 \ 369 GD32_PINMUX_AFIO('D', 4, ALTERNATE, NORMP) 370 371 /* EXMC_NWAIT */ 372 #define EXMC_NWAIT_PD6 \ 373 GD32_PINMUX_AFIO('D', 6, GPIO_IN, NORMP) 374 375 /* EXMC_NWE */ 376 #define EXMC_NWE_PD5 \ 377 GD32_PINMUX_AFIO('D', 5, ALTERNATE, NORMP) 378 379 /* I2C0_SCL */ 380 #define I2C0_SCL_PB6_NORMP \ 381 GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) 382 #define I2C0_SCL_PB8_RMP \ 383 GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) 384 385 /* I2C0_SDA */ 386 #define I2C0_SDA_PB7_NORMP \ 387 GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) 388 #define I2C0_SDA_PB9_RMP \ 389 GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) 390 391 /* I2C0_SMBA */ 392 #define I2C0_SMBA_PB5 \ 393 GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) 394 395 /* I2C0_TXFRAME */ 396 #define I2C0_TXFRAME_PB4 \ 397 GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP) 398 399 /* I2C1_SCL */ 400 #define I2C1_SCL_PB10 \ 401 GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP) 402 403 /* I2C1_SDA */ 404 #define I2C1_SDA_PB11 \ 405 GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP) 406 407 /* I2C1_SMBA */ 408 #define I2C1_SMBA_PB12 \ 409 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 410 411 /* I2C1_TXFRAME */ 412 #define I2C1_TXFRAME_PB13 \ 413 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 414 415 /* I2S1_CK */ 416 #define I2S1_CK_PB13 \ 417 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 418 419 /* I2S1_MCK */ 420 #define I2S1_MCK_PC6 \ 421 GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) 422 423 /* I2S1_SD */ 424 #define I2S1_SD_PB15_INP \ 425 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 426 #define I2S1_SD_PB15_OUT \ 427 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 428 429 /* I2S1_WS */ 430 #define I2S1_WS_PB12_INP \ 431 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 432 #define I2S1_WS_PB12_OUT \ 433 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 434 435 /* I2S2_CK */ 436 #define I2S2_CK_PB3_NORMP \ 437 GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) 438 #define I2S2_CK_PC10_RMP \ 439 GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP) 440 441 /* I2S2_MCK */ 442 #define I2S2_MCK_PC7 \ 443 GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) 444 445 /* I2S2_SD */ 446 #define I2S2_SD_PB5_INP_NORMP \ 447 GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) 448 #define I2S2_SD_PB5_OUT_NORMP \ 449 GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) 450 #define I2S2_SD_PC12_INP_RMP \ 451 GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP) 452 #define I2S2_SD_PC12_OUT_RMP \ 453 GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP) 454 455 /* I2S2_WS */ 456 #define I2S2_WS_PA15_INP_NORMP \ 457 GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) 458 #define I2S2_WS_PA15_OUT_NORMP \ 459 GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) 460 #define I2S2_WS_PA4_INP_RMP \ 461 GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) 462 #define I2S2_WS_PA4_OUT_RMP \ 463 GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) 464 465 /* RTC_TAMPER */ 466 #define RTC_TAMPER_PC13 \ 467 GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) 468 469 /* SPI0_IO2 */ 470 #define SPI0_IO2_PA2_NORMP \ 471 GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP) 472 #define SPI0_IO2_PB6_RMP \ 473 GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP) 474 475 /* SPI0_IO3 */ 476 #define SPI0_IO3_PA3_NORMP \ 477 GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP) 478 #define SPI0_IO3_PB7_RMP \ 479 GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP) 480 481 /* SPI0_MISO */ 482 #define SPI0_MISO_PA6_INP_NORMP \ 483 GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) 484 #define SPI0_MISO_PA6_OUT_NORMP \ 485 GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) 486 #define SPI0_MISO_PB4_INP_RMP \ 487 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) 488 #define SPI0_MISO_PB4_OUT_RMP \ 489 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) 490 491 /* SPI0_MOSI */ 492 #define SPI0_MOSI_PA7_INP_NORMP \ 493 GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) 494 #define SPI0_MOSI_PA7_OUT_NORMP \ 495 GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) 496 #define SPI0_MOSI_PB5_INP_RMP \ 497 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) 498 #define SPI0_MOSI_PB5_OUT_RMP \ 499 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) 500 501 /* SPI0_NSS */ 502 #define SPI0_NSS_PA4_INP_NORMP \ 503 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) 504 #define SPI0_NSS_PA4_OUT_NORMP \ 505 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) 506 #define SPI0_NSS_PA15_INP_RMP \ 507 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) 508 #define SPI0_NSS_PA15_OUT_RMP \ 509 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) 510 511 /* SPI0_SCK */ 512 #define SPI0_SCK_PA5_INP_NORMP \ 513 GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) 514 #define SPI0_SCK_PA5_OUT_NORMP \ 515 GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) 516 #define SPI0_SCK_PB3_INP_RMP \ 517 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) 518 #define SPI0_SCK_PB3_OUT_RMP \ 519 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) 520 521 /* SPI1_MISO */ 522 #define SPI1_MISO_PB14_INP \ 523 GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) 524 #define SPI1_MISO_PB14_OUT \ 525 GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) 526 527 /* SPI1_MOSI */ 528 #define SPI1_MOSI_PB15_INP \ 529 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 530 #define SPI1_MOSI_PB15_OUT \ 531 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 532 533 /* SPI1_NSS */ 534 #define SPI1_NSS_PB12_INP \ 535 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 536 #define SPI1_NSS_PB12_OUT \ 537 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 538 539 /* SPI1_SCK */ 540 #define SPI1_SCK_PB13_INP \ 541 GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) 542 #define SPI1_SCK_PB13_OUT \ 543 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 544 545 /* SPI2_MISO */ 546 #define SPI2_MISO_PB4_INP_NORMP \ 547 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) 548 #define SPI2_MISO_PB4_OUT_NORMP \ 549 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) 550 #define SPI2_MISO_PC11_INP_RMP \ 551 GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP) 552 #define SPI2_MISO_PC11_OUT_RMP \ 553 GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP) 554 555 /* SPI2_MOSI */ 556 #define SPI2_MOSI_PB5_INP_NORMP \ 557 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) 558 #define SPI2_MOSI_PB5_OUT_NORMP \ 559 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) 560 #define SPI2_MOSI_PC12_INP_RMP \ 561 GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP) 562 #define SPI2_MOSI_PC12_OUT_RMP \ 563 GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP) 564 565 /* SPI2_NSS */ 566 #define SPI2_NSS_PA15_INP_NORMP \ 567 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) 568 #define SPI2_NSS_PA15_OUT_NORMP \ 569 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) 570 #define SPI2_NSS_PA4_INP_RMP \ 571 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) 572 #define SPI2_NSS_PA4_OUT_RMP \ 573 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) 574 575 /* SPI2_SCK */ 576 #define SPI2_SCK_PB3_INP_NORMP \ 577 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) 578 #define SPI2_SCK_PB3_OUT_NORMP \ 579 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) 580 #define SPI2_SCK_PC10_INP_RMP \ 581 GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP) 582 #define SPI2_SCK_PC10_OUT_RMP \ 583 GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP) 584 585 /* TIMER0_BKIN */ 586 #define TIMER0_BKIN_PB12_NORMP \ 587 GD32_PINMUX_AFIO('B', 12, GPIO_IN, TIMER0_NORMP) 588 #define TIMER0_BKIN_PA6_PRMP \ 589 GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER0_PRMP) 590 #define TIMER0_BKIN_PE15_FRMP \ 591 GD32_PINMUX_AFIO('E', 15, GPIO_IN, TIMER0_FRMP) 592 593 /* TIMER0_CH0 */ 594 #define TIMER0_CH0_PA8_INP_NORMP \ 595 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) 596 #define TIMER0_CH0_PA8_OUT_NORMP \ 597 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) 598 #define TIMER0_CH0_PA8_INP_PRMP \ 599 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) 600 #define TIMER0_CH0_PA8_OUT_PRMP \ 601 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) 602 #define TIMER0_CH0_PE9_INP_FRMP \ 603 GD32_PINMUX_AFIO('E', 9, GPIO_IN, TIMER0_FRMP) 604 #define TIMER0_CH0_PE9_OUT_FRMP \ 605 GD32_PINMUX_AFIO('E', 9, ALTERNATE, TIMER0_FRMP) 606 607 /* TIMER0_CH0_ON */ 608 #define TIMER0_CH0_ON_PB13_INP_NORMP \ 609 GD32_PINMUX_AFIO('B', 13, GPIO_IN, TIMER0_NORMP) 610 #define TIMER0_CH0_ON_PB13_OUT_NORMP \ 611 GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) 612 #define TIMER0_CH0_ON_PA7_INP_PRMP \ 613 GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER0_PRMP) 614 #define TIMER0_CH0_ON_PA7_OUT_PRMP \ 615 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) 616 #define TIMER0_CH0_ON_PE8_INP_FRMP \ 617 GD32_PINMUX_AFIO('E', 8, GPIO_IN, TIMER0_FRMP) 618 #define TIMER0_CH0_ON_PE8_OUT_FRMP \ 619 GD32_PINMUX_AFIO('E', 8, ALTERNATE, TIMER0_FRMP) 620 621 /* TIMER0_CH1 */ 622 #define TIMER0_CH1_PA9_INP_NORMP \ 623 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) 624 #define TIMER0_CH1_PA9_OUT_NORMP \ 625 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) 626 #define TIMER0_CH1_PA9_INP_PRMP \ 627 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) 628 #define TIMER0_CH1_PA9_OUT_PRMP \ 629 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) 630 #define TIMER0_CH1_PE11_INP_FRMP \ 631 GD32_PINMUX_AFIO('E', 11, GPIO_IN, TIMER0_FRMP) 632 #define TIMER0_CH1_PE11_OUT_FRMP \ 633 GD32_PINMUX_AFIO('E', 11, ALTERNATE, TIMER0_FRMP) 634 635 /* TIMER0_CH1_ON */ 636 #define TIMER0_CH1_ON_PB14_INP_NORMP \ 637 GD32_PINMUX_AFIO('B', 14, GPIO_IN, TIMER0_NORMP) 638 #define TIMER0_CH1_ON_PB14_OUT_NORMP \ 639 GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) 640 #define TIMER0_CH1_ON_PB0_INP_PRMP \ 641 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER0_PRMP) 642 #define TIMER0_CH1_ON_PB0_OUT_PRMP \ 643 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) 644 #define TIMER0_CH1_ON_PE10_INP_FRMP \ 645 GD32_PINMUX_AFIO('E', 10, GPIO_IN, TIMER0_FRMP) 646 #define TIMER0_CH1_ON_PE10_OUT_FRMP \ 647 GD32_PINMUX_AFIO('E', 10, ALTERNATE, TIMER0_FRMP) 648 649 /* TIMER0_CH2 */ 650 #define TIMER0_CH2_PA10_INP_NORMP \ 651 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) 652 #define TIMER0_CH2_PA10_OUT_NORMP \ 653 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) 654 #define TIMER0_CH2_PA10_INP_PRMP \ 655 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) 656 #define TIMER0_CH2_PA10_OUT_PRMP \ 657 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) 658 #define TIMER0_CH2_PE13_INP_FRMP \ 659 GD32_PINMUX_AFIO('E', 13, GPIO_IN, TIMER0_FRMP) 660 #define TIMER0_CH2_PE13_OUT_FRMP \ 661 GD32_PINMUX_AFIO('E', 13, ALTERNATE, TIMER0_FRMP) 662 663 /* TIMER0_CH2_ON */ 664 #define TIMER0_CH2_ON_PB15_NORMP \ 665 GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) 666 #define TIMER0_CH2_ON_PB1_PRMP \ 667 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) 668 #define TIMER0_CH2_ON_PE12_FRMP \ 669 GD32_PINMUX_AFIO('E', 12, ALTERNATE, TIMER0_FRMP) 670 671 /* TIMER0_CH3 */ 672 #define TIMER0_CH3_PA11_INP_NORMP \ 673 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) 674 #define TIMER0_CH3_PA11_OUT_NORMP \ 675 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) 676 #define TIMER0_CH3_PA11_INP_PRMP \ 677 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) 678 #define TIMER0_CH3_PA11_OUT_PRMP \ 679 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) 680 #define TIMER0_CH3_PE14_INP_FRMP \ 681 GD32_PINMUX_AFIO('E', 14, GPIO_IN, TIMER0_FRMP) 682 #define TIMER0_CH3_PE14_OUT_FRMP \ 683 GD32_PINMUX_AFIO('E', 14, ALTERNATE, TIMER0_FRMP) 684 685 /* TIMER0_ETI */ 686 #define TIMER0_ETI_PA12_NORMP \ 687 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) 688 #define TIMER0_ETI_PA12_PRMP \ 689 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) 690 #define TIMER0_ETI_PE7_FRMP \ 691 GD32_PINMUX_AFIO('E', 7, GPIO_IN, TIMER0_FRMP) 692 693 /* TIMER10_CH0 */ 694 #define TIMER10_CH0_PB9_INP \ 695 GD32_PINMUX_AFIO('B', 9, GPIO_IN, NORMP) 696 #define TIMER10_CH0_PB9_OUT \ 697 GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP) 698 699 /* TIMER11_CH0 */ 700 #define TIMER11_CH0_PB14_INP \ 701 GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) 702 #define TIMER11_CH0_PB14_OUT \ 703 GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) 704 705 /* TIMER11_CH11 */ 706 #define TIMER11_CH11_PB15_INP \ 707 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 708 #define TIMER11_CH11_PB15_OUT \ 709 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 710 711 /* TIMER12_CH0 */ 712 #define TIMER12_CH0_PA6_INP \ 713 GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) 714 #define TIMER12_CH0_PA6_OUT \ 715 GD32_PINMUX_AFIO('A', 6, ALTERNATE, NORMP) 716 717 /* TIMER13_CH0 */ 718 #define TIMER13_CH0_PA7_INP \ 719 GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) 720 #define TIMER13_CH0_PA7_OUT \ 721 GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) 722 723 /* TIMER1_CH0_ETI */ 724 #define TIMER1_CH0_ETI_PA0 \ 725 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 726 727 /* TIMER1_CH1 */ 728 #define TIMER1_CH1_PA1_INP_NORMP \ 729 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) 730 #define TIMER1_CH1_PA1_OUT_NORMP \ 731 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) 732 #define TIMER1_CH1_PA1_INP_PRMP2 \ 733 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) 734 #define TIMER1_CH1_PA1_OUT_PRMP2 \ 735 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) 736 #define TIMER1_CH1_PB3_INP_PRMP1 \ 737 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) 738 #define TIMER1_CH1_PB3_OUT_PRMP1 \ 739 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) 740 #define TIMER1_CH1_PB3_INP_FRMP \ 741 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) 742 #define TIMER1_CH1_PB3_OUT_FRMP \ 743 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) 744 745 /* TIMER1_CH2 */ 746 #define TIMER1_CH2_PA2_INP_NORMP \ 747 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) 748 #define TIMER1_CH2_PA2_OUT_NORMP \ 749 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) 750 #define TIMER1_CH2_PA2_INP_PRMP1 \ 751 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) 752 #define TIMER1_CH2_PA2_OUT_PRMP1 \ 753 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) 754 #define TIMER1_CH2_PB10_INP_PRMP2 \ 755 GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2) 756 #define TIMER1_CH2_PB10_OUT_PRMP2 \ 757 GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2) 758 #define TIMER1_CH2_PB10_INP_FRMP \ 759 GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP) 760 #define TIMER1_CH2_PB10_OUT_FRMP \ 761 GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP) 762 763 /* TIMER1_CH3 */ 764 #define TIMER1_CH3_PA3_INP_NORMP \ 765 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) 766 #define TIMER1_CH3_PA3_OUT_NORMP \ 767 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) 768 #define TIMER1_CH3_PA3_INP_PRMP1 \ 769 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) 770 #define TIMER1_CH3_PA3_OUT_PRMP1 \ 771 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) 772 #define TIMER1_CH3_PB11_INP_PRMP2 \ 773 GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2) 774 #define TIMER1_CH3_PB11_OUT_PRMP2 \ 775 GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2) 776 #define TIMER1_CH3_PB11_INP_FRMP \ 777 GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP) 778 #define TIMER1_CH3_PB11_OUT_FRMP \ 779 GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP) 780 781 /* TIMER2_CH0 */ 782 #define TIMER2_CH0_PA6_INP_NORMP \ 783 GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) 784 #define TIMER2_CH0_PA6_OUT_NORMP \ 785 GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) 786 #define TIMER2_CH0_PB4_INP_PRMP \ 787 GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) 788 #define TIMER2_CH0_PB4_OUT_PRMP \ 789 GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) 790 #define TIMER2_CH0_PC6_INP_FRMP \ 791 GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP) 792 #define TIMER2_CH0_PC6_OUT_FRMP \ 793 GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP) 794 795 /* TIMER2_CH1 */ 796 #define TIMER2_CH1_PA7_INP_NORMP \ 797 GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) 798 #define TIMER2_CH1_PA7_OUT_NORMP \ 799 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) 800 #define TIMER2_CH1_PB5_INP_PRMP \ 801 GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) 802 #define TIMER2_CH1_PB5_OUT_PRMP \ 803 GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) 804 #define TIMER2_CH1_PC7_INP_FRMP \ 805 GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP) 806 #define TIMER2_CH1_PC7_OUT_FRMP \ 807 GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP) 808 809 /* TIMER2_CH2 */ 810 #define TIMER2_CH2_PB0_INP_NORMP \ 811 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) 812 #define TIMER2_CH2_PB0_OUT_NORMP \ 813 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) 814 #define TIMER2_CH2_PB0_INP_PRMP \ 815 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) 816 #define TIMER2_CH2_PB0_OUT_PRMP \ 817 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) 818 #define TIMER2_CH2_PC8_INP_FRMP \ 819 GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP) 820 #define TIMER2_CH2_PC8_OUT_FRMP \ 821 GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP) 822 823 /* TIMER2_CH3 */ 824 #define TIMER2_CH3_PB1_INP_NORMP \ 825 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) 826 #define TIMER2_CH3_PB1_OUT_NORMP \ 827 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) 828 #define TIMER2_CH3_PB1_INP_PRMP \ 829 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) 830 #define TIMER2_CH3_PB1_OUT_PRMP \ 831 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) 832 #define TIMER2_CH3_PC9_INP_FRMP \ 833 GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP) 834 #define TIMER2_CH3_PC9_OUT_FRMP \ 835 GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP) 836 837 /* TIMER2_ETI */ 838 #define TIMER2_ETI_PD2 \ 839 GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) 840 841 /* TIMER3_CH0 */ 842 #define TIMER3_CH0_PB6_INP_NORMP \ 843 GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) 844 #define TIMER3_CH0_PB6_OUT_NORMP \ 845 GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) 846 #define TIMER3_CH0_PD12_INP_RMP \ 847 GD32_PINMUX_AFIO('D', 12, GPIO_IN, TIMER3_RMP) 848 #define TIMER3_CH0_PD12_OUT_RMP \ 849 GD32_PINMUX_AFIO('D', 12, ALTERNATE, TIMER3_RMP) 850 851 /* TIMER3_CH1 */ 852 #define TIMER3_CH1_PB7_INP_NORMP \ 853 GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) 854 #define TIMER3_CH1_PB7_OUT_NORMP \ 855 GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) 856 #define TIMER3_CH1_PD13_INP_RMP \ 857 GD32_PINMUX_AFIO('D', 13, GPIO_IN, TIMER3_RMP) 858 #define TIMER3_CH1_PD13_OUT_RMP \ 859 GD32_PINMUX_AFIO('D', 13, ALTERNATE, TIMER3_RMP) 860 861 /* TIMER3_CH2 */ 862 #define TIMER3_CH2_PB8_INP_NORMP \ 863 GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP) 864 #define TIMER3_CH2_PB8_OUT_NORMP \ 865 GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP) 866 #define TIMER3_CH2_PD14_INP_RMP \ 867 GD32_PINMUX_AFIO('D', 14, GPIO_IN, TIMER3_RMP) 868 #define TIMER3_CH2_PD14_OUT_RMP \ 869 GD32_PINMUX_AFIO('D', 14, ALTERNATE, TIMER3_RMP) 870 871 /* TIMER3_CH3 */ 872 #define TIMER3_CH3_PB9_INP_NORMP \ 873 GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP) 874 #define TIMER3_CH3_PB9_OUT_NORMP \ 875 GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP) 876 #define TIMER3_CH3_PD15_INP_RMP \ 877 GD32_PINMUX_AFIO('D', 15, GPIO_IN, TIMER3_RMP) 878 #define TIMER3_CH3_PD15_OUT_RMP \ 879 GD32_PINMUX_AFIO('D', 15, ALTERNATE, TIMER3_RMP) 880 881 /* TIMER3_ETI */ 882 #define TIMER3_ETI_PE0 \ 883 GD32_PINMUX_AFIO('E', 0, GPIO_IN, NORMP) 884 885 /* TIMER4_CH0 */ 886 #define TIMER4_CH0_PA0_INP \ 887 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 888 #define TIMER4_CH0_PA0_OUT \ 889 GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP) 890 891 /* TIMER4_CH1 */ 892 #define TIMER4_CH1_PA1_INP \ 893 GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) 894 #define TIMER4_CH1_PA1_OUT \ 895 GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) 896 897 /* TIMER4_CH2 */ 898 #define TIMER4_CH2_PA2_INP \ 899 GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) 900 #define TIMER4_CH2_PA2_OUT \ 901 GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) 902 903 /* TIMER4_CH3 */ 904 #define TIMER4_CH3_PA3_INP \ 905 GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) 906 #define TIMER4_CH3_PA3_OUT \ 907 GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) 908 909 /* TIMER7_BKIN */ 910 #define TIMER7_BKIN_PA6 \ 911 GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) 912 913 /* TIMER7_CH0 */ 914 #define TIMER7_CH0_PC6_INP \ 915 GD32_PINMUX_AFIO('C', 6, GPIO_IN, NORMP) 916 #define TIMER7_CH0_PC6_OUT \ 917 GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) 918 919 /* TIMER7_CH0_ON */ 920 #define TIMER7_CH0_ON_PA7_INP \ 921 GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) 922 #define TIMER7_CH0_ON_PA7_OUT \ 923 GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) 924 925 /* TIMER7_CH1 */ 926 #define TIMER7_CH1_PC7_INP \ 927 GD32_PINMUX_AFIO('C', 7, GPIO_IN, NORMP) 928 #define TIMER7_CH1_PC7_OUT \ 929 GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) 930 931 /* TIMER7_CH1_ON */ 932 #define TIMER7_CH1_ON_PB0_INP \ 933 GD32_PINMUX_AFIO('B', 0, GPIO_IN, NORMP) 934 #define TIMER7_CH1_ON_PB0_OUT \ 935 GD32_PINMUX_AFIO('B', 0, ALTERNATE, NORMP) 936 937 /* TIMER7_CH2 */ 938 #define TIMER7_CH2_PC8_INP \ 939 GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP) 940 #define TIMER7_CH2_PC8_OUT \ 941 GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP) 942 943 /* TIMER7_CH2_ON */ 944 #define TIMER7_CH2_ON_PB1 \ 945 GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP) 946 947 /* TIMER7_CH3 */ 948 #define TIMER7_CH3_PC9_INP \ 949 GD32_PINMUX_AFIO('C', 9, GPIO_IN, NORMP) 950 #define TIMER7_CH3_PC9_OUT \ 951 GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP) 952 953 /* TIMER7_ETI */ 954 #define TIMER7_ETI_PA0 \ 955 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 956 957 /* TIMER8_CH0 */ 958 #define TIMER8_CH0_PA2_INP \ 959 GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) 960 #define TIMER8_CH0_PA2_OUT \ 961 GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) 962 963 /* TIMER8_CH1 */ 964 #define TIMER8_CH1_PA3_INP \ 965 GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) 966 #define TIMER8_CH1_PA3_OUT \ 967 GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) 968 969 /* TIMER9_CH0 */ 970 #define TIMER9_CH0_PB8_INP \ 971 GD32_PINMUX_AFIO('B', 8, GPIO_IN, NORMP) 972 #define TIMER9_CH0_PB8_OUT \ 973 GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP) 974 975 /* TRACECK */ 976 #define TRACECK_PE2 \ 977 GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP) 978 979 /* TRACED0 */ 980 #define TRACED0_PE3 \ 981 GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP) 982 983 /* TRACED1 */ 984 #define TRACED1_PE4 \ 985 GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP) 986 987 /* TRACED2 */ 988 #define TRACED2_PE5 \ 989 GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP) 990 991 /* TRACED3 */ 992 #define TRACED3_PE6 \ 993 GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP) 994 995 /* UART3_RX */ 996 #define UART3_RX_PC11 \ 997 GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP) 998 999 /* UART3_TX */ 1000 #define UART3_TX_PC10 \ 1001 GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP) 1002 1003 /* UART4_RX */ 1004 #define UART4_RX_PD2 \ 1005 GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) 1006 1007 /* UART4_TX */ 1008 #define UART4_TX_PC12 \ 1009 GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP) 1010 1011 /* USART0_CK */ 1012 #define USART0_CK_PA8 \ 1013 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 1014 1015 /* USART0_CTS */ 1016 #define USART0_CTS_PA11 \ 1017 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 1018 1019 /* USART0_RTS */ 1020 #define USART0_RTS_PA12 \ 1021 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 1022 1023 /* USART0_RX */ 1024 #define USART0_RX_PA10_NORMP \ 1025 GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) 1026 #define USART0_RX_PB7_RMP \ 1027 GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) 1028 1029 /* USART0_TX */ 1030 #define USART0_TX_PA9_NORMP \ 1031 GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) 1032 #define USART0_TX_PB6_RMP \ 1033 GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) 1034 1035 /* USART1_CK */ 1036 #define USART1_CK_PA4_NORMP \ 1037 GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) 1038 #define USART1_CK_PD7_RMP \ 1039 GD32_PINMUX_AFIO('D', 7, ALTERNATE, USART1_RMP) 1040 1041 /* USART1_CTS */ 1042 #define USART1_CTS_PA0_NORMP \ 1043 GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) 1044 #define USART1_CTS_PD3_RMP \ 1045 GD32_PINMUX_AFIO('D', 3, GPIO_IN, USART1_RMP) 1046 1047 /* USART1_RTS */ 1048 #define USART1_RTS_PA1_NORMP \ 1049 GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) 1050 #define USART1_RTS_PD4_RMP \ 1051 GD32_PINMUX_AFIO('D', 4, ALTERNATE, USART1_RMP) 1052 1053 /* USART1_RX */ 1054 #define USART1_RX_PA3_NORMP \ 1055 GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) 1056 #define USART1_RX_PD6_RMP \ 1057 GD32_PINMUX_AFIO('D', 6, GPIO_IN, USART1_RMP) 1058 1059 /* USART1_TX */ 1060 #define USART1_TX_PA2_NORMP \ 1061 GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) 1062 #define USART1_TX_PD5_RMP \ 1063 GD32_PINMUX_AFIO('D', 5, ALTERNATE, USART1_RMP) 1064 1065 /* USART2_CK */ 1066 #define USART2_CK_PB12_NORMP \ 1067 GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP) 1068 #define USART2_CK_PC12_PRMP \ 1069 GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP) 1070 #define USART2_CK_PD10_FRMP \ 1071 GD32_PINMUX_AFIO('D', 10, ALTERNATE, USART2_FRMP) 1072 1073 /* USART2_CTS */ 1074 #define USART2_CTS_PB13_NORMP \ 1075 GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP) 1076 #define USART2_CTS_PB13_PRMP \ 1077 GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP) 1078 #define USART2_CTS_PD11_FRMP \ 1079 GD32_PINMUX_AFIO('D', 11, GPIO_IN, USART2_FRMP) 1080 1081 /* USART2_RTS */ 1082 #define USART2_RTS_PB14_NORMP \ 1083 GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP) 1084 #define USART2_RTS_PB14_PRMP \ 1085 GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP) 1086 #define USART2_RTS_PD12_FRMP \ 1087 GD32_PINMUX_AFIO('D', 12, ALTERNATE, USART2_FRMP) 1088 1089 /* USART2_RX */ 1090 #define USART2_RX_PB11_NORMP \ 1091 GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP) 1092 #define USART2_RX_PC11_PRMP \ 1093 GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP) 1094 #define USART2_RX_PD9_FRMP \ 1095 GD32_PINMUX_AFIO('D', 9, GPIO_IN, USART2_FRMP) 1096 1097 /* USART2_TX */ 1098 #define USART2_TX_PB10_NORMP \ 1099 GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP) 1100 #define USART2_TX_PC10_PRMP \ 1101 GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP) 1102 #define USART2_TX_PD8_FRMP \ 1103 GD32_PINMUX_AFIO('D', 8, ALTERNATE, USART2_FRMP) 1104 1105 /* USBFS_DM */ 1106 #define USBFS_DM_PA11_INP \ 1107 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 1108 #define USBFS_DM_PA11_OUT \ 1109 GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) 1110 1111 /* USBFS_DP */ 1112 #define USBFS_DP_PA12_INP \ 1113 GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) 1114 #define USBFS_DP_PA12_OUT \ 1115 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 1116 1117 /* USBFS_ID */ 1118 #define USBFS_ID_PA10_INP \ 1119 GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) 1120 #define USBFS_ID_PA10_OUT \ 1121 GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) 1122 1123 /* USBFS_SOF */ 1124 #define USBFS_SOF_PA8 \ 1125 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 1126 1127 /* USBFS_VBUS */ 1128 #define USBFS_VBUS_PA9 \ 1129 GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) 1130 1131 /* WKUP */ 1132 #define WKUP_PA0 \ 1133 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 1134
