1 /*
2  * Autogenerated file
3  *
4  * SPDX-License-Identifier: Apache 2.0
5  */
6 
7 #include "gd32e103xx-afio.h"
8 
9 /* ADC01_IN0 */
10 #define ADC01_IN0_PA0 \
11 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
12 
13 /* ADC01_IN1 */
14 #define ADC01_IN1_PA1 \
15 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
16 
17 /* ADC01_IN2 */
18 #define ADC01_IN2_PA2 \
19 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
20 
21 /* ADC01_IN3 */
22 #define ADC01_IN3_PA3 \
23 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
24 
25 /* ADC01_IN4 */
26 #define ADC01_IN4_PA4 \
27 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
28 
29 /* ADC01_IN5 */
30 #define ADC01_IN5_PA5 \
31 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
32 
33 /* ADC01_IN6 */
34 #define ADC01_IN6_PA6 \
35 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
36 
37 /* ADC01_IN7 */
38 #define ADC01_IN7_PA7 \
39 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
40 
41 /* ADC01_IN8 */
42 #define ADC01_IN8_PB0 \
43 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
44 
45 /* ADC01_IN9 */
46 #define ADC01_IN9_PB1 \
47 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
48 
49 /* ANALOG */
50 #define ANALOG_PA0 \
51 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
52 #define ANALOG_PA1 \
53 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
54 #define ANALOG_PA2 \
55 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
56 #define ANALOG_PA3 \
57 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
58 #define ANALOG_PA4 \
59 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
60 #define ANALOG_PA5 \
61 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
62 #define ANALOG_PA6 \
63 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
64 #define ANALOG_PA7 \
65 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
66 #define ANALOG_PA8 \
67 	GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP)
68 #define ANALOG_PA9 \
69 	GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP)
70 #define ANALOG_PA10 \
71 	GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP)
72 #define ANALOG_PA11 \
73 	GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP)
74 #define ANALOG_PA12 \
75 	GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP)
76 #define ANALOG_PA13 \
77 	GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP)
78 #define ANALOG_PA14 \
79 	GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP)
80 #define ANALOG_PA15 \
81 	GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP)
82 #define ANALOG_PB0 \
83 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
84 #define ANALOG_PB1 \
85 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
86 #define ANALOG_PB2 \
87 	GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP)
88 #define ANALOG_PB3 \
89 	GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP)
90 #define ANALOG_PB4 \
91 	GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP)
92 #define ANALOG_PB5 \
93 	GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP)
94 #define ANALOG_PB6 \
95 	GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP)
96 #define ANALOG_PB7 \
97 	GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP)
98 #define ANALOG_PD0 \
99 	GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP)
100 #define ANALOG_PD1 \
101 	GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP)
102 
103 /* CK_OUT0 */
104 #define CK_OUT0_PA8 \
105 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
106 
107 /* CTC_SYNC */
108 #define CTC_SYNC_PA8 \
109 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
110 
111 /* DAC_OUT0 */
112 #define DAC_OUT0_PA4 \
113 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
114 
115 /* DAC_OUT1 */
116 #define DAC_OUT1_PA5 \
117 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
118 
119 /* I2C0_SCL */
120 #define I2C0_SCL_PB6_NORMP \
121 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP)
122 
123 /* I2C0_SDA */
124 #define I2C0_SDA_PB7_NORMP \
125 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP)
126 
127 /* I2C0_SMBA */
128 #define I2C0_SMBA_PB5 \
129 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP)
130 
131 /* I2C0_TXFRAME */
132 #define I2C0_TXFRAME_PB4 \
133 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP)
134 
135 /* SPI0_IO2 */
136 #define SPI0_IO2_PA2_NORMP \
137 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP)
138 #define SPI0_IO2_PB6_RMP \
139 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP)
140 
141 /* SPI0_IO3 */
142 #define SPI0_IO3_PA3_NORMP \
143 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP)
144 #define SPI0_IO3_PB7_RMP \
145 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP)
146 
147 /* SPI0_MISO */
148 #define SPI0_MISO_PA6_INP_NORMP \
149 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP)
150 #define SPI0_MISO_PA6_OUT_NORMP \
151 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP)
152 #define SPI0_MISO_PB4_INP_RMP \
153 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP)
154 #define SPI0_MISO_PB4_OUT_RMP \
155 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP)
156 
157 /* SPI0_MOSI */
158 #define SPI0_MOSI_PA7_INP_NORMP \
159 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP)
160 #define SPI0_MOSI_PA7_OUT_NORMP \
161 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP)
162 #define SPI0_MOSI_PB5_INP_RMP \
163 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP)
164 #define SPI0_MOSI_PB5_OUT_RMP \
165 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP)
166 
167 /* SPI0_NSS */
168 #define SPI0_NSS_PA4_INP_NORMP \
169 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP)
170 #define SPI0_NSS_PA4_OUT_NORMP \
171 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP)
172 #define SPI0_NSS_PA15_INP_RMP \
173 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP)
174 #define SPI0_NSS_PA15_OUT_RMP \
175 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP)
176 
177 /* SPI0_SCK */
178 #define SPI0_SCK_PA5_INP_NORMP \
179 	GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP)
180 #define SPI0_SCK_PA5_OUT_NORMP \
181 	GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP)
182 #define SPI0_SCK_PB3_INP_RMP \
183 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP)
184 #define SPI0_SCK_PB3_OUT_RMP \
185 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP)
186 
187 /* TIMER0_CH0 */
188 #define TIMER0_CH0_PA8_INP_NORMP \
189 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP)
190 #define TIMER0_CH0_PA8_OUT_NORMP \
191 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP)
192 #define TIMER0_CH0_PA8_INP_PRMP \
193 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP)
194 #define TIMER0_CH0_PA8_OUT_PRMP \
195 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP)
196 
197 /* TIMER0_CH1 */
198 #define TIMER0_CH1_PA9_INP_NORMP \
199 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP)
200 #define TIMER0_CH1_PA9_OUT_NORMP \
201 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP)
202 #define TIMER0_CH1_PA9_INP_PRMP \
203 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP)
204 #define TIMER0_CH1_PA9_OUT_PRMP \
205 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP)
206 
207 /* TIMER0_CH2 */
208 #define TIMER0_CH2_PA10_INP_NORMP \
209 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP)
210 #define TIMER0_CH2_PA10_OUT_NORMP \
211 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP)
212 #define TIMER0_CH2_PA10_INP_PRMP \
213 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP)
214 #define TIMER0_CH2_PA10_OUT_PRMP \
215 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP)
216 
217 /* TIMER0_CH3 */
218 #define TIMER0_CH3_PA11_INP_NORMP \
219 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP)
220 #define TIMER0_CH3_PA11_OUT_NORMP \
221 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP)
222 #define TIMER0_CH3_PA11_INP_PRMP \
223 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP)
224 #define TIMER0_CH3_PA11_OUT_PRMP \
225 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP)
226 
227 /* TIMER0_ETI */
228 #define TIMER0_ETI_PA12_NORMP \
229 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP)
230 #define TIMER0_ETI_PA12_PRMP \
231 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP)
232 
233 /* TIMER1_CH0_ETI */
234 #define TIMER1_CH0_ETI_PA0 \
235 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
236 
237 /* TIMER1_CH1 */
238 #define TIMER1_CH1_PA1_INP_NORMP \
239 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP)
240 #define TIMER1_CH1_PA1_OUT_NORMP \
241 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP)
242 #define TIMER1_CH1_PA1_INP_PRMP2 \
243 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2)
244 #define TIMER1_CH1_PA1_OUT_PRMP2 \
245 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2)
246 #define TIMER1_CH1_PB3_INP_PRMP1 \
247 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1)
248 #define TIMER1_CH1_PB3_OUT_PRMP1 \
249 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1)
250 #define TIMER1_CH1_PB3_INP_FRMP \
251 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP)
252 #define TIMER1_CH1_PB3_OUT_FRMP \
253 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP)
254 
255 /* TIMER1_CH2 */
256 #define TIMER1_CH2_PA2_INP_NORMP \
257 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP)
258 #define TIMER1_CH2_PA2_OUT_NORMP \
259 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP)
260 #define TIMER1_CH2_PA2_INP_PRMP1 \
261 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1)
262 #define TIMER1_CH2_PA2_OUT_PRMP1 \
263 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1)
264 
265 /* TIMER1_CH3 */
266 #define TIMER1_CH3_PA3_INP_NORMP \
267 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP)
268 #define TIMER1_CH3_PA3_OUT_NORMP \
269 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP)
270 #define TIMER1_CH3_PA3_INP_PRMP1 \
271 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1)
272 #define TIMER1_CH3_PA3_OUT_PRMP1 \
273 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1)
274 
275 /* TIMER2_CH0 */
276 #define TIMER2_CH0_PA6_INP_NORMP \
277 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP)
278 #define TIMER2_CH0_PA6_OUT_NORMP \
279 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP)
280 #define TIMER2_CH0_PB4_INP_PRMP \
281 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP)
282 #define TIMER2_CH0_PB4_OUT_PRMP \
283 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP)
284 
285 /* TIMER2_CH1 */
286 #define TIMER2_CH1_PA7_INP_NORMP \
287 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP)
288 #define TIMER2_CH1_PA7_OUT_NORMP \
289 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP)
290 #define TIMER2_CH1_PB5_INP_PRMP \
291 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP)
292 #define TIMER2_CH1_PB5_OUT_PRMP \
293 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP)
294 
295 /* TIMER2_CH2 */
296 #define TIMER2_CH2_PB0_INP_NORMP \
297 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP)
298 #define TIMER2_CH2_PB0_OUT_NORMP \
299 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP)
300 #define TIMER2_CH2_PB0_INP_PRMP \
301 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP)
302 #define TIMER2_CH2_PB0_OUT_PRMP \
303 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP)
304 
305 /* TIMER2_CH3 */
306 #define TIMER2_CH3_PB1_INP_NORMP \
307 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP)
308 #define TIMER2_CH3_PB1_OUT_NORMP \
309 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP)
310 #define TIMER2_CH3_PB1_INP_PRMP \
311 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP)
312 #define TIMER2_CH3_PB1_OUT_PRMP \
313 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP)
314 
315 /* TIMER3_CH0 */
316 #define TIMER3_CH0_PB6_INP_NORMP \
317 	GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP)
318 #define TIMER3_CH0_PB6_OUT_NORMP \
319 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP)
320 
321 /* TIMER3_CH1 */
322 #define TIMER3_CH1_PB7_INP_NORMP \
323 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP)
324 #define TIMER3_CH1_PB7_OUT_NORMP \
325 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP)
326 
327 /* TIMER4_CH0 */
328 #define TIMER4_CH0_PA0_INP \
329 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
330 #define TIMER4_CH0_PA0_OUT \
331 	GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP)
332 
333 /* TIMER4_CH1 */
334 #define TIMER4_CH1_PA1_INP \
335 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP)
336 #define TIMER4_CH1_PA1_OUT \
337 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP)
338 
339 /* TIMER4_CH2 */
340 #define TIMER4_CH2_PA2_INP \
341 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP)
342 #define TIMER4_CH2_PA2_OUT \
343 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP)
344 
345 /* TIMER4_CH3 */
346 #define TIMER4_CH3_PA3_INP \
347 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP)
348 #define TIMER4_CH3_PA3_OUT \
349 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP)
350 
351 /* USART0_CK */
352 #define USART0_CK_PA8 \
353 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
354 
355 /* USART0_CTS */
356 #define USART0_CTS_PA11 \
357 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
358 
359 /* USART0_RTS */
360 #define USART0_RTS_PA12 \
361 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
362 
363 /* USART0_RX */
364 #define USART0_RX_PA10_NORMP \
365 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP)
366 #define USART0_RX_PB7_RMP \
367 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP)
368 
369 /* USART0_TX */
370 #define USART0_TX_PA9_NORMP \
371 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP)
372 #define USART0_TX_PB6_RMP \
373 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP)
374 
375 /* USART1_CK */
376 #define USART1_CK_PA4_NORMP \
377 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP)
378 
379 /* USART1_CTS */
380 #define USART1_CTS_PA0_NORMP \
381 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP)
382 
383 /* USART1_RTS */
384 #define USART1_RTS_PA1_NORMP \
385 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP)
386 
387 /* USART1_RX */
388 #define USART1_RX_PA3_NORMP \
389 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP)
390 
391 /* USART1_TX */
392 #define USART1_TX_PA2_NORMP \
393 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP)
394 
395 /* USBFS_DM */
396 #define USBFS_DM_PA11_INP \
397 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
398 #define USBFS_DM_PA11_OUT \
399 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP)
400 
401 /* USBFS_DP */
402 #define USBFS_DP_PA12_INP \
403 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP)
404 #define USBFS_DP_PA12_OUT \
405 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
406 
407 /* USBFS_ID */
408 #define USBFS_ID_PA10_INP \
409 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP)
410 #define USBFS_ID_PA10_OUT \
411 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP)
412 
413 /* USBFS_SOF */
414 #define USBFS_SOF_PA8 \
415 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
416 
417 /* USBFS_VBUS */
418 #define USBFS_VBUS_PA9 \
419 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP)
420 
421 /* WKUP */
422 #define WKUP_PA0 \
423 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
424