1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32e103xx-afio.h" 8 9 /* ADC01_IN0 */ 10 #define ADC01_IN0_PA0 \ 11 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 12 13 /* ADC01_IN1 */ 14 #define ADC01_IN1_PA1 \ 15 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 16 17 /* ADC01_IN10 */ 18 #define ADC01_IN10_PC0 \ 19 GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) 20 21 /* ADC01_IN11 */ 22 #define ADC01_IN11_PC1 \ 23 GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) 24 25 /* ADC01_IN12 */ 26 #define ADC01_IN12_PC2 \ 27 GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) 28 29 /* ADC01_IN13 */ 30 #define ADC01_IN13_PC3 \ 31 GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) 32 33 /* ADC01_IN14 */ 34 #define ADC01_IN14_PC4 \ 35 GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) 36 37 /* ADC01_IN15 */ 38 #define ADC01_IN15_PC5 \ 39 GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) 40 41 /* ADC01_IN2 */ 42 #define ADC01_IN2_PA2 \ 43 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 44 45 /* ADC01_IN3 */ 46 #define ADC01_IN3_PA3 \ 47 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 48 49 /* ADC01_IN4 */ 50 #define ADC01_IN4_PA4 \ 51 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 52 53 /* ADC01_IN5 */ 54 #define ADC01_IN5_PA5 \ 55 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 56 57 /* ADC01_IN6 */ 58 #define ADC01_IN6_PA6 \ 59 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 60 61 /* ADC01_IN7 */ 62 #define ADC01_IN7_PA7 \ 63 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 64 65 /* ADC01_IN8 */ 66 #define ADC01_IN8_PB0 \ 67 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 68 69 /* ADC01_IN9 */ 70 #define ADC01_IN9_PB1 \ 71 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 72 73 /* ANALOG */ 74 #define ANALOG_PA0 \ 75 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 76 #define ANALOG_PA1 \ 77 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 78 #define ANALOG_PA2 \ 79 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 80 #define ANALOG_PA3 \ 81 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 82 #define ANALOG_PA4 \ 83 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 84 #define ANALOG_PA5 \ 85 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 86 #define ANALOG_PA6 \ 87 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 88 #define ANALOG_PA7 \ 89 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 90 #define ANALOG_PA8 \ 91 GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) 92 #define ANALOG_PA9 \ 93 GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) 94 #define ANALOG_PA10 \ 95 GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) 96 #define ANALOG_PA11 \ 97 GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) 98 #define ANALOG_PA12 \ 99 GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) 100 #define ANALOG_PA13 \ 101 GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) 102 #define ANALOG_PA14 \ 103 GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) 104 #define ANALOG_PA15 \ 105 GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) 106 #define ANALOG_PB0 \ 107 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 108 #define ANALOG_PB1 \ 109 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 110 #define ANALOG_PB2 \ 111 GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) 112 #define ANALOG_PB3 \ 113 GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) 114 #define ANALOG_PB4 \ 115 GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) 116 #define ANALOG_PB5 \ 117 GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) 118 #define ANALOG_PB6 \ 119 GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) 120 #define ANALOG_PB7 \ 121 GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) 122 #define ANALOG_PB8 \ 123 GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) 124 #define ANALOG_PB9 \ 125 GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) 126 #define ANALOG_PB10 \ 127 GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) 128 #define ANALOG_PB11 \ 129 GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) 130 #define ANALOG_PB12 \ 131 GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) 132 #define ANALOG_PB13 \ 133 GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) 134 #define ANALOG_PB14 \ 135 GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) 136 #define ANALOG_PB15 \ 137 GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) 138 #define ANALOG_PC0 \ 139 GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) 140 #define ANALOG_PC1 \ 141 GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) 142 #define ANALOG_PC2 \ 143 GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) 144 #define ANALOG_PC3 \ 145 GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) 146 #define ANALOG_PC4 \ 147 GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) 148 #define ANALOG_PC5 \ 149 GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) 150 #define ANALOG_PC6 \ 151 GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP) 152 #define ANALOG_PC7 \ 153 GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP) 154 #define ANALOG_PC8 \ 155 GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP) 156 #define ANALOG_PC9 \ 157 GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP) 158 #define ANALOG_PC10 \ 159 GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP) 160 #define ANALOG_PC11 \ 161 GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP) 162 #define ANALOG_PC12 \ 163 GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP) 164 #define ANALOG_PC13 \ 165 GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) 166 #define ANALOG_PC14 \ 167 GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) 168 #define ANALOG_PC15 \ 169 GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) 170 #define ANALOG_PD0 \ 171 GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) 172 #define ANALOG_PD1 \ 173 GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) 174 #define ANALOG_PD2 \ 175 GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP) 176 177 /* CK_OUT0 */ 178 #define CK_OUT0_PA8 \ 179 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 180 181 /* CTC_SYNC */ 182 #define CTC_SYNC_PA8 \ 183 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 184 185 /* DAC_OUT0 */ 186 #define DAC_OUT0_PA4 \ 187 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 188 189 /* DAC_OUT1 */ 190 #define DAC_OUT1_PA5 \ 191 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 192 193 /* I2C0_SCL */ 194 #define I2C0_SCL_PB6_NORMP \ 195 GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) 196 #define I2C0_SCL_PB8_RMP \ 197 GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) 198 199 /* I2C0_SDA */ 200 #define I2C0_SDA_PB7_NORMP \ 201 GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) 202 #define I2C0_SDA_PB9_RMP \ 203 GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) 204 205 /* I2C0_SMBA */ 206 #define I2C0_SMBA_PB5 \ 207 GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) 208 209 /* I2C0_TXFRAME */ 210 #define I2C0_TXFRAME_PB4 \ 211 GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP) 212 213 /* I2C1_SCL */ 214 #define I2C1_SCL_PB10 \ 215 GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP) 216 217 /* I2C1_SDA */ 218 #define I2C1_SDA_PB11 \ 219 GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP) 220 221 /* I2C1_SMBA */ 222 #define I2C1_SMBA_PB12 \ 223 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 224 225 /* I2C1_TXFRAME */ 226 #define I2C1_TXFRAME_PB13 \ 227 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 228 229 /* I2S1_CK */ 230 #define I2S1_CK_PB13 \ 231 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 232 233 /* I2S1_MCK */ 234 #define I2S1_MCK_PC6 \ 235 GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) 236 237 /* I2S1_SD */ 238 #define I2S1_SD_PB15_INP \ 239 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 240 #define I2S1_SD_PB15_OUT \ 241 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 242 243 /* I2S1_WS */ 244 #define I2S1_WS_PB12_INP \ 245 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 246 #define I2S1_WS_PB12_OUT \ 247 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 248 249 /* I2S2_CK */ 250 #define I2S2_CK_PB3_NORMP \ 251 GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) 252 #define I2S2_CK_PC10_RMP \ 253 GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP) 254 255 /* I2S2_MCK */ 256 #define I2S2_MCK_PC7 \ 257 GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) 258 259 /* I2S2_SD */ 260 #define I2S2_SD_PB5_INP_NORMP \ 261 GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) 262 #define I2S2_SD_PB5_OUT_NORMP \ 263 GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) 264 #define I2S2_SD_PC12_INP_RMP \ 265 GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP) 266 #define I2S2_SD_PC12_OUT_RMP \ 267 GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP) 268 269 /* I2S2_WS */ 270 #define I2S2_WS_PA15_INP_NORMP \ 271 GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) 272 #define I2S2_WS_PA15_OUT_NORMP \ 273 GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) 274 #define I2S2_WS_PA4_INP_RMP \ 275 GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) 276 #define I2S2_WS_PA4_OUT_RMP \ 277 GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) 278 279 /* RTC_TAMPER */ 280 #define RTC_TAMPER_PC13 \ 281 GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) 282 283 /* SPI0_IO2 */ 284 #define SPI0_IO2_PA2_NORMP \ 285 GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP) 286 #define SPI0_IO2_PB6_RMP \ 287 GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP) 288 289 /* SPI0_IO3 */ 290 #define SPI0_IO3_PA3_NORMP \ 291 GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP) 292 #define SPI0_IO3_PB7_RMP \ 293 GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP) 294 295 /* SPI0_MISO */ 296 #define SPI0_MISO_PA6_INP_NORMP \ 297 GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) 298 #define SPI0_MISO_PA6_OUT_NORMP \ 299 GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) 300 #define SPI0_MISO_PB4_INP_RMP \ 301 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) 302 #define SPI0_MISO_PB4_OUT_RMP \ 303 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) 304 305 /* SPI0_MOSI */ 306 #define SPI0_MOSI_PA7_INP_NORMP \ 307 GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) 308 #define SPI0_MOSI_PA7_OUT_NORMP \ 309 GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) 310 #define SPI0_MOSI_PB5_INP_RMP \ 311 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) 312 #define SPI0_MOSI_PB5_OUT_RMP \ 313 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) 314 315 /* SPI0_NSS */ 316 #define SPI0_NSS_PA4_INP_NORMP \ 317 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) 318 #define SPI0_NSS_PA4_OUT_NORMP \ 319 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) 320 #define SPI0_NSS_PA15_INP_RMP \ 321 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) 322 #define SPI0_NSS_PA15_OUT_RMP \ 323 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) 324 325 /* SPI0_SCK */ 326 #define SPI0_SCK_PA5_INP_NORMP \ 327 GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) 328 #define SPI0_SCK_PA5_OUT_NORMP \ 329 GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) 330 #define SPI0_SCK_PB3_INP_RMP \ 331 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) 332 #define SPI0_SCK_PB3_OUT_RMP \ 333 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) 334 335 /* SPI1_MISO */ 336 #define SPI1_MISO_PB14_INP \ 337 GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) 338 #define SPI1_MISO_PB14_OUT \ 339 GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) 340 341 /* SPI1_MOSI */ 342 #define SPI1_MOSI_PB15_INP \ 343 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 344 #define SPI1_MOSI_PB15_OUT \ 345 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 346 347 /* SPI1_NSS */ 348 #define SPI1_NSS_PB12_INP \ 349 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 350 #define SPI1_NSS_PB12_OUT \ 351 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 352 353 /* SPI1_SCK */ 354 #define SPI1_SCK_PB13_INP \ 355 GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) 356 #define SPI1_SCK_PB13_OUT \ 357 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 358 359 /* SPI2_MISO */ 360 #define SPI2_MISO_PB4_INP_NORMP \ 361 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) 362 #define SPI2_MISO_PB4_OUT_NORMP \ 363 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) 364 #define SPI2_MISO_PC11_INP_RMP \ 365 GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP) 366 #define SPI2_MISO_PC11_OUT_RMP \ 367 GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP) 368 369 /* SPI2_MOSI */ 370 #define SPI2_MOSI_PB5_INP_NORMP \ 371 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) 372 #define SPI2_MOSI_PB5_OUT_NORMP \ 373 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) 374 #define SPI2_MOSI_PC12_INP_RMP \ 375 GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP) 376 #define SPI2_MOSI_PC12_OUT_RMP \ 377 GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP) 378 379 /* SPI2_NSS */ 380 #define SPI2_NSS_PA15_INP_NORMP \ 381 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) 382 #define SPI2_NSS_PA15_OUT_NORMP \ 383 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) 384 #define SPI2_NSS_PA4_INP_RMP \ 385 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) 386 #define SPI2_NSS_PA4_OUT_RMP \ 387 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) 388 389 /* SPI2_SCK */ 390 #define SPI2_SCK_PB3_INP_NORMP \ 391 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) 392 #define SPI2_SCK_PB3_OUT_NORMP \ 393 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) 394 #define SPI2_SCK_PC10_INP_RMP \ 395 GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP) 396 #define SPI2_SCK_PC10_OUT_RMP \ 397 GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP) 398 399 /* TIMER0_BKIN */ 400 #define TIMER0_BKIN_PB12_NORMP \ 401 GD32_PINMUX_AFIO('B', 12, GPIO_IN, TIMER0_NORMP) 402 #define TIMER0_BKIN_PA6_PRMP \ 403 GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER0_PRMP) 404 405 /* TIMER0_CH0 */ 406 #define TIMER0_CH0_PA8_INP_NORMP \ 407 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) 408 #define TIMER0_CH0_PA8_OUT_NORMP \ 409 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) 410 #define TIMER0_CH0_PA8_INP_PRMP \ 411 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) 412 #define TIMER0_CH0_PA8_OUT_PRMP \ 413 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) 414 415 /* TIMER0_CH0_ON */ 416 #define TIMER0_CH0_ON_PB13_INP_NORMP \ 417 GD32_PINMUX_AFIO('B', 13, GPIO_IN, TIMER0_NORMP) 418 #define TIMER0_CH0_ON_PB13_OUT_NORMP \ 419 GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) 420 #define TIMER0_CH0_ON_PA7_INP_PRMP \ 421 GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER0_PRMP) 422 #define TIMER0_CH0_ON_PA7_OUT_PRMP \ 423 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) 424 425 /* TIMER0_CH1 */ 426 #define TIMER0_CH1_PA9_INP_NORMP \ 427 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) 428 #define TIMER0_CH1_PA9_OUT_NORMP \ 429 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) 430 #define TIMER0_CH1_PA9_INP_PRMP \ 431 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) 432 #define TIMER0_CH1_PA9_OUT_PRMP \ 433 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) 434 435 /* TIMER0_CH1_ON */ 436 #define TIMER0_CH1_ON_PB14_INP_NORMP \ 437 GD32_PINMUX_AFIO('B', 14, GPIO_IN, TIMER0_NORMP) 438 #define TIMER0_CH1_ON_PB14_OUT_NORMP \ 439 GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) 440 #define TIMER0_CH1_ON_PB0_INP_PRMP \ 441 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER0_PRMP) 442 #define TIMER0_CH1_ON_PB0_OUT_PRMP \ 443 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) 444 445 /* TIMER0_CH2 */ 446 #define TIMER0_CH2_PA10_INP_NORMP \ 447 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) 448 #define TIMER0_CH2_PA10_OUT_NORMP \ 449 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) 450 #define TIMER0_CH2_PA10_INP_PRMP \ 451 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) 452 #define TIMER0_CH2_PA10_OUT_PRMP \ 453 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) 454 455 /* TIMER0_CH2_ON */ 456 #define TIMER0_CH2_ON_PB15_NORMP \ 457 GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) 458 #define TIMER0_CH2_ON_PB1_PRMP \ 459 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) 460 461 /* TIMER0_CH3 */ 462 #define TIMER0_CH3_PA11_INP_NORMP \ 463 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) 464 #define TIMER0_CH3_PA11_OUT_NORMP \ 465 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) 466 #define TIMER0_CH3_PA11_INP_PRMP \ 467 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) 468 #define TIMER0_CH3_PA11_OUT_PRMP \ 469 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) 470 471 /* TIMER0_ETI */ 472 #define TIMER0_ETI_PA12_NORMP \ 473 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) 474 #define TIMER0_ETI_PA12_PRMP \ 475 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) 476 477 /* TIMER10_CH0 */ 478 #define TIMER10_CH0_PB9_INP \ 479 GD32_PINMUX_AFIO('B', 9, GPIO_IN, NORMP) 480 #define TIMER10_CH0_PB9_OUT \ 481 GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP) 482 483 /* TIMER11_CH0 */ 484 #define TIMER11_CH0_PB14_INP \ 485 GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) 486 #define TIMER11_CH0_PB14_OUT \ 487 GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) 488 489 /* TIMER11_CH11 */ 490 #define TIMER11_CH11_PB15_INP \ 491 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 492 #define TIMER11_CH11_PB15_OUT \ 493 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 494 495 /* TIMER12_CH0 */ 496 #define TIMER12_CH0_PA6_INP \ 497 GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) 498 #define TIMER12_CH0_PA6_OUT \ 499 GD32_PINMUX_AFIO('A', 6, ALTERNATE, NORMP) 500 501 /* TIMER13_CH0 */ 502 #define TIMER13_CH0_PA7_INP \ 503 GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) 504 #define TIMER13_CH0_PA7_OUT \ 505 GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) 506 507 /* TIMER1_CH0_ETI */ 508 #define TIMER1_CH0_ETI_PA0 \ 509 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 510 511 /* TIMER1_CH1 */ 512 #define TIMER1_CH1_PA1_INP_NORMP \ 513 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) 514 #define TIMER1_CH1_PA1_OUT_NORMP \ 515 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) 516 #define TIMER1_CH1_PA1_INP_PRMP2 \ 517 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) 518 #define TIMER1_CH1_PA1_OUT_PRMP2 \ 519 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) 520 #define TIMER1_CH1_PB3_INP_PRMP1 \ 521 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) 522 #define TIMER1_CH1_PB3_OUT_PRMP1 \ 523 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) 524 #define TIMER1_CH1_PB3_INP_FRMP \ 525 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) 526 #define TIMER1_CH1_PB3_OUT_FRMP \ 527 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) 528 529 /* TIMER1_CH2 */ 530 #define TIMER1_CH2_PA2_INP_NORMP \ 531 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) 532 #define TIMER1_CH2_PA2_OUT_NORMP \ 533 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) 534 #define TIMER1_CH2_PA2_INP_PRMP1 \ 535 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) 536 #define TIMER1_CH2_PA2_OUT_PRMP1 \ 537 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) 538 #define TIMER1_CH2_PB10_INP_PRMP2 \ 539 GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2) 540 #define TIMER1_CH2_PB10_OUT_PRMP2 \ 541 GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2) 542 #define TIMER1_CH2_PB10_INP_FRMP \ 543 GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP) 544 #define TIMER1_CH2_PB10_OUT_FRMP \ 545 GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP) 546 547 /* TIMER1_CH3 */ 548 #define TIMER1_CH3_PA3_INP_NORMP \ 549 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) 550 #define TIMER1_CH3_PA3_OUT_NORMP \ 551 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) 552 #define TIMER1_CH3_PA3_INP_PRMP1 \ 553 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) 554 #define TIMER1_CH3_PA3_OUT_PRMP1 \ 555 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) 556 #define TIMER1_CH3_PB11_INP_PRMP2 \ 557 GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2) 558 #define TIMER1_CH3_PB11_OUT_PRMP2 \ 559 GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2) 560 #define TIMER1_CH3_PB11_INP_FRMP \ 561 GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP) 562 #define TIMER1_CH3_PB11_OUT_FRMP \ 563 GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP) 564 565 /* TIMER2_CH0 */ 566 #define TIMER2_CH0_PA6_INP_NORMP \ 567 GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) 568 #define TIMER2_CH0_PA6_OUT_NORMP \ 569 GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) 570 #define TIMER2_CH0_PB4_INP_PRMP \ 571 GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) 572 #define TIMER2_CH0_PB4_OUT_PRMP \ 573 GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) 574 #define TIMER2_CH0_PC6_INP_FRMP \ 575 GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP) 576 #define TIMER2_CH0_PC6_OUT_FRMP \ 577 GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP) 578 579 /* TIMER2_CH1 */ 580 #define TIMER2_CH1_PA7_INP_NORMP \ 581 GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) 582 #define TIMER2_CH1_PA7_OUT_NORMP \ 583 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) 584 #define TIMER2_CH1_PB5_INP_PRMP \ 585 GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) 586 #define TIMER2_CH1_PB5_OUT_PRMP \ 587 GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) 588 #define TIMER2_CH1_PC7_INP_FRMP \ 589 GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP) 590 #define TIMER2_CH1_PC7_OUT_FRMP \ 591 GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP) 592 593 /* TIMER2_CH2 */ 594 #define TIMER2_CH2_PB0_INP_NORMP \ 595 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) 596 #define TIMER2_CH2_PB0_OUT_NORMP \ 597 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) 598 #define TIMER2_CH2_PB0_INP_PRMP \ 599 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) 600 #define TIMER2_CH2_PB0_OUT_PRMP \ 601 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) 602 #define TIMER2_CH2_PC8_INP_FRMP \ 603 GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP) 604 #define TIMER2_CH2_PC8_OUT_FRMP \ 605 GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP) 606 607 /* TIMER2_CH3 */ 608 #define TIMER2_CH3_PB1_INP_NORMP \ 609 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) 610 #define TIMER2_CH3_PB1_OUT_NORMP \ 611 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) 612 #define TIMER2_CH3_PB1_INP_PRMP \ 613 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) 614 #define TIMER2_CH3_PB1_OUT_PRMP \ 615 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) 616 #define TIMER2_CH3_PC9_INP_FRMP \ 617 GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP) 618 #define TIMER2_CH3_PC9_OUT_FRMP \ 619 GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP) 620 621 /* TIMER2_ETI */ 622 #define TIMER2_ETI_PD2 \ 623 GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) 624 625 /* TIMER3_CH0 */ 626 #define TIMER3_CH0_PB6_INP_NORMP \ 627 GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) 628 #define TIMER3_CH0_PB6_OUT_NORMP \ 629 GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) 630 631 /* TIMER3_CH1 */ 632 #define TIMER3_CH1_PB7_INP_NORMP \ 633 GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) 634 #define TIMER3_CH1_PB7_OUT_NORMP \ 635 GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) 636 637 /* TIMER3_CH2 */ 638 #define TIMER3_CH2_PB8_INP_NORMP \ 639 GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP) 640 #define TIMER3_CH2_PB8_OUT_NORMP \ 641 GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP) 642 643 /* TIMER3_CH3 */ 644 #define TIMER3_CH3_PB9_INP_NORMP \ 645 GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP) 646 #define TIMER3_CH3_PB9_OUT_NORMP \ 647 GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP) 648 649 /* TIMER4_CH0 */ 650 #define TIMER4_CH0_PA0_INP \ 651 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 652 #define TIMER4_CH0_PA0_OUT \ 653 GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP) 654 655 /* TIMER4_CH1 */ 656 #define TIMER4_CH1_PA1_INP \ 657 GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) 658 #define TIMER4_CH1_PA1_OUT \ 659 GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) 660 661 /* TIMER4_CH2 */ 662 #define TIMER4_CH2_PA2_INP \ 663 GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) 664 #define TIMER4_CH2_PA2_OUT \ 665 GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) 666 667 /* TIMER4_CH3 */ 668 #define TIMER4_CH3_PA3_INP \ 669 GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) 670 #define TIMER4_CH3_PA3_OUT \ 671 GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) 672 673 /* TIMER7_BKIN */ 674 #define TIMER7_BKIN_PA6 \ 675 GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) 676 677 /* TIMER7_CH0 */ 678 #define TIMER7_CH0_PC6_INP \ 679 GD32_PINMUX_AFIO('C', 6, GPIO_IN, NORMP) 680 #define TIMER7_CH0_PC6_OUT \ 681 GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) 682 683 /* TIMER7_CH0_ON */ 684 #define TIMER7_CH0_ON_PA7_INP \ 685 GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) 686 #define TIMER7_CH0_ON_PA7_OUT \ 687 GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) 688 689 /* TIMER7_CH1 */ 690 #define TIMER7_CH1_PC7_INP \ 691 GD32_PINMUX_AFIO('C', 7, GPIO_IN, NORMP) 692 #define TIMER7_CH1_PC7_OUT \ 693 GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) 694 695 /* TIMER7_CH1_ON */ 696 #define TIMER7_CH1_ON_PB0_INP \ 697 GD32_PINMUX_AFIO('B', 0, GPIO_IN, NORMP) 698 #define TIMER7_CH1_ON_PB0_OUT \ 699 GD32_PINMUX_AFIO('B', 0, ALTERNATE, NORMP) 700 701 /* TIMER7_CH2 */ 702 #define TIMER7_CH2_PC8_INP \ 703 GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP) 704 #define TIMER7_CH2_PC8_OUT \ 705 GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP) 706 707 /* TIMER7_CH2_ON */ 708 #define TIMER7_CH2_ON_PB1 \ 709 GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP) 710 711 /* TIMER7_CH3 */ 712 #define TIMER7_CH3_PC9_INP \ 713 GD32_PINMUX_AFIO('C', 9, GPIO_IN, NORMP) 714 #define TIMER7_CH3_PC9_OUT \ 715 GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP) 716 717 /* TIMER7_ETI */ 718 #define TIMER7_ETI_PA0 \ 719 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 720 721 /* TIMER8_CH0 */ 722 #define TIMER8_CH0_PA2_INP \ 723 GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) 724 #define TIMER8_CH0_PA2_OUT \ 725 GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) 726 727 /* TIMER8_CH1 */ 728 #define TIMER8_CH1_PA3_INP \ 729 GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) 730 #define TIMER8_CH1_PA3_OUT \ 731 GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) 732 733 /* TIMER9_CH0 */ 734 #define TIMER9_CH0_PB8_INP \ 735 GD32_PINMUX_AFIO('B', 8, GPIO_IN, NORMP) 736 #define TIMER9_CH0_PB8_OUT \ 737 GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP) 738 739 /* UART3_RX */ 740 #define UART3_RX_PC11 \ 741 GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP) 742 743 /* UART3_TX */ 744 #define UART3_TX_PC10 \ 745 GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP) 746 747 /* UART4_RX */ 748 #define UART4_RX_PD2 \ 749 GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) 750 751 /* UART4_TX */ 752 #define UART4_TX_PC12 \ 753 GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP) 754 755 /* USART0_CK */ 756 #define USART0_CK_PA8 \ 757 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 758 759 /* USART0_CTS */ 760 #define USART0_CTS_PA11 \ 761 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 762 763 /* USART0_RTS */ 764 #define USART0_RTS_PA12 \ 765 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 766 767 /* USART0_RX */ 768 #define USART0_RX_PA10_NORMP \ 769 GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) 770 #define USART0_RX_PB7_RMP \ 771 GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) 772 773 /* USART0_TX */ 774 #define USART0_TX_PA9_NORMP \ 775 GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) 776 #define USART0_TX_PB6_RMP \ 777 GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) 778 779 /* USART1_CK */ 780 #define USART1_CK_PA4_NORMP \ 781 GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) 782 783 /* USART1_CTS */ 784 #define USART1_CTS_PA0_NORMP \ 785 GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) 786 787 /* USART1_RTS */ 788 #define USART1_RTS_PA1_NORMP \ 789 GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) 790 791 /* USART1_RX */ 792 #define USART1_RX_PA3_NORMP \ 793 GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) 794 795 /* USART1_TX */ 796 #define USART1_TX_PA2_NORMP \ 797 GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) 798 799 /* USART2_CK */ 800 #define USART2_CK_PB12_NORMP \ 801 GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP) 802 #define USART2_CK_PC12_PRMP \ 803 GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP) 804 805 /* USART2_CTS */ 806 #define USART2_CTS_PB13_NORMP \ 807 GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP) 808 #define USART2_CTS_PB13_PRMP \ 809 GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP) 810 811 /* USART2_RTS */ 812 #define USART2_RTS_PB14_NORMP \ 813 GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP) 814 #define USART2_RTS_PB14_PRMP \ 815 GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP) 816 817 /* USART2_RX */ 818 #define USART2_RX_PB11_NORMP \ 819 GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP) 820 #define USART2_RX_PC11_PRMP \ 821 GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP) 822 823 /* USART2_TX */ 824 #define USART2_TX_PB10_NORMP \ 825 GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP) 826 #define USART2_TX_PC10_PRMP \ 827 GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP) 828 829 /* USBFS_DM */ 830 #define USBFS_DM_PA11_INP \ 831 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 832 #define USBFS_DM_PA11_OUT \ 833 GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) 834 835 /* USBFS_DP */ 836 #define USBFS_DP_PA12_INP \ 837 GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) 838 #define USBFS_DP_PA12_OUT \ 839 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 840 841 /* USBFS_ID */ 842 #define USBFS_ID_PA10_INP \ 843 GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) 844 #define USBFS_ID_PA10_OUT \ 845 GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) 846 847 /* USBFS_SOF */ 848 #define USBFS_SOF_PA8 \ 849 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 850 851 /* USBFS_VBUS */ 852 #define USBFS_VBUS_PA9 \ 853 GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) 854 855 /* WKUP */ 856 #define WKUP_PA0 \ 857 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 858
