1 /*!
2 \file gd32l23x_dac.c
3 \brief DAC driver
4
5 \version 2021-08-04, V1.0.0, firmware for GD32L23x
6 */
7
8 /*
9 Copyright (c) 2021, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32l23x_dac.h"
36
37 /* DAC register bit offset */
38 #define OUT1_REG_OFFSET ((uint32_t)0x00000010U)
39 #define DH_12BIT_OFFSET ((uint32_t)0x00000010U)
40 #define DH_8BIT_OFFSET ((uint32_t)0x00000008U)
41
42 /*!
43 \brief deinitialize DAC
44 \param[in] none
45 \param[out] none
46 \retval none
47 */
dac_deinit(void)48 void dac_deinit(void)
49 {
50 rcu_periph_reset_enable(RCU_DACRST);
51 rcu_periph_reset_disable(RCU_DACRST);
52 }
53
54 /*!
55 \brief enable DAC
56 \param[in] none
57 \param[out] none
58 \retval none
59 */
dac_enable(void)60 void dac_enable(void)
61 {
62 DAC_CTL0 |= DAC_CTL0_DEN;
63 }
64
65 /*!
66 \brief disable DAC
67 \param[in] none
68 \param[out] none
69 \retval none
70 */
dac_disable(void)71 void dac_disable(void)
72 {
73 DAC_CTL0 &= ~DAC_CTL0_DEN;
74 }
75
76 /*!
77 \brief enable DAC DMA function
78 \param[in] none
79 \param[out] none
80 \retval none
81 */
dac_dma_enable(void)82 void dac_dma_enable(void)
83 {
84 DAC_CTL0 |= DAC_CTL0_DDMAEN;
85 }
86
87 /*!
88 \brief disable DAC DMA function
89 \param[in] none
90 \param[out] none
91 \retval none
92 */
dac_dma_disable(void)93 void dac_dma_disable(void)
94 {
95 DAC_CTL0 &= ~DAC_CTL0_DDMAEN;
96 }
97
98 /*!
99 \brief enable DAC output buffer
100 \param[in] none
101 \param[out] none
102 \retval none
103 */
dac_output_buffer_enable(void)104 void dac_output_buffer_enable(void)
105 {
106 DAC_CTL0 &= ~DAC_CTL0_DBOFF;
107 }
108
109 /*!
110 \brief disable DAC output buffer
111 \param[in] none
112 \param[out] none
113 \retval none
114 */
dac_output_buffer_disable(void)115 void dac_output_buffer_disable(void)
116 {
117 DAC_CTL0 |= DAC_CTL0_DBOFF;
118 }
119
120 /*!
121 \brief get DAC output value
122 \param[in] none
123 \param[out] none
124 \retval DAC output data: 0~4095
125 */
dac_output_value_get(void)126 uint16_t dac_output_value_get(void)
127 {
128 uint16_t data = 0U;
129 data = (uint16_t)OUT_DO;
130
131 return data;
132 }
133
134 /*!
135 \brief set DAC data holding register value
136 \param[in] dac_align: DAC data alignment mode
137 only one parameter can be selected which is shown as below:
138 \arg DAC_ALIGN_12B_R: 12-bit right-aligned data
139 \arg DAC_ALIGN_12B_L: 12-bit left-aligned data
140 \arg DAC_ALIGN_8B_R: 8-bit right-aligned data
141 \param[in] data: data to be loaded, 0~4095
142 \param[out] none
143 \retval none
144 */
dac_data_set(uint32_t dac_align,uint16_t data)145 void dac_data_set(uint32_t dac_align, uint16_t data)
146 {
147 switch(dac_align) {
148 /* 12-bit right-aligned data */
149 case DAC_ALIGN_12B_R:
150 OUT_R12DH = data;
151 break;
152 /* 12-bit left-aligned data */
153 case DAC_ALIGN_12B_L:
154 OUT_L12DH = data;
155 break;
156 /* 8-bit right-aligned data */
157 case DAC_ALIGN_8B_R:
158 OUT_R8DH = data;
159 break;
160 default:
161 break;
162 }
163 }
164
165 /*!
166 \brief enable DAC trigger
167 \param[in] none
168 \param[out] none
169 \retval none
170 */
dac_trigger_enable(void)171 void dac_trigger_enable(void)
172 {
173 DAC_CTL0 |= DAC_CTL0_DTEN;
174 }
175
176 /*!
177 \brief disable DAC trigger
178 \param[in] none
179 \param[out] none
180 \retval none
181 */
dac_trigger_disable(void)182 void dac_trigger_disable(void)
183 {
184 DAC_CTL0 &= ~DAC_CTL0_DTEN;
185 }
186
187 /*!
188 \brief configure DAC trigger source
189 \param[in] triggersource: external triggers of DAC
190 only one parameter can be selected which is shown as below:
191 \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
192 \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO
193 \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
194 \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
195 \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
196 \arg DAC_TRIGGER_SOFTWARE: software trigger
197 \param[out] none
198 \retval none
199 */
dac_trigger_source_config(uint32_t triggersource)200 void dac_trigger_source_config(uint32_t triggersource)
201 {
202 /* configure DAC trigger source */
203 DAC_CTL0 &= (uint32_t)(~DAC_CTL0_DTSEL);
204 DAC_CTL0 |= triggersource;
205 }
206
207 /*!
208 \brief enable DAC software trigger
209 \param[in] none
210 \retval none
211 */
dac_software_trigger_enable(void)212 void dac_software_trigger_enable(void)
213 {
214 DAC_SWT |= DAC_SWT_SWTR;
215 }
216
217 /*!
218 \brief disable DAC software trigger
219 \param[in] none
220 \param[out] none
221 \retval none
222 */
dac_software_trigger_disable(void)223 void dac_software_trigger_disable(void)
224 {
225 DAC_SWT &= ~DAC_SWT_SWTR;
226 }
227
228 /*!
229 \brief configure DAC wave mode
230 \param[in] wave_mode: DAC wave mode
231 only one parameter can be selected which is shown as below:
232 \arg DAC_WAVE_DISABLE: wave mode disable
233 \arg DAC_WAVE_MODE_LFSR: LFSR noise mode
234 \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
235 \param[out] none
236 \retval none
237 */
dac_wave_mode_config(uint32_t wave_mode)238 void dac_wave_mode_config(uint32_t wave_mode)
239 {
240 /* configure DAC wave mode */
241 DAC_CTL0 &= ~DAC_CTL0_DWM;
242 DAC_CTL0 |= wave_mode;
243 }
244
245 /*!
246 \brief configure DAC wave bit width
247 \param[in] bit_width: DAC noise wave bit width
248 only one parameter can be selected which is shown as below:
249 \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
250 \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
251 \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
252 \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
253 \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
254 \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
255 \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
256 \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
257 \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
258 \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
259 \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
260 \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
261 \param[out] none
262 \retval none
263 */
dac_wave_bit_width_config(uint32_t bit_width)264 void dac_wave_bit_width_config(uint32_t bit_width)
265 {
266 /* configure DAC wave bit width */
267 DAC_CTL0 &= ~DAC_CTL0_DWBW;
268 DAC_CTL0 |= bit_width;
269 }
270
271 /*!
272 \brief configure DAC LFSR noise mode
273 \param[in] unmask_bits: LFSR noise unmask bits
274 only one parameter can be selected which is shown as below:
275 \arg DAC_LFSR_BIT0: unmask the LFSR bit0
276 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
277 \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
278 \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
279 \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
280 \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
281 \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
282 \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
283 \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
284 \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
285 \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
286 \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
287 \param[out] none
288 \retval none
289 */
dac_lfsr_noise_config(uint32_t unmask_bits)290 void dac_lfsr_noise_config(uint32_t unmask_bits)
291 {
292 /* configure DAC LFSR noise mode */
293 DAC_CTL0 &= ~DAC_CTL0_DWBW;
294 DAC_CTL0 |= unmask_bits;
295 }
296
297 /*!
298 \brief configure DAC triangle noise mode
299 \param[in] amplitude: the amplitude of the triangle
300 only one parameter can be selected which is shown as below:
301 \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
302 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
303 \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
304 \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
305 \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
306 \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
307 \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
308 \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
309 \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
310 \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
311 \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
312 \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
313 \param[out] none
314 \retval none
315 */
dac_triangle_noise_config(uint32_t amplitude)316 void dac_triangle_noise_config(uint32_t amplitude)
317 {
318 /* configure DAC triangle noise mode */
319 DAC_CTL0 &= ~DAC_CTL0_DWBW;
320 DAC_CTL0 |= amplitude;
321 }
322
323 /*!
324 \brief get DAC flag
325 \param[in] dac_flag: DAC flag
326 only one parameter can be selected which is shown as below:
327 \arg DAC_FLAG_DDUDR: DMA underrun flag
328 \param[out] none
329 \retval FlagStatus: SET or RESET
330 */
dac_flag_get(uint32_t flag)331 FlagStatus dac_flag_get(uint32_t flag)
332 {
333 /* check DAC flag */
334 if(DAC_FLAG_DDUDR == flag) {
335 if(RESET != (DAC_STAT0 & DAC_STAT0_DDUDR)) {
336 return SET;
337 }
338 }
339 return RESET;
340 }
341
342 /*!
343 \brief clear DAC flag
344 \param[in] flag: DAC flag
345 only one parameter can be selected which is shown as below:
346 \arg DAC_FLAG_DDUDR: DMA underrun flag
347 \param[out] none
348 \retval none
349 */
dac_flag_clear(uint32_t flag)350 void dac_flag_clear(uint32_t flag)
351 {
352 /* clear DAC_OUT flag */
353 if(DAC_FLAG_DDUDR == flag) {
354 DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR;
355 }
356 }
357
358 /*!
359 \brief enable DAC interrupt
360 \param[in] interrupt: the DAC interrupt
361 only one parameter can be selected which is shown as below:
362 \arg DAC_INT_DDUDRIE: DMA underrun interrupt enable
363 \param[out] none
364 \retval none
365 */
dac_interrupt_enable(uint32_t interrupt)366 void dac_interrupt_enable(uint32_t interrupt)
367 {
368 /* enable DAC interrupt */
369 if(DAC_INT_DDUDRIE == interrupt) {
370 DAC_CTL0 |= (uint32_t)DAC_CTL0_DDUDRIE;
371 }
372 }
373
374 /*!
375 \brief disable DAC interrupt
376 \param[in] interrupt: the DAC interrupt
377 only one parameter can be selected which is shown as below:
378 \arg DAC_INT_DDUDRIE: DMA underrun interrupt disable
379 \param[out] none
380 \retval none
381 */
dac_interrupt_disable(uint32_t interrupt)382 void dac_interrupt_disable(uint32_t interrupt)
383 {
384 /* disable DAC interrupt */
385 if(DAC_INT_DDUDRIE == interrupt) {
386 DAC_CTL0 &= (uint32_t)(~DAC_CTL0_DDUDRIE);
387 }
388 }
389
390 /*!
391 \brief get DAC interrupt flag
392 \param[in] int_flag: DAC interrupt flag
393 only one parameter can be selected which is shown as below:
394 \arg DAC_INT_FLAG_DDUDR: DMA underrun interrupt flag
395 \param[out] none
396 \retval the state of DAC interrupt flag(SET or RESET)
397 */
dac_interrupt_flag_get(uint32_t int_flag)398 FlagStatus dac_interrupt_flag_get(uint32_t int_flag)
399 {
400 uint32_t reg1 = 0U, reg2 = 0U;
401
402 /* check DAC interrupt flag */
403 if(DAC_INT_FLAG_DDUDR == int_flag) {
404 reg1 = DAC_STAT0 & DAC_STAT0_DDUDR;
405 reg2 = DAC_CTL0 & DAC_CTL0_DDUDRIE;
406 }
407
408 /*get DAC interrupt flag status */
409 if((RESET != reg1) && (RESET != reg2)) {
410 return SET;
411 } else {
412 return RESET;
413 }
414 }
415
416 /*!
417 \brief clear DAC interrupt flag
418 \param[in] int_flag: DAC interrupt flag
419 only one parameter can be selected which is shown as below:
420 \arg DAC_INT_FLAG_DDUDR: DMA underrun interrupt flag
421 \param[out] none
422 \retval none
423 */
dac_interrupt_flag_clear(uint32_t int_flag)424 void dac_interrupt_flag_clear(uint32_t int_flag)
425 {
426 /* clear DAC interrupt flag */
427 if(DAC_INT_FLAG_DDUDR == int_flag) {
428 DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR;
429 }
430 }
431
