1 /*! 2 \file gd32l23x_dbg.h 3 \brief definitions for the DBG 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_DBG_H 36 #define GD32L23X_DBG_H 37 38 #include "gd32l23x.h" 39 40 /* DBG definitions */ 41 #define DBG DBG_BASE /*!< DBG base address */ 42 43 /* registers definitions */ 44 #define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ 45 #define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */ 46 #define DBG_CTL1 REG32(DBG + 0x00000008U) /*!< DBG control register 1 */ 47 48 /* bits definitions */ 49 /* DBG_ID */ 50 #define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ 51 52 /* DBG_CTL0 */ 53 #define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ 54 #define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ 55 #define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ 56 #define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< hold FWDGT counter when core is halted */ 57 #define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< hold WWDGT counter when core is halted */ 58 #define DBG_CTL0_TIMER1_HOLD BIT(12) /*!< hold TIMER1 counter when core is halted */ 59 #define DBG_CTL0_TIMER2_HOLD BIT(13) /*!< hold TIMER2 counter when core is halted */ 60 #define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ 61 #define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ 62 #define DBG_CTL0_TIMER5_HOLD BIT(20) /*!< hold TIMER5 counter when core is halted */ 63 #define DBG_CTL0_TIMER6_HOLD BIT(21) /*!< hold TIMER6 counter when core is halted */ 64 #define DBG_CTL0_TIMER8_HOLD BIT(23) /*!< hold TIMER8 counter when core is halted */ 65 #define DBG_CTL0_TIMER11_HOLD BIT(26) /*!< hold TIMER11 counter when core is halted */ 66 67 /* DBG_CTL1 */ 68 #define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ 69 #define DBG_CTL1_LPTIMER_HOLD BIT(16) /*!< hold LPTIMER counter when core is halted */ 70 #define DBG_CTL1_I2C2_HOLD BIT(17) /*!< hold I2C2 smbus when core is halted */ 71 72 /* constants definitions */ 73 /* keep debugger connection */ 74 #define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ 75 #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ 76 #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ 77 78 /* define the peripheral debug hold bit position and its register index offset */ 79 #define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) 80 #define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) 81 #define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 82 83 /* register index */ 84 enum dbg_reg_idx { 85 DBG_IDX_CTL0 = 0x04U, 86 DBG_IDX_CTL1 = 0x08U, 87 }; 88 89 /* peripherals hold bit */ 90 typedef enum { 91 DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */ 92 DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */ 93 DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER1 hold bit */ 94 DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 13U), /*!< TIMER2 hold bit */ 95 DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */ 96 DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */ 97 DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 20U), /*!< TIMER5 hold bit */ 98 DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 21U), /*!< TIMER6 hold bit */ 99 DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 23U), /*!< TIMER8 hold bit */ 100 DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 26U), /*!< TIMER11 hold bit */ 101 DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */ 102 DBG_LPTIMER_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< LPTIMER hold bit */ 103 DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< I2C2 hold bit */ 104 } dbg_periph_enum; 105 106 /* function declarations */ 107 /* deinitialize the DBG */ 108 void dbg_deinit(void); 109 /* read DBG_ID code register */ 110 uint32_t dbg_id_get(void); 111 112 /* enable low power behavior when the MCU is in debug mode */ 113 void dbg_low_power_enable(uint32_t dbg_low_power); 114 /* disable low power behavior when the MCU is in debug mode */ 115 void dbg_low_power_disable(uint32_t dbg_low_power); 116 117 /* enable peripheral behavior when the MCU is in debug mode */ 118 void dbg_periph_enable(dbg_periph_enum dbg_periph); 119 /* disable peripheral behavior when the MCU is in debug mode */ 120 void dbg_periph_disable(dbg_periph_enum dbg_periph); 121 122 #endif /* GD32L23X_DBG_H */ 123
