1 /*!
2 \file gd32f3x0_dbg.c
3 \brief DBG driver
4
5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0
6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0
7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0
8 */
9
10 /*
11 Copyright (c) 2020, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #include "gd32f3x0_dbg.h"
38
39 #define DBG_RESET_VAL ((uint32_t)0x00000000U) /*!< DBG reset value */
40
41 /*!
42 \brief deinitialize the DBG
43 \param[in] none
44 \param[out] none
45 \retval none
46 */
dbg_deinit(void)47 void dbg_deinit(void)
48 {
49 DBG_CTL0 = DBG_RESET_VAL;
50 DBG_CTL1 = DBG_RESET_VAL;
51 }
52
53 /*!
54 \brief read DBG_ID code register
55 \param[in] none
56 \param[out] none
57 \retval DBG_ID code
58 */
dbg_id_get(void)59 uint32_t dbg_id_get(void)
60 {
61 return DBG_ID;
62 }
63
64 /*!
65 \brief enable low power behavior when the mcu is in debug mode
66 \param[in] dbg_low_power:
67 one or more parameters can be selected which are shown as below:
68 \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
69 \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
70 \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
71 \param[out] none
72 \retval none
73 */
dbg_low_power_enable(uint32_t dbg_low_power)74 void dbg_low_power_enable(uint32_t dbg_low_power)
75 {
76 DBG_CTL0 |= dbg_low_power;
77 }
78
79 /*!
80 \brief disable low power behavior when the mcu is in debug mode
81 \param[in] dbg_low_power:
82 one or more parameters can be selected which are shown as below:
83 \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
84 \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
85 \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
86 \param[out] none
87 \retval none
88 */
dbg_low_power_disable(uint32_t dbg_low_power)89 void dbg_low_power_disable(uint32_t dbg_low_power)
90 {
91 DBG_CTL0 &= ~dbg_low_power;
92 }
93
94 /*!
95 \brief enable peripheral behavior when the mcu is in debug mode
96 \param[in] dbg_periph: refer to dbg_periph_enum
97 only one parameter can be selected which are shown as below:
98 \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode
99 \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
100 \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode
101 \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
102 \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
103 \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted
104 \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
105 \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
106 \param[out] none
107 \retval none
108 */
dbg_periph_enable(dbg_periph_enum dbg_periph)109 void dbg_periph_enable(dbg_periph_enum dbg_periph)
110 {
111 DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
112 }
113
114 /*!
115 \brief disable peripheral behavior when the mcu is in debug mode
116 \param[in] dbg_periph: refer to dbg_periph_enum
117 only one parameter can be selected which are shown as below:
118 \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode
119 \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
120 \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode
121 \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
122 \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
123 \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted
124 \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
125 \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
126 \param[out] none
127 \retval none
128 */
dbg_periph_disable(dbg_periph_enum dbg_periph)129 void dbg_periph_disable(dbg_periph_enum dbg_periph)
130 {
131 DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
132 }
133
