1 /*!
2 \file gd32f3x0_dac.c
3 \brief DAC driver
4
5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0
6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0
7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0
8 */
9
10 /*
11 Copyright (c) 2020, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #ifdef GD32F350
38 #include "gd32f3x0_dac.h"
39
40 /*!
41 \brief deinitialize DAC
42 \param[in] none
43 \param[out] none
44 \retval none
45 */
dac_deinit(void)46 void dac_deinit(void)
47 {
48 rcu_periph_reset_enable(RCU_DACRST);
49 rcu_periph_reset_disable(RCU_DACRST);
50 }
51
52 /*!
53 \brief enable DAC
54 \param[in] none
55 \param[out] none
56 \retval none
57 */
dac_enable(void)58 void dac_enable(void)
59 {
60 DAC_CTL |= DAC_CTL_DEN;
61 }
62
63 /*!
64 \brief disable DAC
65 \param[in] none
66 \param[out] none
67 \retval none
68 */
dac_disable(void)69 void dac_disable(void)
70 {
71 DAC_CTL &= ~DAC_CTL_DEN;
72 }
73
74 /*!
75 \brief enable DAC DMA
76 \param[in] none
77 \param[out] none
78 \retval none
79 */
dac_dma_enable(void)80 void dac_dma_enable(void)
81 {
82 DAC_CTL |= DAC_CTL_DDMAEN;
83 }
84
85 /*!
86 \brief disable DAC DMA
87 \param[in] none
88 \param[out] none
89 \retval none
90 */
dac_dma_disable(void)91 void dac_dma_disable(void)
92 {
93 DAC_CTL &= ~DAC_CTL_DDMAEN;
94 }
95
96 /*!
97 \brief enable DAC output buffer
98 \param[in] none
99 \param[out] none
100 \retval none
101 */
dac_output_buffer_enable(void)102 void dac_output_buffer_enable(void)
103 {
104 DAC_CTL &= ~DAC_CTL_DBOFF;
105 }
106
107 /*!
108 \brief disable DAC output buffer
109 \param[in] none
110 \param[out] none
111 \retval none
112 */
dac_output_buffer_disable(void)113 void dac_output_buffer_disable(void)
114 {
115 DAC_CTL |= DAC_CTL_DBOFF;
116 }
117
118 /*!
119 \brief enable DAC trigger
120 \param[in] none
121 \param[out] none
122 \retval none
123 */
dac_trigger_enable(void)124 void dac_trigger_enable(void)
125 {
126 DAC_CTL |= DAC_CTL_DTEN;
127 }
128
129 /*!
130 \brief disable DAC trigger
131 \param[in] none
132 \param[out] none
133 \retval none
134 */
dac_trigger_disable(void)135 void dac_trigger_disable(void)
136 {
137 DAC_CTL &= ~DAC_CTL_DTEN;
138 }
139
140 /*!
141 \brief enable DAC software trigger
142 \param[in] none
143 \param[out] none
144 \retval none
145 */
dac_software_trigger_enable(void)146 void dac_software_trigger_enable(void)
147 {
148 DAC_SWT |= DAC_SWT_SWTR;
149 }
150
151 /*!
152 \brief disable DAC software trigger
153 \param[in] none
154 \param[out] none
155 \retval none
156 */
dac_software_trigger_disable(void)157 void dac_software_trigger_disable(void)
158 {
159 DAC_SWT &= ~DAC_SWT_SWTR;
160 }
161
162 /*!
163 \brief enable DAC interrupt(DAC DMA underrun interrupt)
164 \param[in] none
165 \param[out] none
166 \retval none
167 */
dac_interrupt_enable(void)168 void dac_interrupt_enable(void)
169 {
170 DAC_CTL |= DAC_CTL_DDUDRIE;
171 }
172
173 /*!
174 \brief disable DAC interrupt(DAC DMA underrun interrupt)
175 \param[in] none
176 \param[out] none
177 \retval none
178 */
dac_interrupt_disable(void)179 void dac_interrupt_disable(void)
180 {
181 DAC_CTL &= ~DAC_CTL_DDUDRIE;
182 }
183
184 /*!
185 \brief set DAC tgigger source
186 \param[in] triggersource: external triggers of DAC
187 \arg DAC_TRIGGER_T1_TRGO: trigger source is TIMER1 TRGO
188 \arg DAC_TRIGGER_T2_TRGO: trigger source is TIMER2 TRGO
189 \arg DAC_TRIGGER_T5_TRGO: trigger source is TIMER5 TRGO
190 \arg DAC_TRIGGER_T14_TRGO: trigger source is TIMER14 TRGO
191 \arg DAC_TRIGGER_EXTI_9: trigger source is EXTI interrupt line9 event
192 \arg DAC_TRIGGER_SOFTWARE: software trigger
193 \param[out] none
194 \retval none
195 */
dac_trigger_source_config(uint32_t triggersource)196 void dac_trigger_source_config(uint32_t triggersource)
197 {
198 DAC_CTL &= ~DAC_CTL_DTSEL;
199 DAC_CTL |= triggersource;
200 }
201
202 /*!
203 \brief configure DAC wave mode
204 \param[in] wave_mode
205 \arg DAC_WAVE_DISABLE: wave disable
206 \arg DAC_WAVE_MODE_LFSR: LFSR noise mode
207 \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
208 \param[out] none
209 \retval none
210 */
dac_wave_mode_config(uint32_t wave_mode)211 void dac_wave_mode_config(uint32_t wave_mode)
212 {
213 DAC_CTL &= ~DAC_CTL_DWM;
214 DAC_CTL |= wave_mode;
215 }
216
217 /*!
218 \brief configure DAC wave bit width
219 \param[in] bit_width
220 \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
221 \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
222 \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
223 \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
224 \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
225 \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
226 \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
227 \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
228 \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
229 \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
230 \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
231 \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
232 \param[out] none
233 \retval none
234 */
dac_wave_bit_width_config(uint32_t bit_width)235 void dac_wave_bit_width_config(uint32_t bit_width)
236 {
237 DAC_CTL &= ~DAC_CTL_DWBW;
238 DAC_CTL |= bit_width;
239 }
240
241 /*!
242 \brief configure DAC LFSR noise mode
243 \param[in] unmask_bits
244 \arg DAC_LFSR_BIT0: unmask the LFSR bit0
245 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
246 \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
247 \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
248 \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
249 \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
250 \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
251 \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
252 \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
253 \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
254 \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
255 \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
256 \param[out] none
257 \retval none
258 */
dac_lfsr_noise_config(uint32_t unmask_bits)259 void dac_lfsr_noise_config(uint32_t unmask_bits)
260 {
261 DAC_CTL &= ~DAC_CTL_DWBW;
262 DAC_CTL |= unmask_bits;
263 }
264
265 /*!
266 \brief configure DAC triangle noise mode
267 \param[in] amplitude
268 \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
269 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
270 \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
271 \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
272 \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
273 \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
274 \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
275 \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
276 \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
277 \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
278 \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
279 \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
280 \param[out] none
281 \retval none
282 */
dac_triangle_noise_config(uint32_t amplitude)283 void dac_triangle_noise_config(uint32_t amplitude)
284 {
285 DAC_CTL &= ~DAC_CTL_DWBW;
286 DAC_CTL |= amplitude;
287 }
288
289 /*!
290 \brief get DAC output value
291 \param[in] none
292 \param[out] none
293 \retval DAC output data
294 */
dac_output_value_get(void)295 uint16_t dac_output_value_get(void)
296 {
297 uint16_t data = 0U;
298 data = (uint16_t)DAC_DO;
299 return data;
300 }
301
302 /*!
303 \brief get the specified DAC flag(DAC DMA underrun flag)
304 \param[in] none
305 \param[out] none
306 \retval the state of dac bit(SET or RESET)
307 */
dac_flag_get(void)308 FlagStatus dac_flag_get(void)
309 {
310 /* check the DMA underrun flag */
311 if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR)){
312 return SET;
313 }else{
314 return RESET;
315 }
316 }
317
318 /*!
319 \brief clear the specified DAC flag(DAC DMA underrun flag)
320 \param[in] none
321 \param[out] none
322 \retval none
323 */
dac_flag_clear(void)324 void dac_flag_clear(void)
325 {
326 DAC_STAT |= DAC_STAT_DDUDR;
327 }
328
329 /*!
330 \brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
331 \param[in] none
332 \param[out] none
333 \retval the state of DAC interrupt flag(SET or RESET)
334 */
dac_interrupt_flag_get(void)335 FlagStatus dac_interrupt_flag_get(void)
336 {
337 FlagStatus temp_flag = RESET;
338 uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
339 /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
340 ddudr_flag = DAC_STAT & DAC_STAT_DDUDR;
341 ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE;
342 if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
343 temp_flag = SET;
344 }
345 return temp_flag;
346 }
347
348 /*!
349 \brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
350 \param[in] none
351 \param[out] none
352 \retval none
353 */
dac_interrupt_flag_clear(void)354 void dac_interrupt_flag_clear(void)
355 {
356 DAC_STAT |= DAC_STAT_DDUDR;
357 }
358
359 /*!
360 \brief set DAC data holding register value
361 \param[in] dac_align
362 \arg DAC_ALIGN_8B_R: data right 8b alignment
363 \arg DAC_ALIGN_12B_R: data right 12b alignment
364 \arg DAC_ALIGN_12B_L: data left 12b alignment
365 \param[in] data: data to be loaded
366 \param[out] none
367 \retval none
368 */
dac_data_set(uint32_t dac_align,uint16_t data)369 void dac_data_set(uint32_t dac_align, uint16_t data)
370 {
371 switch(dac_align){
372 /* data right 12b alignment */
373 case DAC_ALIGN_12B_R:
374 DAC_R12DH = data;
375 break;
376 /* data left 12b alignment */
377 case DAC_ALIGN_12B_L:
378 DAC_L12DH = data;
379 break;
380 /* data right 8b alignment */
381 case DAC_ALIGN_8B_R:
382 DAC_R8DH = data;
383 break;
384 default:
385 break;
386 }
387 }
388 #endif /* GD32F350 */
389
