1 /*! 2 \file gd32f3x0_dma.h 3 \brief definitions for the DMA 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_DMA_H 38 #define GD32F3X0_DMA_H 39 40 #include "gd32f3x0.h" 41 42 /* DMA definitions */ 43 #define DMA DMA_BASE /*!< DMA base address */ 44 45 /* registers definitions */ 46 #define DMA_INTF REG32(DMA + 0x00000000U) /*!< DMA interrupt flag register */ 47 #define DMA_INTC REG32(DMA + 0x00000004U) /*!< DMA interrupt flag clear register */ 48 #define DMA_CH0CTL REG32(DMA + 0x00000008U) /*!< DMA channel 0 control register */ 49 #define DMA_CH0CNT REG32(DMA + 0x0000000CU) /*!< DMA channel 0 counter register */ 50 #define DMA_CH0PADDR REG32(DMA + 0x00000010U) /*!< DMA channel 0 peripheral base address register */ 51 #define DMA_CH0MADDR REG32(DMA + 0x00000014U) /*!< DMA channel 0 memory base address register */ 52 #define DMA_CH1CTL REG32(DMA + 0x0000001CU) /*!< DMA channel 1 control register */ 53 #define DMA_CH1CNT REG32(DMA + 0x00000020U) /*!< DMA channel 1 counter register */ 54 #define DMA_CH1PADDR REG32(DMA + 0x00000024U) /*!< DMA channel 1 peripheral base address register */ 55 #define DMA_CH1MADDR REG32(DMA + 0x00000028U) /*!< DMA channel 1 memory base address register */ 56 #define DMA_CH2CTL REG32(DMA + 0x00000030U) /*!< DMA channel 2 control register */ 57 #define DMA_CH2CNT REG32(DMA + 0x00000034U) /*!< DMA channel 2 counter register */ 58 #define DMA_CH2PADDR REG32(DMA + 0x00000038U) /*!< DMA channel 2 peripheral base address register */ 59 #define DMA_CH2MADDR REG32(DMA + 0x0000003CU) /*!< DMA channel 2 memory base address register */ 60 #define DMA_CH3CTL REG32(DMA + 0x00000044U) /*!< DMA channel 3 control register */ 61 #define DMA_CH3CNT REG32(DMA + 0x00000048U) /*!< DMA channel 3 counter register */ 62 #define DMA_CH3PADDR REG32(DMA + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */ 63 #define DMA_CH3MADDR REG32(DMA + 0x00000050U) /*!< DMA channel 3 memory base address register */ 64 #define DMA_CH4CTL REG32(DMA + 0x00000058U) /*!< DMA channel 4 control register */ 65 #define DMA_CH4CNT REG32(DMA + 0x0000005CU) /*!< DMA channel 4 counter register */ 66 #define DMA_CH4PADDR REG32(DMA + 0x00000060U) /*!< DMA channel 4 peripheral base address register */ 67 #define DMA_CH4MADDR REG32(DMA + 0x00000064U) /*!< DMA channel 4 memory base address register */ 68 #define DMA_CH5CTL REG32(DMA + 0x0000006CU) /*!< DMA channel 5 control register */ 69 #define DMA_CH5CNT REG32(DMA + 0x00000070U) /*!< DMA channel 5 counter register */ 70 #define DMA_CH5PADDR REG32(DMA + 0x00000074U) /*!< DMA channel 5 peripheral base address register */ 71 #define DMA_CH5MADDR REG32(DMA + 0x00000078U) /*!< DMA channel 5 memory base address register */ 72 #define DMA_CH6CTL REG32(DMA + 0x00000080U) /*!< DMA channel 6 control register */ 73 #define DMA_CH6CNT REG32(DMA + 0x00000084U) /*!< DMA channel 6 counter register */ 74 #define DMA_CH6PADDR REG32(DMA + 0x00000088U) /*!< DMA channel 6 peripheral base address register */ 75 #define DMA_CH6MADDR REG32(DMA + 0x0000008CU) /*!< DMA channel 6 memory base address register */ 76 77 /* bits definitions */ 78 /* DMA_INTF */ 79 #define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ 80 #define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ 81 #define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ 82 #define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ 83 84 /* DMA_INTC */ 85 #define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ 86 #define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ 87 #define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ 88 #define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ 89 90 /* DMA_CHxCTL,x=0..6 */ 91 #define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ 92 #define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ 93 #define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ 94 #define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ 95 #define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ 96 #define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ 97 #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ 98 #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ 99 #define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ 100 #define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ 101 #define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ 102 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ 103 104 /* DMA_CHxCNT,x=0..6 */ 105 #define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ 106 107 /* DMA_CHxPADDR,x=0..6 */ 108 #define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ 109 110 /* DMA_CHxMADDR,x=0..6 */ 111 #define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ 112 113 /* constants definitions */ 114 /* DMA channel select */ 115 typedef enum 116 { 117 DMA_CH0 = 0, /*!< DMA Channel0 */ 118 DMA_CH1, /*!< DMA Channel1 */ 119 DMA_CH2, /*!< DMA Channel2 */ 120 DMA_CH3, /*!< DMA Channel3 */ 121 DMA_CH4, /*!< DMA Channel4 */ 122 DMA_CH5, /*!< DMA Channel5 */ 123 DMA_CH6 /*!< DMA Channel6 */ 124 } dma_channel_enum; 125 126 /* DMA initialize struct */ 127 typedef struct 128 { 129 uint32_t periph_addr; /*!< peripheral base address */ 130 uint32_t periph_width; /*!< transfer data size of peripheral */ 131 uint8_t periph_inc; /*!< peripheral increasing mode */ 132 uint32_t memory_addr; /*!< memory base address */ 133 uint32_t memory_width; /*!< transfer data size of memory */ 134 uint8_t memory_inc; /*!< memory increasing mode */ 135 uint8_t direction; /*!< channel data transfer direction */ 136 uint32_t number; /*!< channel transfer number */ 137 uint32_t priority; /*!< channel priority level */ 138 } dma_parameter_struct; 139 140 /* DMA reset value */ 141 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ 142 #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ 143 #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ 144 #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ 145 #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ 146 DMA_INTF_HTFIF | DMA_INTF_ERRIF) 147 148 #define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ 149 150 /* DMA_CHCTL base address */ 151 #define DMA_CHXCTL_BASE (DMA + (uint32_t)0x00000008U) /*!< the base address of DMA channel CHXCTL register */ 152 #define DMA_CHXCNT_BASE (DMA + (uint32_t)0x0000000CU) /*!< the base address of DMA channel CHXCNT register */ 153 #define DMA_CHXPADDR_BASE (DMA + (uint32_t)0x00000010U) /*!< the base address of DMA channel CHXPADDR register */ 154 #define DMA_CHXMADDR_BASE (DMA + (uint32_t)0x00000014U) /*!< the base address of DMA channel CHXMADDR register */ 155 156 /* DMA channel shift bit */ 157 #define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ 158 #define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ 159 #define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ 160 #define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ 161 162 /* DMA_INTF register */ 163 /* interrupt flag bits */ 164 #define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ 165 #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ 166 #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ 167 #define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ 168 169 /* flag bits */ 170 #define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ 171 #define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ 172 #define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ 173 #define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ 174 175 /* DMA_CHxCTL register */ 176 /* interrupt enable bits */ 177 #define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ 178 #define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ 179 #define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ 180 181 /* transfer direction */ 182 #define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ 183 #define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ 184 185 /* peripheral increasing mode */ 186 #define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ 187 #define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ 188 189 /* memory increasing mode */ 190 #define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ 191 #define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ 192 193 /* transfer data size of peripheral */ 194 #define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ 195 #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ 196 #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ 197 #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ 198 199 /* transfer data size of memory */ 200 #define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ 201 #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ 202 #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ 203 #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ 204 205 /* channel priority level */ 206 #define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ 207 #define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ 208 #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ 209 #define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ 210 #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ 211 212 /* DMA_CHxCNT register */ 213 /* transfer counter */ 214 #define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT 215 216 /* function declarations */ 217 /* deinitialize DMA a channel registers */ 218 void dma_deinit(dma_channel_enum channelx); 219 /* initialize the parameters of DMA struct with the default values */ 220 void dma_struct_para_init(dma_parameter_struct* init_struct); 221 /* initialize DMA channel */ 222 void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct); 223 /* enable DMA circulation mode */ 224 void dma_circulation_enable(dma_channel_enum channelx); 225 /* disable DMA circulation mode */ 226 void dma_circulation_disable(dma_channel_enum channelx); 227 /* enable memory to memory mode */ 228 void dma_memory_to_memory_enable(dma_channel_enum channelx); 229 /* disable memory to memory mode */ 230 void dma_memory_to_memory_disable(dma_channel_enum channelx); 231 /* enable DMA channel */ 232 void dma_channel_enable(dma_channel_enum channelx); 233 /* disable DMA channel */ 234 void dma_channel_disable(dma_channel_enum channelx); 235 236 /* set DMA peripheral base address */ 237 void dma_periph_address_config(dma_channel_enum channelx, uint32_t address); 238 /* set DMA memory base address */ 239 void dma_memory_address_config(dma_channel_enum channelx, uint32_t address); 240 /* set the number of remaining data to be transferred by the DMA */ 241 void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number); 242 /* get the number of remaining data to be transferred by the DMA */ 243 uint32_t dma_transfer_number_get(dma_channel_enum channelx); 244 /* configure priority level of DMA channel */ 245 void dma_priority_config(dma_channel_enum channelx, uint32_t priority); 246 /* configure transfer data size of memory */ 247 void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth); 248 /* configure transfer data size of peripheral */ 249 void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth); 250 /* enable next address increasement algorithm of memory */ 251 void dma_memory_increase_enable(dma_channel_enum channelx); 252 /* disable next address increasement algorithm of memory */ 253 void dma_memory_increase_disable(dma_channel_enum channelx); 254 /* enable next address increasement algorithm of peripheral */ 255 void dma_periph_increase_enable(dma_channel_enum channelx); 256 /* disable next address increasement algorithm of peripheral */ 257 void dma_periph_increase_disable(dma_channel_enum channelx); 258 /* configure the direction of data transfer on the channel */ 259 void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction); 260 261 /* check DMA flag is set or not */ 262 FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag); 263 /* clear DMA a channel flag */ 264 void dma_flag_clear(dma_channel_enum channelx, uint32_t flag); 265 /* check DMA flag and interrupt enable bit is set or not */ 266 FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag); 267 /* clear DMA a channel flag */ 268 void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag); 269 /* enable DMA interrupt */ 270 void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source); 271 /* disable DMA interrupt */ 272 void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source); 273 274 #endif /* GD32F3X0_DMA_H */ 275
