1 /*! 2 \file gd32f3x0_dbg.h 3 \brief definitions for the DBG 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_DBG_H 38 #define GD32F3X0_DBG_H 39 40 #include "gd32f3x0.h" 41 42 /* DBG definitions */ 43 #define DBG DBG_BASE 44 45 /* registers definitions */ 46 #define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ 47 #define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */ 48 #define DBG_CTL1 REG32(DBG + 0x00000008U) /*!< DBG control register 1 */ 49 50 /* bits definitions */ 51 /* DBG_ID */ 52 #define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ 53 54 /* DBG_CTL0 */ 55 #define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ 56 #define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ 57 #define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ 58 #define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ 59 #define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ 60 #define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ 61 #define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ 62 #define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ 63 #define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ 64 #define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ 65 #ifdef GD32F350 66 #define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ 67 #endif /* GD32F350 */ 68 #define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ 69 70 /* DBG_CTL1 */ 71 #define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ 72 #define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */ 73 #define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */ 74 #define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */ 75 76 /* constants definitions */ 77 #define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ 78 #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ 79 #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ 80 81 /* define the peripheral debug hold bit position and its register index offset */ 82 #define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) 83 #define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) 84 #define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) 85 86 /* register index */ 87 typedef enum 88 { 89 DBG_IDX_CTL0 = 0x04U, /*!< DBG control register 0 offset */ 90 DBG_IDX_CTL1 = 0x08U, /*!< DBG control register 1 offset */ 91 }dbg_reg_idx; 92 93 /* peripherals hold bit */ 94 typedef enum 95 { 96 DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< debug FWDGT kept when core is halted */ 97 DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< debug WWDGT kept when core is halted */ 98 DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< hold TIMER0 counter when core is halted */ 99 DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U), /*!< hold TIMER1 counter when core is halted */ 100 DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< hold TIMER2 counter when core is halted */ 101 #ifdef GD32F350 102 DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< hold TIMER5 counter when core is halted */ 103 #endif /* GD32F350 */ 104 DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< hold TIMER13 counter when core is halted */ 105 DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< hold TIMER14 counter when core is halted */ 106 DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< hold TIMER15 counter when core is halted */ 107 DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< hold TIMER16 counter when core is halted */ 108 DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< hold I2C0 smbus when core is halted */ 109 DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< hold I2C1 smbus when core is halted */ 110 DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ 111 }dbg_periph_enum; 112 113 /* function declarations */ 114 /* deinitialize the DBG */ 115 void dbg_deinit(void); 116 /* read DBG_ID code register */ 117 uint32_t dbg_id_get(void); 118 119 /* enable low power behavior when the MCU is in debug mode */ 120 void dbg_low_power_enable(uint32_t dbg_low_power); 121 /* disable low power behavior when the MCU is in debug mode */ 122 void dbg_low_power_disable(uint32_t dbg_low_power); 123 124 /* enable peripheral behavior when the MCU is in debug mode */ 125 void dbg_periph_enable(dbg_periph_enum dbg_periph); 126 /* disable peripheral behavior when the MCU is in debug mode */ 127 void dbg_periph_disable(dbg_periph_enum dbg_periph); 128 129 #endif /* GD32F3X0_DBG_H */ 130
