1 /*!
2     \file    gd32e50x_fwdgt.c
3     \brief   FWDGT driver
4 
5     \version 2020-03-10, V1.0.0, firmware for GD32E50x
6     \version 2020-08-26, V1.1.0, firmware for GD32E50x
7     \version 2021-03-23, V1.2.0, firmware for GD32E50x
8 */
9 
10 /*
11     Copyright (c) 2021, GigaDevice Semiconductor Inc.
12 
13     Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15 
16     1. Redistributions of source code must retain the above copyright notice, this
17        list of conditions and the following disclaimer.
18     2. Redistributions in binary form must reproduce the above copyright notice,
19        this list of conditions and the following disclaimer in the documentation
20        and/or other materials provided with the distribution.
21     3. Neither the name of the copyright holder nor the names of its contributors
22        may be used to endorse or promote products derived from this software without
23        specific prior written permission.
24 
25     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36 
37 #include "gd32e50x_fwdgt.h"
38 
39 /* write value to FWDGT_CTL_CMD bit field */
40 #define CTL_CMD(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0))
41 /* write value to FWDGT_RLD_RLD bit field */
42 #define RLD_RLD(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0))
43 
44 /*!
45     \brief      enable write access to FWDGT_PSC and FWDGT_RLD
46     \param[in]  none
47     \param[out] none
48     \retval     none
49 */
fwdgt_write_enable(void)50 void fwdgt_write_enable(void)
51 {
52     FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
53 }
54 
55 /*!
56     \brief      disable write access to FWDGT_PSC and FWDGT_RLD
57     \param[in]  none
58     \param[out] none
59     \retval     none
60 */
fwdgt_write_disable(void)61 void fwdgt_write_disable(void)
62 {
63     FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
64 }
65 
66 /*!
67     \brief      start the free watchdog timer counter
68     \param[in]  none
69     \param[out] none
70     \retval     none
71 */
fwdgt_enable(void)72 void fwdgt_enable(void)
73 {
74     FWDGT_CTL = FWDGT_KEY_ENABLE;
75 }
76 
77 /*!
78     \brief      configure the FWDGT counter prescaler value
79     \param[in]  prescaler_value: specify prescaler value
80                 only one parameter can be selected which is shown as below:
81       \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
82       \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
83       \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
84       \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
85       \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
86       \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
87       \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
88     \param[out] none
89     \retval     ErrStatus: ERROR or SUCCESS
90 */
fwdgt_prescaler_value_config(uint16_t prescaler_value)91 ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
92 {
93     uint32_t timeout = FWDGT_PSC_TIMEOUT;
94     uint32_t flag_status = RESET;
95 
96     /* enable write access to FWDGT_PSC */
97     FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
98 
99     /* wait until the PUD flag to be reset */
100     do{
101         flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
102     } while((--timeout > 0U) && (RESET != flag_status));
103 
104     if(RESET != flag_status){
105         return ERROR;
106     }
107 
108     /* configure FWDGT */
109     FWDGT_PSC = (uint32_t)prescaler_value;
110 
111     return SUCCESS;
112 }
113 
114 /*!
115     \brief      configure the FWDGT counter reload value
116     \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
117     \param[out] none
118     \retval     ErrStatus: ERROR or SUCCESS
119 */
fwdgt_reload_value_config(uint16_t reload_value)120 ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
121 {
122     uint32_t timeout = FWDGT_RLD_TIMEOUT;
123     uint32_t flag_status = RESET;
124 
125     /* enable write access to FWDGT_RLD */
126     FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
127 
128     /* wait until the RUD flag to be reset */
129     do{
130         flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
131     }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
132 
133     if ((uint32_t)RESET != flag_status){
134         return ERROR;
135     }
136 
137     FWDGT_RLD = RLD_RLD(reload_value);
138 
139     return SUCCESS;
140 }
141 
142 /*!
143     \brief      configure counter reload value, and prescaler divider value
144     \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
145     \param[in]  prescaler_div: FWDGT prescaler value
146                 only one parameter can be selected which is shown as below:
147       \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
148       \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
149       \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
150       \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
151       \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
152       \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
153       \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
154     \param[out] none
155     \retval     ErrStatus: ERROR or SUCCESS
156 */
fwdgt_config(uint16_t reload_value,uint8_t prescaler_div)157 ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
158 {
159     uint32_t timeout = FWDGT_PSC_TIMEOUT;
160     uint32_t flag_status = RESET;
161 
162     /* enable write access to FWDGT_PSC,and FWDGT_RLD */
163     FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
164 
165     /* wait until the PUD flag to be reset */
166     do{
167        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
168     }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
169 
170     if ((uint32_t)RESET != flag_status){
171         return ERROR;
172     }
173 
174     /* configure FWDGT */
175     FWDGT_PSC = (uint32_t)prescaler_div;
176 
177     timeout = FWDGT_RLD_TIMEOUT;
178     /* wait until the RUD flag to be reset */
179     do{
180        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
181     }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
182 
183     if ((uint32_t)RESET != flag_status){
184         return ERROR;
185     }
186 
187     FWDGT_RLD = RLD_RLD(reload_value);
188 
189     /* reload the counter */
190     FWDGT_CTL = FWDGT_KEY_RELOAD;
191 
192     return SUCCESS;
193 }
194 
195 /*!
196     \brief      reload the counter of FWDGT
197     \param[in]  none
198     \param[out] none
199     \retval     none
200 */
fwdgt_counter_reload(void)201 void fwdgt_counter_reload(void)
202 {
203     FWDGT_CTL = FWDGT_KEY_RELOAD;
204 }
205 
206 /*!
207     \brief      get flag state of FWDGT
208     \param[in]  flag: flag to get
209                 only one parameter can be selected which is shown as below:
210       \arg        FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
211       \arg        FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
212     \param[out] none
213     \retval     FlagStatus: SET or RESET
214 */
fwdgt_flag_get(uint16_t flag)215 FlagStatus fwdgt_flag_get(uint16_t flag)
216 {
217     if(RESET != (FWDGT_STAT & flag)){
218         return SET;
219     }
220 
221     return RESET;
222 }
223