1 /*! 2 \file gd32e50x_fwdgt.h 3 \brief definitions for the FWDGT 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_FWDGT_H 38 #define GD32E50X_FWDGT_H 39 40 #include "gd32e50x.h" 41 42 /* FWDGT definitions */ 43 #define FWDGT FWDGT_BASE 44 45 /* registers definitions */ 46 #define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ 47 #define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ 48 #define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ 49 #define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ 50 51 /* bits definitions */ 52 /* FWDGT_CTL */ 53 #define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ 54 55 /* FWDGT_PSC */ 56 #define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ 57 58 /* FWDGT_RLD */ 59 #define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ 60 61 /* FWDGT_STAT */ 62 #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ 63 #define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ 64 65 /* constants definitions */ 66 /* psc register value */ 67 #define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) 68 #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ 69 #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ 70 #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ 71 #define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ 72 #define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ 73 #define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ 74 #define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ 75 76 /* control value */ 77 #define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ 78 #define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ 79 #define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ 80 #define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ 81 82 /* FWDGT timeout value */ 83 #define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ 84 #define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ 85 86 /* FWDGT flag definitions */ 87 #define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ 88 #define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ 89 90 /* function declarations */ 91 /* enable write access to FWDGT_PSC and FWDGT_RLD */ 92 void fwdgt_write_enable(void); 93 /* disable write access to FWDGT_PSC and FWDGT_RLD */ 94 void fwdgt_write_disable(void); 95 /* start the free watchdog timer counter */ 96 void fwdgt_enable(void); 97 98 /* configure the FWDGT counter prescaler value */ 99 ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); 100 /* configure the FWDGT counter reload value */ 101 ErrStatus fwdgt_reload_value_config(uint16_t reload_value); 102 /* configure counter reload value, and prescaler divider value */ 103 ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); 104 /* reload the counter of FWDGT */ 105 void fwdgt_counter_reload(void); 106 107 /* get flag state of FWDGT */ 108 FlagStatus fwdgt_flag_get(uint16_t flag); 109 110 #endif /* GD32E50X_FWDGT_H */ 111
