1 /*!
2 \file gd32a50x_rcu.c
3 \brief RCU driver
4
5 \version 2022-01-30, V1.0.0, firmware for GD32A50x
6 */
7
8 /*
9 Copyright (c) 2022, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32a50x_rcu.h"
36
37 /* define startup timeout count */
38 #define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU)
39 #define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU)
40
41 /* RCU IRC8M adjust value mask and offset*/
42 #define RCU_IRC8M_ADJUST_MASK ((uint8_t)0x1FU)
43 #define RCU_IRC8M_ADJUST_OFFSET ((uint32_t)3U)
44
45 /*!
46 \brief deinitialize the RCU
47 \param[in] none
48 \param[out] none
49 \retval none
50 */
rcu_deinit(void)51 void rcu_deinit(void)
52 {
53 /* enable IRC8M */
54 RCU_CTL |= RCU_CTL_IRC8MEN;
55 if(ERROR == rcu_osci_stab_wait(RCU_IRC8M)) {
56 while(1) {
57 }
58 }
59
60 RCU_CFG0 &= ~RCU_CFG0_SCS;
61 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_IRC8M) {
62 }
63 /* reset CTL register */
64 RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN | RCU_CTL_HXTALSCAL | RCU_CTL_LCKMEN | RCU_CTL_PLLMEN);
65 RCU_CTL &= ~RCU_CTL_HXTALBPS;
66 /* reset CFG0 register */
67 RCU_CFG0 = 0x00020000U;
68 /* reset INT and CFG1 and CFG2 register */
69 RCU_INT = 0x00FF0000U;
70 RCU_CFG1 = 0x00000000U;
71 RCU_CFG2 = 0x00000000U;
72 }
73
74 /*!
75 \brief enable the peripherals clock
76 \param[in] periph: RCU peripherals, refer to rcu_periph_enum
77 only one parameter can be selected which is shown as below:
78 \arg RCU_DMAx (x=0,1): DMA clock
79 \arg RCU_DMAMUX: DMAMUX clock
80 \arg RCU_CRC: CRC clock
81 \arg RCU_GPIOx (x=A,B,C,D,E,F): GPIO ports clock
82 \arg RCU_SYSCFG: SYSCFG clock
83 \arg RCU_CMP: CMP clock
84 \arg RCU_ADCx (x=0,1): ADCx clock
85 \arg RCU_TIMERx (x=0,1,5,6,7,19,20): TIMER clock
86 \arg RCU_SPIx (x=0,1): SPIx clock
87 \arg RCU_USARTx (x=0,1,2): USARTx clock
88 \arg RCU_MFCOM: MFCOM clock
89 \arg RCU_TRIGSEL: TRIGSEL clock
90 \arg RCU_CANx (x=0,1): CANx clock
91 \arg RCU_I2Cx (x=0,1): I2Cx clock
92 \arg RCU_WWDGT: WWDGT clock
93 \arg RCU_BKP: BKP clock
94 \arg RCU_PMU: PMU clock
95 \arg RCU_DAC: DAC clock
96 \arg RCU_RTC: RTC clock
97 \param[out] none
98 \retval none
99 */
rcu_periph_clock_enable(rcu_periph_enum periph)100 void rcu_periph_clock_enable(rcu_periph_enum periph)
101 {
102 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
103 }
104
105 /*!
106 \brief disable the peripherals clock
107 \param[in] periph: RCU peripherals, refer to rcu_periph_enum
108 only one parameter can be selected which is shown as below:
109 \arg RCU_DMAx (x=0,1): DMA clock
110 \arg RCU_DMAMUX: DMAMUX clock
111 \arg RCU_CRC: CRC clock
112 \arg RCU_GPIOx (x=A,B,C,D,E,F): GPIO ports clock
113 \arg RCU_SYSCFG: SYSCFG clock
114 \arg RCU_CMP: CMP clock
115 \arg RCU_ADCx (x=0,1): ADCx clock
116 \arg RCU_TIMERx (x=0,1,5,6,7,19,20): TIMER clock
117 \arg RCU_SPIx (x=0,1): SPIx clock
118 \arg RCU_USARTx (x=0,1,2): USARTx clock
119 \arg RCU_MFCOM: MFCOM clock
120 \arg RCU_TRIGSEL: TRIGSEL clock
121 \arg RCU_CANx (x=0,1): CANx clock
122 \arg RCU_I2Cx (x=0,1): I2Cx clock
123 \arg RCU_WWDGT: WWDGT clock
124 \arg RCU_BKP: BKP clock
125 \arg RCU_PMU: PMU clock
126 \arg RCU_DAC: DAC clock
127 \arg RCU_RTC: RTC clock
128 \param[out] none
129 \retval none
130 */
rcu_periph_clock_disable(rcu_periph_enum periph)131 void rcu_periph_clock_disable(rcu_periph_enum periph)
132 {
133 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
134 }
135
136 /*!
137 \brief reset the peripherals
138 \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
139 only one parameter can be selected which is shown as below:
140 \arg RCU_DMAxRST (x=0,1): DMA reset enable
141 \arg RCU_DMAMUXRST: DMAMUX reset enable
142 \arg RCU_MFCOMRST: MFCOM reset enable
143 \arg RCU_CRCRST: CRC reset enable
144 \arg RCU_GPIOxRST (x=A,B,C,D,E,F): GPIO ports reset enable
145 \arg RCU_SYSCFGRST: SYSCFG reset enable
146 \arg RCU_CMPRST: CMP reset enable
147 \arg RCU_ADCxRST (x=0,1): ADCx reset enable
148 \arg RCU_TIMERxRST (x=0,1,5,6,7,19,20): TIMER reset enable
149 \arg RCU_SPIxRST (x=0,1): SPIx reset enable
150 \arg RCU_USARTxRST (x=0,1,2): USARTx reset enable
151 \arg RCU_CANxRST (x=0,1): CANx reset enable
152 \arg RCU_I2CxRST(x=0,1): I2Cx reset enable
153 \arg RCU_WWDGTRST: WWDGT reset enable
154 \arg RCU_PMURST: PMU reset enable
155 \arg RCU_DACRST: DAC reset enable
156 \param[out] none
157 \retval none
158 */
rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)159 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
160 {
161 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
162 }
163
164 /*!
165 \brief disable reset the peripheral
166 \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
167 only one parameter can be selected which is shown as below:
168 \arg RCU_DMAxRST (x=0,1): DMA reset enable
169 \arg RCU_DMAMUXRST: DMAMUX reset enable
170 \arg RCU_MFCOMRST: MFCOM reset enable
171 \arg RCU_CRCRST: CRC reset enable
172 \arg RCU_GPIOxRST (x=A,B,C,D,E,F): GPIO ports reset enable
173 \arg RCU_SYSCFGRST: SYSCFG reset enable
174 \arg RCU_CMPRST: CMP reset enable
175 \arg RCU_ADCxRST (x=0,1): ADCx reset enable
176 \arg RCU_TIMERxRST (x=0,1,5,6,7,19,20): TIMER reset enable
177 \arg RCU_SPIxRST (x=0,1): SPIx reset enable
178 \arg RCU_USARTxRST (x=0,1,2): USARTx reset enable
179 \arg RCU_CANxRST (x=0,1): CANx reset enable
180 \arg RCU_I2CxRST(x=0,1): I2Cx reset enable
181 \arg RCU_WWDGTRST: WWDGT reset enable
182 \arg RCU_PMURST: PMU reset enable
183 \arg RCU_DACRST: DAC reset enable
184 \param[out] none
185 \retval none
186 */
rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)187 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
188 {
189 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
190 }
191
192 /*!
193 \brief enable the peripherals clock when in sleep mode
194 \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
195 only one parameter can be selected which is shown as below:
196 \arg RCU_FMC_SLP: FMC clock
197 \arg RCU_SRAM_SLP: SRAM clock
198 \param[out] none
199 \retval none
200 */
rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)201 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
202 {
203 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
204 }
205
206 /*!
207 \brief disable the peripherals clock when in sleep mode
208 \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
209 only one parameter can be selected which is shown as below:
210 \arg RCU_FMC_SLP: FMC clock
211 \arg RCU_SRAM_SLP: SRAM clock
212 \param[out] none
213 \retval none
214 */
rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)215 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
216 {
217 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
218 }
219
220 /*!
221 \brief reset the BKP domain control register
222 \param[in] none
223 \param[out] none
224 \retval none
225 */
rcu_bkp_reset_enable(void)226 void rcu_bkp_reset_enable(void)
227 {
228 RCU_BDCTL |= RCU_BDCTL_BKPRST;
229 }
230
231 /*!
232 \brief disable the BKP domain control register reset
233 \param[in] none
234 \param[out] none
235 \retval none
236 */
rcu_bkp_reset_disable(void)237 void rcu_bkp_reset_disable(void)
238 {
239 RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
240 }
241
242 /*!
243 \brief configure the system clock source
244 \param[in] ck_sys: system clock source select
245 only one parameter can be selected which is shown as below:
246 \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
247 \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
248 \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
249 \param[out] none
250 \retval none
251 */
rcu_system_clock_source_config(uint32_t ck_sys)252 void rcu_system_clock_source_config(uint32_t ck_sys)
253 {
254 uint32_t reg;
255 reg = RCU_CFG0;
256 /* reset the SCS bits and set according to ck_sys */
257 reg &= ~RCU_CFG0_SCS;
258 RCU_CFG0 = (reg | ck_sys);
259 }
260
261 /*!
262 \brief get the system clock source
263 \param[in] none
264 \param[out] none
265 \retval which clock is selected as CK_SYS source
266 \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source
267 \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source
268 \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source
269 */
rcu_system_clock_source_get(void)270 uint32_t rcu_system_clock_source_get(void)
271 {
272 return (RCU_CFG0 & RCU_CFG0_SCSS);
273 }
274
275 /*!
276 \brief configure the AHB clock prescaler selection
277 \param[in] ck_ahb: AHB clock prescaler selection
278 only one parameter can be selected which is shown as below:
279 \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
280 \param[out] none
281 \retval none
282 */
rcu_ahb_clock_config(uint32_t ck_ahb)283 void rcu_ahb_clock_config(uint32_t ck_ahb)
284 {
285 uint32_t reg;
286 reg = RCU_CFG0;
287 /* reset the AHBPSC bits and set according to ck_ahb */
288 reg &= ~RCU_CFG0_AHBPSC;
289 RCU_CFG0 = (reg | ck_ahb);
290 }
291
292 /*!
293 \brief configure the APB1 clock prescaler selection
294 \param[in] ck_apb1: APB1 clock prescaler selection
295 only one parameter can be selected which is shown as below:
296 \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
297 \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
298 \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
299 \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
300 \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
301 \param[out] none
302 \retval none
303 */
rcu_apb1_clock_config(uint32_t ck_apb1)304 void rcu_apb1_clock_config(uint32_t ck_apb1)
305 {
306 uint32_t reg;
307 reg = RCU_CFG0;
308 /* reset the APB1PSC and set according to ck_apb1 */
309 reg &= ~RCU_CFG0_APB1PSC;
310 RCU_CFG0 = (reg | ck_apb1);
311 }
312
313 /*!
314 \brief configure the APB2 clock prescaler selection
315 \param[in] ck_apb2: APB2 clock prescaler selection
316 only one parameter can be selected which is shown as below:
317 \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
318 \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
319 \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
320 \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
321 \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
322 \param[out] none
323 \retval none
324 */
rcu_apb2_clock_config(uint32_t ck_apb2)325 void rcu_apb2_clock_config(uint32_t ck_apb2)
326 {
327 uint32_t reg;
328 reg = RCU_CFG0;
329 /* reset the APB2PSC and set according to ck_apb2 */
330 reg &= ~RCU_CFG0_APB2PSC;
331 RCU_CFG0 = (reg | ck_apb2);
332 }
333
334 /*!
335 \brief configure the CK_OUT clock source
336 \param[in] ckout0_src: CK_OUT clock source selection
337 only one parameter can be selected which is shown as below:
338 \arg RCU_CKOUTSRC_NONE: no clock selected
339 \arg RCU_CKOUTSRC_IRC40K��IRC40K selected
340 \arg RCU_CKOUTSRC_LXTAL�� LXTAL selected
341 \arg RCU_CKOUTSRC_CKSYS: system clock selected
342 \arg RCU_CKOUTSRC_IRC8M: high speed 8M internal oscillator clock selected
343 \arg RCU_CKOUTSRC_HXTAL: HXTAL selected
344 \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected
345 \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected
346 \param[in] ckout_div: CK_OUT divider
347 \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x
348 \param[out] none
349 \retval none
350 */
rcu_ckout_config(uint32_t ckout_src,uint32_t ckout_div)351 void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div)
352 {
353 uint32_t ckout = 0U;
354 ckout = RCU_CFG0;
355 /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */
356 ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
357 RCU_CFG0 = (ckout | ckout_src | ckout_div);
358 }
359
360 /*!
361 \brief configure the PLL clock source selection and PLL multiply factor
362 \param[in] pll_src: PLL clock source selection
363 only one parameter can be selected which is shown as below:
364 \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock
365 \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock
366 \param[in] pll_mul: PLL multiply factor
367 only one parameter can be selected which is shown as below:
368 \arg RCU_PLL_MULx(x=2..32): PLL source clock * x
369 \param[out] none
370 \retval none
371 */
rcu_pll_config(uint32_t pll_src,uint32_t pll_mul)372 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
373 {
374 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
375 RCU_CFG0 |= (pll_src | pll_mul);
376 }
377
378 /*!
379 \brief enable double PLL clock
380 \param[in] none
381 \param[out] none
382 \retval none
383 */
rcu_double_pll_enable(void)384 void rcu_double_pll_enable(void)
385 {
386 RCU_CFG0 &= ~RCU_CFG0_DPLL;
387 }
388
389 /*!
390 \brief disable double PLL clock
391 \param[in] none
392 \param[out] none
393 \retval none
394 */
rcu_double_pll_disable(void)395 void rcu_double_pll_disable(void)
396 {
397 RCU_CFG0 |= RCU_CFG0_DPLL;
398 }
399
400 /*!
401 \brief enable RCU system reset
402 \param[in] reset_source: reset source
403 one or more parameters can be selected which is shown as below:
404 \arg RCU_SYSRST_LOCKUP: CPU lock-up reset
405 \arg RCU_SYSRST_LVD: low voltage detection reset
406 \arg RCU_SYSRST_ECC: ECC 2 bits error reset
407 \arg RCU_SYSRST_LOH: lost of HXTAL reset
408 \arg RCU_SYSRST_LOP: lost of PLL reset
409 \param[out] none
410 \retval none
411 */
rcu_system_reset_enable(uint32_t reset_source)412 void rcu_system_reset_enable(uint32_t reset_source)
413 {
414 RCU_RSTSCK |= reset_source;
415 }
416
417 /*!
418 \brief disable RCU system reset
419 \param[in] reset_source: reset source
420 one or more parameters can be selected which is shown as below:
421 \arg RCU_SYSRST_LOCKUP: CPU lock-up reset
422 \arg RCU_SYSRST_LVD: low voltage detection reset
423 \arg RCU_SYSRST_ECC: ECC 2 bits error reset
424 \arg RCU_SYSRST_LOH: lost of HXTAL reset
425 \arg RCU_SYSRST_LOP: lost of PLL reset
426 \param[out] none
427 \retval none
428 */
rcu_system_reset_disable(uint32_t reset_source)429 void rcu_system_reset_disable(uint32_t reset_source)
430 {
431 RCU_RSTSCK &= ~reset_source;
432 }
433
434 /*!
435 \brief configure the ADC prescaler factor
436 \param[in] adc_psc: ADC prescaler factor
437 only one parameter can be selected which is shown as below:
438 \arg RCU_CKADC_CKAHB_DIVx (x=2,3,...,32): ADC prescaler select CK_AHB/(x)
439 \param[out] none
440 \retval none
441 */
rcu_adc_clock_config(uint32_t adc_psc)442 void rcu_adc_clock_config(uint32_t adc_psc)
443 {
444 uint32_t reg;
445 /* reset the ADCPSC bits */
446 reg = RCU_CFG2;
447 reg &= ~RCU_CFG2_ADCPSC;
448 /* set the ADC prescaler factor */
449 reg |= adc_psc & RCU_CFG2_ADCPSC;
450 /* set the register */
451 RCU_CFG2 = reg;
452 }
453
454 /*!
455 \brief configure the RTC clock source selection
456 \param[in] rtc_clock_source: RTC clock source selection
457 only one parameter can be selected which is shown as below:
458 \arg RCU_RTCSRC_NONE: no clock selected
459 \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
460 \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
461 \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock
462 \param[out] none
463 \retval none
464 */
rcu_rtc_clock_config(uint32_t rtc_clock_source)465 void rcu_rtc_clock_config(uint32_t rtc_clock_source)
466 {
467 uint32_t reg;
468 reg = RCU_BDCTL;
469 /* reset the RTCSRC bits and set according to rtc_clock_source */
470 reg &= ~RCU_BDCTL_RTCSRC;
471 RCU_BDCTL = (reg | rtc_clock_source);
472 }
473
474 /*!
475 \brief configure the USART clock source selection
476 \param[in] usart_periph: USARTx(x=0,1,2)
477 \param[in] usart_clock_source: USART clock source selection
478 only one parameter can be selected which is shown as below:
479 \arg RCU_USARTSRC_HXTAL: HXTAL clock selected as USART source clock
480 \arg RCU_USARTSRC_CKSYS: system clock selected as USART source clock
481 \arg RCU_USARTSRC_LXTAL: LXTAL clock selected as USART source clock
482 \arg RCU_USARTSRC_IRC8M: IRC8M clock selected as USART source clock
483 \param[out] none
484 \retval none
485 */
rcu_usart_clock_config(uint32_t usart_periph,uint32_t usart_clock_source)486 void rcu_usart_clock_config(uint32_t usart_periph, uint32_t usart_clock_source)
487 {
488 uint32_t reg;
489 reg = RCU_CFG2;
490 switch(usart_periph) {
491 case USART0:
492 /* reset the USART0SEL bit and set according to usart_clock_source */
493 reg &= ~RCU_CFG2_USART0SEL;
494 RCU_CFG2 = (reg | usart_clock_source);
495 break;
496 case USART1:
497 /* reset the USART1SEL bit and set according to usart_clock_source */
498 reg &= ~RCU_CFG2_USART1SEL;
499 RCU_CFG2 = (reg | (uint32_t)(usart_clock_source << 4U));
500 break;
501 case USART2:
502 /* reset the USART2SEL bit and set according to usart_clock_source */
503 reg &= ~RCU_CFG2_USART2SEL;
504 RCU_CFG2 = (reg | (uint32_t)(usart_clock_source << 6U));
505 break;
506 default:
507 break;
508 }
509 }
510
511 /*!
512 \brief configure the CAN clock source selection
513 \param[in] can_periph: CANx(x=0,1)
514 \param[in] can_clock_source: CAN clock source selection
515 only one parameter can be selected which is shown as below:
516 \arg RCU_CANSRC_HXTAL: HXTAL clock selected as CAN source clock
517 \arg RCU_CANSRC_PCLK2: PCLK2 clock selected as CAN source clock
518 \arg RCU_CANSRC_PCLK2_DIV_2: PCLK2/2 clock selected as CAN source clock
519 \arg RCU_CANSRC_IRC8M: IRC8M clock selected as CAN source clock
520 \param[out] none
521 \retval none
522 */
rcu_can_clock_config(uint32_t can_periph,uint32_t can_clock_source)523 void rcu_can_clock_config(uint32_t can_periph, uint32_t can_clock_source)
524 {
525 uint32_t reg;
526 reg = RCU_CFG2;
527 switch(can_periph) {
528 case CAN0:
529 /* reset the CAN0SEL bits and set according to can_clock_source */
530 reg &= ~RCU_CFG2_CAN0SEL;
531 RCU_CFG2 = (reg | can_clock_source);
532 break;
533 case CAN1:
534 /* reset the CAN1SEL bits and set according to can_clock_source */
535 reg &= ~RCU_CFG2_CAN1SEL;
536 RCU_CFG2 = (reg | (uint32_t)(can_clock_source << 2U));
537 break;
538 default:
539 break;
540 }
541 }
542
543 /*!
544 \brief configure the LXTAL drive capability
545 \param[in] lxtal_dricap: drive capability of LXTAL
546 only one parameter can be selected which is shown as below:
547 \arg RCU_LXTAL_LOWDRI: lower driving capability
548 \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability
549 \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability
550 \arg RCU_LXTAL_HIGHDRI: higher driving capability
551 \param[out] none
552 \retval none
553 */
rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)554 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
555 {
556 uint32_t reg;
557 reg = RCU_BDCTL;
558 /* reset the LXTALDRI bits and set according to lxtal_dricap */
559 reg &= ~RCU_BDCTL_LXTALDRI;
560 RCU_BDCTL = (reg | lxtal_dricap);
561 }
562
563 /*!
564 \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout
565 \param[in] osci: oscillator types, refer to rcu_osci_type_enum
566 only one parameter can be selected which is shown as below:
567 \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
568 \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
569 \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
570 \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
571 \arg RCU_PLL_CK: phase locked loop(PLL)
572 \param[out] none
573 \retval ErrStatus: SUCCESS or ERROR
574 */
rcu_osci_stab_wait(rcu_osci_type_enum osci)575 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
576 {
577 uint32_t stb_cnt = 0U;
578 ErrStatus reval = ERROR;
579 FlagStatus osci_stat = RESET;
580
581 switch(osci) {
582 /* wait HXTAL stable */
583 case RCU_HXTAL:
584 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) {
585 osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
586 stb_cnt++;
587 }
588 /* check whether flag is set or not */
589 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) {
590 reval = SUCCESS;
591 }
592 break;
593 /* wait LXTAL stable */
594 case RCU_LXTAL:
595 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) {
596 osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
597 stb_cnt++;
598 }
599 /* check whether flag is set or not */
600 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) {
601 reval = SUCCESS;
602 }
603 break;
604 /* wait IRC8M stable */
605 case RCU_IRC8M:
606 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) {
607 osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
608 stb_cnt++;
609 }
610 /* check whether flag is set or not */
611 if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) {
612 reval = SUCCESS;
613 }
614 break;
615 /* wait IRC40K stable */
616 case RCU_IRC40K:
617 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
618 osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
619 stb_cnt++;
620 }
621 /* check whether flag is set or not */
622 if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) {
623 reval = SUCCESS;
624 }
625 break;
626 /* wait PLL stable */
627 case RCU_PLL_CK:
628 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
629 osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
630 stb_cnt++;
631 }
632 /* check whether flag is set or not */
633 if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) {
634 reval = SUCCESS;
635 }
636 break;
637 default:
638 break;
639 }
640 /* return value */
641 return reval;
642 }
643
644 /*!
645 \brief turn on the oscillator
646 \param[in] osci: oscillator types, refer to rcu_osci_type_enum
647 only one parameter can be selected which is shown as below:
648 \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
649 \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
650 \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
651 \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
652 \arg RCU_PLL_CK: phase locked loop(PLL)
653 \param[out] none
654 \retval none
655 */
rcu_osci_on(rcu_osci_type_enum osci)656 void rcu_osci_on(rcu_osci_type_enum osci)
657 {
658 RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
659 }
660
661 /*!
662 \brief turn off the oscillator
663 \param[in] osci: oscillator types, refer to rcu_osci_type_enum
664 only one parameter can be selected which is shown as below:
665 \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
666 \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
667 \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
668 \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
669 \arg RCU_PLL_CK: phase locked loop(PLL)
670 \param[out] none
671 \retval none
672 */
rcu_osci_off(rcu_osci_type_enum osci)673 void rcu_osci_off(rcu_osci_type_enum osci)
674 {
675 RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
676 }
677
678 /*!
679 \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
680 \param[in] osci: oscillator types, refer to rcu_osci_type_enum
681 only one parameter can be selected which is shown as below:
682 \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
683 \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
684 \param[out] none
685 \retval none
686 */
rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)687 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
688 {
689 uint32_t reg;
690
691 switch(osci) {
692 /* enable HXTAL to bypass mode */
693 case RCU_HXTAL:
694 reg = RCU_CTL;
695 RCU_CTL &= ~RCU_CTL_HXTALEN;
696 RCU_CTL = (reg | RCU_CTL_HXTALBPS);
697 break;
698 /* enable LXTAL to bypass mode */
699 case RCU_LXTAL:
700 reg = RCU_BDCTL;
701 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
702 RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
703 break;
704 default:
705 break;
706 }
707 }
708
709 /*!
710 \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
711 \param[in] osci: oscillator types, refer to rcu_osci_type_enum
712 only one parameter can be selected which is shown as below:
713 \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
714 \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
715 \param[out] none
716 \retval none
717 */
rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)718 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
719 {
720 uint32_t reg;
721
722 switch(osci) {
723 /* disable HXTAL to bypass mode */
724 case RCU_HXTAL:
725 reg = RCU_CTL;
726 RCU_CTL &= ~RCU_CTL_HXTALEN;
727 RCU_CTL = (reg & ~RCU_CTL_HXTALBPS);
728 break;
729 /* disable LXTAL to bypass mode */
730 case RCU_LXTAL:
731 reg = RCU_BDCTL;
732 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
733 RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS);
734 break;
735 default:
736 break;
737 }
738 }
739
740 /*!
741 \brief HXTAL frequency scale select
742 \param[in] hxtal_scal: HXTAL frequency scale
743 only one parameter can be selected which is shown as below:
744 \arg HXTAL_SCALE_2M_TO_8M: HXTAL scale is 2-8MHz
745 \arg HXTAL_SCALE_8M_TO_40M: HXTAL scale is 8-40MHz
746 \param[out] none
747 \retval none
748 */
rcu_hxtal_frequency_scale_select(uint32_t hxtal_scal)749 void rcu_hxtal_frequency_scale_select(uint32_t hxtal_scal)
750 {
751 if(HXTAL_SCALE_2M_TO_8M == hxtal_scal) {
752 RCU_CTL &= ~RCU_CTL_HXTALSCAL;
753 } else {
754 RCU_CTL |= RCU_CTL_HXTALSCAL;
755 }
756 }
757
758 /*!
759 \brief configure the HXTAL divider used as input of PLL
760 \param[in] hxtal_prediv: HXTAL previous PLL
761 only one parameter can be selected which is shown as below:
762 \arg RCU_PREDV_DIVx(x=1..16): HXTAL divided x used as input of PLL
763 \param[out] none
764 \retval none
765 */
rcu_hxtal_prediv_config(uint32_t hxtal_prediv)766 void rcu_hxtal_prediv_config(uint32_t hxtal_prediv)
767 {
768 uint32_t prediv = 0U;
769 prediv = RCU_CFG1;
770 /* reset the PREDV bits and set according to hxtal_prediv */
771 prediv &= ~RCU_CFG1_PREDV;
772 RCU_CFG1 = (prediv | hxtal_prediv);
773 }
774
775 /*!
776 \brief set the IRC8M adjust value
777 \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F
778 \arg 0x00 - 0x1F
779 \param[out] none
780 \retval none
781 */
rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)782 void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
783 {
784 uint32_t reg;
785 reg = RCU_CTL;
786 /* reset the IRC8MADJ bits and set according to irc8m_adjval */
787 reg &= ~RCU_CTL_IRC8MADJ;
788 RCU_CTL = (reg | ((irc8m_adjval & RCU_IRC8M_ADJUST_MASK) << RCU_IRC8M_ADJUST_OFFSET));
789 }
790
791 /*!
792 \brief enable the HXTAL clock monitor
793 \param[in] none
794 \param[out] none
795 \retval none
796 */
rcu_hxtal_clock_monitor_enable(void)797 void rcu_hxtal_clock_monitor_enable(void)
798 {
799 RCU_CTL |= RCU_CTL_CKMEN;
800 }
801
802 /*!
803 \brief disable the HXTAL clock monitor
804 \param[in] none
805 \param[out] none
806 \retval none
807 */
rcu_hxtal_clock_monitor_disable(void)808 void rcu_hxtal_clock_monitor_disable(void)
809 {
810 RCU_CTL &= ~RCU_CTL_CKMEN;
811 }
812
813 /*!
814 \brief enable the LXTAL clock monitor
815 \param[in] none
816 \param[out] none
817 \retval none
818 */
rcu_lxtal_clock_monitor_enable(void)819 void rcu_lxtal_clock_monitor_enable(void)
820 {
821 RCU_CTL |= RCU_CTL_LCKMEN;
822 }
823
824 /*!
825 \brief disable the LXTAL clock monitor
826 \param[in] none
827 \param[out] none
828 \retval none
829 */
rcu_lxtal_clock_monitor_disable(void)830 void rcu_lxtal_clock_monitor_disable(void)
831 {
832 RCU_CTL &= ~RCU_CTL_LCKMEN;
833 }
834
835 /*!
836 \brief enable the PLL clock monitor
837 \param[in] none
838 \param[out] none
839 \retval none
840 */
rcu_pll_clock_monitor_enable(void)841 void rcu_pll_clock_monitor_enable(void)
842 {
843 RCU_CTL |= RCU_CTL_PLLMEN;
844 }
845
846 /*!
847 \brief disable the PLL clock monitor
848 \param[in] none
849 \param[out] none
850 \retval none
851 */
rcu_pll_clock_monitor_disable(void)852 void rcu_pll_clock_monitor_disable(void)
853 {
854 RCU_CTL &= ~RCU_CTL_PLLMEN;
855 }
856
857 /*!
858 \brief unlock the voltage key
859 \param[in] none
860 \param[out] none
861 \retval none
862 */
rcu_voltage_key_unlock(void)863 void rcu_voltage_key_unlock(void)
864 {
865 /* reset the KEY bits and set 0x1A2B3C4D */
866 RCU_VKEY = ~RCU_VKEY_KEY;
867 RCU_VKEY = RCU_VKEY_UNLOCK;
868 }
869
870 /*!
871 \brief deep-sleep mode voltage select
872 \param[in] dsvol: deep sleep mode voltage
873 only one parameter can be selected which is shown as below:
874 \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V
875 \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
876 \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
877 \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V
878 \param[out] none
879 \retval none
880 */
rcu_deepsleep_voltage_set(uint32_t dsvol)881 void rcu_deepsleep_voltage_set(uint32_t dsvol)
882 {
883 /* reset the DSLPVS bits and set according to dsvol */
884 RCU_DSV &= ~RCU_DSV_DSLPVS;
885 RCU_DSV |= dsvol;
886 }
887
888 /*!
889 \brief get the system clock, bus and peripheral clock frequency
890 \param[in] clock: the clock frequency which to get
891 only one parameter can be selected which is shown as below:
892 \arg CK_SYS: system clock frequency
893 \arg CK_AHB: AHB clock frequency
894 \arg CK_APB1: APB1 clock frequency
895 \arg CK_APB2: APB2 clock frequency
896 \arg CK_USART0: USART0 clock frequency
897 \arg CK_USART1: USART1 clock frequency
898 \arg CK_USART2: USART2 clock frequency
899 \param[out] none
900 \retval clock frequency of system, AHB, APB1, APB2, USART
901 */
rcu_clock_freq_get(rcu_clock_freq_enum clock)902 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
903 {
904 uint32_t sws, ck_freq = 0U;
905 uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
906 uint32_t usart_freq = 0U;
907 uint32_t pllsel, pllmf, ck_src, idx, clk_exp;
908 uint32_t predv0;
909
910 /* exponent of AHB, APB1 and APB2 clock divider */
911 uint8_t ahb_exp[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
912 uint8_t apb1_exp[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
913 uint8_t apb2_exp[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
914
915 sws = RCU_CFG0 & RCU_CFG0_SCSS;
916 switch(sws) {
917 /* IRC8M is selected as CK_SYS */
918 case RCU_SCSS_IRC8M:
919 cksys_freq = IRC8M_VALUE;
920 break;
921 /* HXTAL is selected as CK_SYS */
922 case RCU_SCSS_HXTAL:
923 cksys_freq = HXTAL_VALUE;
924 break;
925 /* PLL is selected as CK_SYS */
926 case RCU_SCSS_PLL:
927 /* PLL clock source selection, HXTAL or IRC8M/2 */
928 pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
929 if(RCU_PLLSRC_HXTAL == pllsel) {
930 /* PLL clock source is HXTAL */
931 ck_src = HXTAL_VALUE;
932 predv0 = (RCU_CFG1 & RCU_CFG1_PREDV) + 1U;
933 ck_src /= predv0;
934 } else {
935 /* PLL clock source is IRC8M/2 */
936 ck_src = IRC8M_VALUE / 2U;
937 }
938 /* PLL multiplication factor */
939 pllmf = GET_BITS(RCU_CFG0, 18, 21);
940 pllmf += ((RCU_CFG0 & RCU_CFG0_PLLMF_4) ? 15U : 0U);
941 pllmf += ((RCU_CFG0_PLLMF == (RCU_CFG0 & RCU_CFG0_PLLMF)) ? 1U : 2U);
942 cksys_freq = ck_src * pllmf;
943 break;
944 /* IRC8M is selected as CK_SYS */
945 default:
946 cksys_freq = IRC8M_VALUE;
947 break;
948 }
949 /* calculate AHB clock frequency */
950 idx = GET_BITS(RCU_CFG0, 4, 7);
951 clk_exp = ahb_exp[idx];
952 ahb_freq = cksys_freq >> clk_exp;
953 /* calculate APB1 clock frequency */
954 idx = GET_BITS(RCU_CFG0, 8, 10);
955 clk_exp = apb1_exp[idx];
956 apb1_freq = ahb_freq >> clk_exp;
957 /* calculate APB2 clock frequency */
958 idx = GET_BITS(RCU_CFG0, 11, 13);
959 clk_exp = apb2_exp[idx];
960 apb2_freq = ahb_freq >> clk_exp;
961 /* return the clocks frequency */
962 switch(clock) {
963 case CK_SYS:
964 ck_freq = cksys_freq;
965 break;
966 case CK_AHB:
967 ck_freq = ahb_freq;
968 break;
969 case CK_APB1:
970 ck_freq = apb1_freq;
971 break;
972 case CK_APB2:
973 ck_freq = apb2_freq;
974 break;
975 case CK_USART0:
976 /* calculate USART0 clock frequency */
977 if(RCU_USARTSRC_HXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)) {
978 usart_freq = HXTAL_VALUE;
979 } else if(RCU_USARTSRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)) {
980 usart_freq = cksys_freq;
981 } else if(RCU_USARTSRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)) {
982 usart_freq = LXTAL_VALUE;
983 } else if(RCU_USARTSRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)) {
984 usart_freq = IRC8M_VALUE;
985 } else {
986 }
987 ck_freq = usart_freq;
988 break;
989 case CK_USART1:
990 /* calculate USART1 clock frequency */
991 if(RCU_USARTSRC_HXTAL == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART1SEL) >> 4U)) {
992 usart_freq = HXTAL_VALUE;
993 } else if(RCU_USARTSRC_CKSYS == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART1SEL) >> 4U)) {
994 usart_freq = cksys_freq;
995 } else if(RCU_USARTSRC_LXTAL == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART1SEL) >> 4U)) {
996 usart_freq = LXTAL_VALUE;
997 } else if(RCU_USARTSRC_IRC8M == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART1SEL) >> 4U)) {
998 usart_freq = IRC8M_VALUE;
999 } else {
1000 }
1001 ck_freq = usart_freq;
1002 break;
1003 case CK_USART2:
1004 /* calculate USART2 clock frequency */
1005 if(RCU_USARTSRC_HXTAL == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART2SEL) >> 6U)) {
1006 usart_freq = HXTAL_VALUE;
1007 } else if(RCU_USARTSRC_CKSYS == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART2SEL) >> 6U)) {
1008 usart_freq = cksys_freq;
1009 } else if(RCU_USARTSRC_LXTAL == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART2SEL) >> 6U)) {
1010 usart_freq = LXTAL_VALUE;
1011 } else if(RCU_USARTSRC_IRC8M == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART2SEL) >> 6U)) {
1012 usart_freq = IRC8M_VALUE;
1013 } else {
1014 }
1015 ck_freq = usart_freq;
1016 break;
1017 default:
1018 break;
1019 }
1020 return ck_freq;
1021 }
1022
1023 /*!
1024 \brief get the clock stabilization and peripheral reset flags
1025 \param[in] flag: the clock stabilization and peripheral reset flags, refer to rcu_flag_enum
1026 only one parameter can be selected which is shown as below:
1027 \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
1028 \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag
1029 \arg RCU_FLAG_PLLSTB: PLL stabilization flag
1030 \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag
1031 \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
1032 \arg RCU_FLAG_BORRST: BOR reset flag
1033 \arg RCU_FLAG_LOCKUPRST: CPU LOCK UP error reset flag
1034 \arg RCU_FLAG_LVDRST: low voltage detect error reset flag
1035 \arg RCU_FLAG_ECCRST: 2 bits ECC error reset flag
1036 \arg RCU_FLAG_LOHRST: lost of HXTAL error reset flag
1037 \arg RCU_FLAG_LOPRST: lost of PLL error reset flag
1038 \arg RCU_FLAG_V11RST: 1.1V domain Power reset flag
1039 \arg RCU_FLAG_OBLRST: option byte loader reset flag
1040 \arg RCU_FLAG_EPRST: external PIN reset flags
1041 \arg RCU_FLAG_PORRST: power reset flag
1042 \arg RCU_FLAG_SWRST: software reset flag
1043 \arg RCU_FLAG_FWDGTRST: FWDGT reset flag
1044 \arg RCU_FLAG_WWDGTRST: WWDGT reset flag
1045 \arg RCU_FLAG_LPRST: low-power reset flag
1046 \param[out] none
1047 \retval none
1048 */
rcu_flag_get(rcu_flag_enum flag)1049 FlagStatus rcu_flag_get(rcu_flag_enum flag)
1050 {
1051 /* get the rcu flag */
1052 if(0U != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) {
1053 return SET;
1054 } else {
1055 return RESET;
1056 }
1057 }
1058
1059 /*!
1060 \brief clear all the reset flag
1061 \param[in] none
1062 \param[out] none
1063 \retval none
1064 */
rcu_all_reset_flag_clear(void)1065 void rcu_all_reset_flag_clear(void)
1066 {
1067 RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
1068 }
1069
1070 /*!
1071 \brief get the clock stabilization interrupt and ckm flags
1072 \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
1073 only one parameter can be selected which is shown as below:
1074 \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
1075 \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
1076 \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
1077 \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
1078 \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
1079 \arg RCU_INT_FLAG_LCKM: LXTAL clock monitor interrupt flag
1080 \arg RCU_INT_FLAG_PLLM: PLL clock monitor interrupt flag
1081 \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
1082 \param[out] none
1083 \retval FlagStatus: SET or RESET
1084 */
rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)1085 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
1086 {
1087 /* get the rcu interrupt flag */
1088 if(0U != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) {
1089 return SET;
1090 } else {
1091 return RESET;
1092 }
1093 }
1094
1095 /*!
1096 \brief clear the interrupt flags
1097 \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
1098 only one parameter can be selected which is shown as below:
1099 \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
1100 \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
1101 \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
1102 \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
1103 \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
1104 \arg RCU_INT_FLAG_LCKM_CLR: LXTAL clock monitor interrupt flag clear
1105 \arg RCU_INT_FLAG_PLLM_CLR: PLL clock monitor interrupt flag clear
1106 \arg RCU_INT_FLAG_CKM_CLR: HXTAL clock monitor interrupt flag clear
1107 \param[out] none
1108 \retval none
1109 */
rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag)1110 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag)
1111 {
1112 RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag));
1113 }
1114
1115 /*!
1116 \brief enable the stabilization interrupt
1117 \param[in] interrupt clock stabilization interrupt, refer to rcu_int_enum
1118 only one parameter can be selected which is shown as below:
1119 \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt
1120 \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt
1121 \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt
1122 \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt
1123 \arg RCU_INT_PLLSTB: PLL stabilization interrupt
1124 \arg RCU_INT_LCKM: LXTAL clock monitor interrupt
1125 \arg RCU_INT_PLLM: PLL clock monitor interrupt
1126 \param[out] none
1127 \retval none
1128 */
rcu_interrupt_enable(rcu_int_enum interrupt)1129 void rcu_interrupt_enable(rcu_int_enum interrupt)
1130 {
1131 RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt));
1132 }
1133
1134 /*!
1135 \brief disable the stabilization interrupt
1136 \param[in] interrupt clock stabilization interrupt, refer to rcu_int_enum
1137 only one parameter can be selected which is shown as below:
1138 \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt
1139 \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt
1140 \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt
1141 \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt
1142 \arg RCU_INT_PLLSTB: PLL stabilization interrupt
1143 \arg RCU_INT_LCKM: LXTAL clock monitor interrupt
1144 \arg RCU_INT_PLLM: PLL clock monitor interrupt
1145 \param[out] none
1146 \retval none
1147 */
rcu_interrupt_disable(rcu_int_enum interrupt)1148 void rcu_interrupt_disable(rcu_int_enum interrupt)
1149 {
1150 RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt));
1151 }
1152
